Indonesi
an
Journa
l
of El
ect
ri
cal Engineer
ing
an
d
Comp
ut
er
Scie
nce
Vo
l.
1
3
,
No.
2
,
Febr
u
ary
201
9
, pp.
8
45
~
852
IS
S
N: 25
02
-
4752, DO
I: 10
.11
591/ijeecs
.v1
3
.i
2
.pp
845
-
852
845
Journ
al h
om
e
page
:
http:
//
ia
es
core.c
om/j
ourn
als/i
ndex.
ph
p/ij
eecs
ASIC
de
sign of l
ow po
wer
-
delay p
ro
du
ct
carr
y pre
-
comp
utation
based m
ulti
pli
er
Chaitany
a C
V
S
1
, S
u
nd
ares
an
C
2,
P
R Ven
ka
t
esw
ar
an
3
, Ke
erth
ana Pr
as
ad
4
1,2,4
School
of
In
f
orm
at
ion
Sci
ences,
Manip
al Academ
y
of
Higher
Educ
a
ti
on,
Mani
pal
,
Karna
ta
k
a
,
I
ndia
.
3
Bhara
t
Hea
v
y
E
le
c
tri
c
al
s
Li
m
it
e
d,
T
iruc
hur
apa
l
li,
T
amil
Nadu
,
In
dia
.
Art
ic
le
In
f
o
ABSTR
A
CT
Art
ic
le
history:
Re
cei
ved
Oct
6
, 2
018
Re
vised
Dec
07
,
2018
Accepte
d
Dec
21
, 201
8
High
spee
d
and
eff
i
ci
en
t
m
ult
i
pli
ers
ar
e
essenti
al
components
in
tod
a
y
’s
computat
ion
al
ci
rcu
it
s
li
k
e
d
igi
tal
signa
l
p
roc
essing,
al
go
rit
hm
s
for
cr
y
p
togra
ph
y
a
nd
high
per
for
m
anc
e
proc
essors
.
Inva
ri
ably
,
al
m
ost
al
l
proc
essing
unit
s
wil
l
contain
h
ar
dware
m
ult
ip
li
er
s
base
d
on
som
e
al
gori
thm
tha
t
f
it
s
th
e
a
ppli
c
at
ion
req
ui
rement
.
Tre
m
e
ndous
adva
nc
es
in
VLSI
te
chno
log
y
over
the
past
sev
era
l
y
e
ars
resulted
in
an
inc
r
ea
sed
n
e
ed
for
high
spee
d
m
ult
iplier
s
and
compelle
d
the
d
esigne
rs
to
go
for
tr
ade
-
offs
among
spee
d,
power
consum
pti
on
a
nd
area.
Am
ongst
var
ious
m
et
hods
of
m
ult
ipl
icati
on
,
Vedic
m
ult
iplier
s
are
gai
ning
gr
ound
due
to
their
expect
e
d
improvem
ent
in
per
form
anc
e
.
A
novel
m
ult
iplier
design
for
high
spee
d
VLS
I
appl
i
ca
t
ions
usi
ng
Urdhva
-
Ti
r
yagbh
y
am
sutra
of
Vedic
Multi
pli
c
at
ion
has
bee
n
pre
sent
ed
in
thi
s
pape
r.
The
proposed
arc
hitect
ur
e
m
odel
ed
using
Veri
log
HD
L,
sim
ula
te
d
using
Cade
nc
e
NCS
IM
and
s
y
n
thes
iz
ed
using
Cade
nc
e
RT
L
C
om
pil
er
with
65
nm
TSMC
li
bra
r
y
.
The
proposed
m
ult
ipl
i
er
arc
hi
te
c
t
ure
is
c
om
par
ed
with
t
he
exi
sting
m
ultipli
ers
and
the
r
esult
s
show
signifi
c
ant
improvem
ent
in
spee
d
and
pow
er
diss
ipa
ti
on
.
Ke
yw
or
d
s
:
Bi
nar
y M
ulti
pl
ic
at
ion
Ca
rr
y P
re C
ompu
ta
ti
on
Mult
ipli
er Arc
hitec
ture
Op
e
ra
nd D
ec
om
po
sit
ion
Ved
ic
M
ulti
plier
Copyright
©
201
9
Instit
ut
e
o
f Ad
vanc
ed
Engi
n
ee
r
ing
and
S
cienc
e
.
Al
l
rights re
serv
ed
.
Corres
pond
in
g
Aut
h
or
:
Chait
anya CV
S
,
School
of In
for
m
at
ion
Science
s,
Ma
nip
al
Acad
e
m
y of
Higher
Ed
ucati
on,
Ma
nip
al
576104, Ka
rn
at
a
ka,
I
nd
ia
.
Em
a
il
:
cha
it
an
ya
.cvs@m
anipal.ed
u
1.
INTROD
U
CTION
Pr
oc
esso
rs
are i
m
po
rtant p
a
rt o
f
integ
rated
ci
rcu
it
s (
IC)
.
La
r
ge
nu
m
ber
s of f
unct
io
nalit
ie
s
are p
acke
d
in
an
IC
tha
nk
s
to
trem
end
ou
s
gro
wth
i
n
de
ns
it
y
of
i
nteg
r
at
ion
in
rece
nt
tim
es.
As
the
nu
m
ber
of
f
unct
ion
s
increases
,
the
need
for
com
pu
ta
ti
on
al
so
grow
s
.
W
it
h
t
he
adv
e
nt
of
ne
w
process
te
ch
nolo
gies,
s
hr
in
ki
ng
of
featur
e
siz
e
an
d
avail
abili
ty
of
m
od
er
n
CA
D
too
ls,
a
dev
el
op
m
ent
of
co
m
plex
integrated
ci
rcu
it
s
f
or
var
i
ou
s
app
li
cat
io
ns
is
po
ssi
ble.
Ex
a
m
ples
of
su
c
h
ap
plica
ti
on
s
inclu
de
di
gital
sign
al
proc
essing
[
1
,
2],
m
ob
il
e
com
pu
ta
ti
on
s
a
nd
c
omm
un
ic
at
ion
s,
m
ultim
e
dia
ap
plica
ti
ons
an
d
proce
ssing
re
qu
ire
d
for
sci
entifi
c
com
pu
ti
ng
and
ap
plica
ti
ons
et
c.
The
s
peed
an
d
e
ff
ic
ie
n
cy
of
proc
essor
in
su
c
h
IC
is
ve
ry
cr
uc
ia
l
fo
r
m
eet
i
ng
the
requirem
ents
of
the
a
pp
li
cat
io
ns
s
upporte
d
by
the
IC.
T
he
s
peed
of
proce
s
so
r
a
nd
ef
fici
ency
of
proce
ss
or
i
n
-
tur
n
de
pe
nds
upon
a
n
arit
hm
et
ic
log
ic
unit
[3
]
w
hich
is
co
ns
ide
red
as
the
m
ai
n
com
pu
ta
ti
o
nal
unit
of
th
e
process
or.
More
ov
e
r,
t
he
m
ulti
plier
unit
s
[4
]
are
th
e
m
os
t
i
m
po
rtant
hard
war
e
struct
ur
es
i
n
a
com
plex
arit
hm
etic
un
it
.
The
m
ulti
pli
er
unit
s
are
c
apab
le
of
perf
or
m
ing
operat
ion
s
on
opera
nd
s
of
va
rio
us
data
ty
pes
su
c
h
as
cal
culat
ing
r
un
ning
s
um
of
pro
duct
s.
As
m
ulti
plica
ti
on
is
a
cru
ci
al
arit
hm
etic
op
erati
on
i
n
process
or
s
[
5]
and
dig
it
al
co
m
pu
te
r
syst
e
m
s,
m
ulti
pliers
a
re
the
co
re
bu
il
ding
bl
ock
for
m
any
al
go
rith
m
s
in
a
wide
va
riet
y
of
c
om
pu
ti
ng
app
li
cat
io
ns
.
Althou
gh
m
ult
ipli
ers
are
m
a
in
arit
h
m
et
ic
com
po
ne
nts
use
d
for
processi
ng
sci
entifi
c
data,
th
e
excessive
po
wer
co
nsum
pti
on
a
nd
delay
at
tract
s
at
te
nti
on
f
r
om
the
research
Evaluation Warning : The document was created with Spire.PDF for Python.
IS
S
N
:
2502
-
4752
Ind
on
esi
a
n
J
E
le
c Eng &
Co
m
p
Sci,
Vo
l.
1
3
, N
o.
2
,
Fe
bru
ary
201
9
:
8
4
5
–
8
5
2
846
com
m
un
it
y.
Usu
al
ly
,
m
ulti
pl
e
arit
hm
et
ic
cor
es
work
i
ng
in
par
al
le
l
are
us
e
d
s
o
as
t
o
proc
ess
la
rg
e
am
ou
nts
of
data with
r
el
a
ti
vely
low po
we
r
a
nd d
el
ay
.
Var
i
ou
s
al
gorithm
s
hav
e
been
pro
po
se
d
for
t
he
hardw
a
re
i
m
ple
m
entat
ion
of
m
ulti
pliers
in
the
past
.
Add
an
d
S
hift
is
the
com
mo
n
al
go
rithm
us
e
d
in
desi
gning
of
m
ulti
pl
ie
r
[6
]
.
I
n
pa
r
al
le
l
m
ul
ti
pliers,
the
i
m
po
rtant
par
a
m
et
er
wh
ic
h
i
s
us
e
d
to
dete
rm
ine
per
f
or
m
ance
is
the
nu
m
ber
of
par
ti
a
l
products
wh
i
ch
are
need
e
d
to
be
add
e
d.
On
e s
uc
h
al
gorithm
is
Mod
ifie
d
Bo
oth
algorit
hm
[
7] w
hich red
uces
the n
um
ber
of p
arti
al
pro
du
ct
s
duri
ng
the
m
ulti
pli
cat
ion
wh
ic
h
in
tu
rn
inc
rea
ses
the
pe
rform
a
nce
of
the
m
ulti
plier.
An
ot
he
r
al
gorithm
is
Wall
ace
tree
based
al
gorithm
wh
ic
h
re
duces
num
ber
of
a
dd
i
ng
sta
ges
an
d
is
us
ed
to
im
pr
ov
e
th
e
sp
ee
d
of
m
ultip
li
cat
ion
.
I
n
s
om
e
i
m
ple
m
ent
at
ion
s,
e
ff
ic
ie
nt
m
ulti
plier
arc
hitec
ture
is
des
ign
e
d
by
com
bin
i
ng
bo
t
h
Mo
di
fied
Boo
th
al
gorit
hm
and
W
al
la
ce
Tree
al
gorithm
.
Ho
we
ver,
an
increasi
ng
par
al
le
li
sm
increases
the
num
ber
of
s
hifts
betwe
en
inte
rm
ediate
su
m
and
pa
rtia
l
products
w
hich
res
ults
in
reduce
d
sp
ee
d,
increase
d
pow
er co
nsum
ption
and also
incr
eased ar
ea bec
ause of
irre
gu
l
ar s
truct
ur
e. T
hu
s
, in
so
m
e c
ases, l
ow
powe
r
a
nd
co
m
pact
m
ult
iplier
arc
hitec
ture
s
is
im
ple
m
en
te
d
usi
ng
se
rial
m
ulti
plica
tio
n
al
gorithm
.
Seria
l
m
ul
ti
pliers
[8
]
hav
e
bette
r
perform
ance
fo
r
powe
r
co
nsum
ption
an
d
area
with
the
delay
trade
off.
De
pe
nd
i
ng
upon the
appli
cat
ion
, eit
her
pa
rall
el
o
r
ser
ia
l
m
ult
ipli
ers
are
selec
te
d
to
p
e
r
form
the o
pe
ra
ti
on
.
Howe
ver,
in
t
he
high
s
pee
d
proces
sors
wh
ic
h
are
operati
ng
at
higher
cl
oc
k
f
re
qu
e
ncies,
the
existi
ng
m
ul
ti
plier
ta
kes
m
or
e
delay
f
or
e
xecu
ti
on
of
the
instru
ct
io
ns.
The
e
xisti
ng
m
ulti
plier
un
it
s
that
con
s
um
e
m
or
e
powe
r
are
no
t
su
it
able
to
be
i
ncor
porated
in
the
process
ors
wh
ic
h
are
us
e
d
in
wi
reless
a
nd
portable
de
vices.
Th
us
, p
ow
e
r
sa
vings is a
n
im
po
rta
nt ar
ea
for
i
m
pr
ovem
ent.
In
order
t
o
ad
dr
ess
t
he
lo
w
powe
r
com
pu
t
at
ion
al
ong
wi
th
high
perfor
m
ance,
a
ne
w
appr
oach
t
o
m
ul
ti
plier
design
base
d
on
a
nc
ie
nt
Ve
dic
Ma
them
atics
has
been
ex
plored
.
The
m
at
he
m
atical
op
erati
ons
us
i
ng
Ved
ic
m
at
he
m
at
ic
s
are
ver
y
f
ast
and
re
quire
le
ss
hardw
a
re.
This
aspect
of
Ved
ic
m
at
hem
at
ic
s
can
be
util
iz
ed
to
increase
the
com
pu
ta
ti
on
al
sp
eed
of
m
ult
ipli
ers.
This
pa
per
descr
i
bes
the
desi
gn
a
nd
i
m
ple
m
entat
io
n
of
a
Ved
ic
m
ulti
pli
er
base
d
on
U
rdh
va
-
Tiry
a
gbhyam
Su
tra
[9]
-
[11].
T
he
nu
m
ber
of
ste
ps
require
d
to
perform
a
m
ul
ti
plica
ti
on
operati
on
by
us
in
g
Urd
hvaTi
ryagbhyam
Su
tra
are
c
on
si
der
a
bly
le
ss
com
par
ed
to
th
e
conve
ntion
al
m
ul
ti
plica
ti
on
te
chn
iq
ues
.
In
this
pap
e
r,
we
hav
e
furthe
r
exp
l
or
e
d
a
nove
l
m
et
ho
d
to
enh
a
nc
e
the
sp
e
ed
of
a
Ve
dic
m
ulti
pl
ie
r
by
pr
e
-
co
m
pu
ti
ng
the
c
arr
ie
s
wh
ic
h
a
re
use
d
duri
ng
su
m
m
ation
of
par
ti
a
l
pro
du
ct
s.
T
he
i
m
ple
m
entat
io
n
of
pr
e
-
c
om
pu
ta
ti
on
lo
gic
usi
ng
m
ulti
plexer
base
d
car
ry
-
look
ahea
d
lo
gi
c
and
XO
R
lo
gic
resu
lt
ed
in
re
duct
ion
of
delay
.
The
pro
pose
d
m
ult
ipli
er
al
ong
with
ope
rand
dec
om
posit
ion
te
chn
iq
ue
resu
l
te
d
in
re
du
ct
i
o
n
of
po
wer
c
onsu
m
ption
wh
i
ch
in
tu
rn
re
duced
the
power
-
delay
pro
du
ct
of
the
m
ul
ti
plier.
The
str
uctur
e
of
the
pap
e
r
is
div
ide
d
as
f
ollows:
The
m
et
ho
dolo
gy
and
the
a
rch
it
ect
ur
e
of
the
pro
po
se
d
m
ultip
li
ers
are
giv
e
n
in
sect
io
n
2.
Re
su
lt
s
are
pre
sented
i
n
sect
ion
3.
Finall
y,
con
cl
us
io
n
is
gi
ven
i
n
sect
ion
4.
2.
RESEA
R
CH MET
HO
D
2.1
.
Ca
rr
y pr
e
-
com
pu
tatio
n based
binar
y
mul
tipli
er
An
8
bit
Bi
nary
Ved
ic
Mult
ipli
er
has
bee
n
pro
po
se
d
with
A
a
nd
B
as
in
puts
a
nd
P
as
t
he
final
16
-
bit
pro
du
ct
.
T
he
blo
c
k
dia
gr
am
for
8
bit
m
ulti
plica
ti
on
is
sh
ow
n
in
F
ig
ur
e
1
.
I
n
the
propose
d
m
ulti
pl
ie
r
the
op
e
ra
nd
s
A an
d
B a
re
div
id
ed
into Hig
he
r
a
nd L
ower
pa
rts
with
4
-
bits eac
h.
A
= {
A
H,
AL}
(1)
B = {B
H, BL}
(2)
AL
*BH
AH*BH
AL
*A
L
AH*
AL
Pr
od
uct
Figure
1
.
Bl
oc
k Diag
ram
o
f
8
-
bit M
ulti
plica
ti
on
In
this
ty
pe
of
m
ult
ipli
er
an
8
bit
Bi
nary
m
ulti
plicatio
n
is
reali
zed
us
in
g
4
-
bit
bin
a
ry
ved
i
c
m
ul
ti
plica
ti
on
us
in
g
car
ry
pr
e
-
co
m
pu
ta
ti
on
l
og
ic
s
how
n
in
belo
w
F
ig
ur
e
2.
wh
e
re
A
3,
A
2,
A
1,
A
0
&
B3,
B2
,
B1,
B
0
a
re
4 bi
t bina
ry in
pu
ts
and P
7,
P6, P
5, P4, P
3, P
2,
P1, P
0
a
re th
e
b
i
na
ry outp
ut
bits.
Evaluation Warning : The document was created with Spire.PDF for Python.
Ind
on
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n
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E
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c Eng &
Co
m
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Sci
IS
S
N:
25
02
-
4752
ASI
C
d
esi
gn o
f
low
po
we
r
-
del
ay pr
oduct c
arry
p
re
-
c
omp
uta
ti
on base
d m
ul
ti
plier
(
Cha
it
an
ya
CVS
)
847
A
3
A
2
A
1
A
0
X
B
3
B
2
B
1
B
0
pp
4
pp
3
pp
2
pp
1
pp
8
pp
7
pp
6
pp
5
pp
12
pp
11
pp
10
pp
9
pp
16
pp
15
pp
14
pp
13
c
32
c
31
c
2
c
42
c
41
c
52
c
51
c
62
c
61
c
71
P
8
P
7
P
6
P
5
P
4
P
3
P
2
P
1
Figure
2.
Ca
rr
y
Pr
e
-
Com
pu
ta
ti
on Based
Mult
ipli
er
The
a
rch
it
ect
ur
e of the
4
-
bit
m
ul
ti
plier can be
unde
rstood
from
the
blo
c
k diag
ram
sh
own
in
Fi
gure
3
.
P
a
r
t
i
a
l
P
r
o
d
u
c
t
s
G
e
n
e
r
a
t
o
r
X
O
R
L
o
g
i
c
P
r
e
-
C
a
r
r
y
L
o
g
i
c
B
[
3
:
0
]
A
[
3
:
0
]
P
r
o
d
u
c
t
[
7
:
0
]
P
P
[
1
5
:
0
]
P
P
[
1
5
:
0
]
P
r
e
-
C
o
m
p
u
t
e
d
C
a
r
r
i
e
s
Figure
3.
A
rch
i
te
ct
ur
e
of
Ca
rry
Pr
e
-
C
om
pu
ta
ti
on
base
d
Mul
ti
plier
The
par
ti
al
pro
du
ct
ge
ner
at
or
is
the
first
blo
c
k
of
t
he
m
ulti
plier
to
w
hich
the
4
bit
m
ulti
plica
nd
a
nd
m
ul
ti
plier
are
giv
e
n
as
input
s.
At
this
j
unc
ture,
the
m
ultip
li
cat
ion
te
ch
ni
qu
e
use
d
is
U
rdh
va
-
Tiry
a
gbhyam
.
T
he
4
bit
m
ultip
li
cat
ion
res
ult
s
in
a
total
of
16
pa
rtia
l
produ
ct
s
(pp1
-
pp16).
The
res
ult
of
m
ul
ti
plyi
ng
an
y
on
e
bin
a
ry b
it
with
ano
t
her is ei
the
r
a ze
ro or a
on
e whic
h
is
sim
ply t
he
lo
gic
of ANDi
ng of t
he
two bits.
The
pro
du
ct
s
of
AL
*BL,
A
H*
BL
,
AL
*BH
,
A
H*
B
H
a
r
e
determ
ined
us
in
g
a
bove
4
-
bit
car
ry
pr
e
-
com
pu
ta
ti
on
ba
sed
m
ulti
plier
an
d
t
he
re
su
lt
s
of
al
l
s
ub
m
ulti
pliers
are
a
dd
e
d
t
o
deter
m
ine
the
fi
nal
pro
du
ct
.
The bloc
k of t
he
8
-
bit m
ulti
pli
er is s
how
n
i
n
F
igure
4.
Evaluation Warning : The document was created with Spire.PDF for Python.
IS
S
N
:
2502
-
4752
Ind
on
esi
a
n
J
E
le
c Eng &
Co
m
p
Sci,
Vo
l.
1
3
, N
o.
2
,
Fe
bru
ary
201
9
:
8
4
5
–
8
5
2
848
4
-
b
i
t
C
a
r
r
y
P
r
e
-
C
o
m
p
u
t
a
t
i
o
n
B
a
s
e
d
M
u
l
t
i
p
l
i
e
r
4
-
b
i
t
C
a
r
r
y
P
r
e
-
C
o
m
p
u
t
a
t
i
o
n
B
a
s
e
d
M
u
l
t
i
p
l
i
e
r
4
-
b
i
t
C
a
r
r
y
P
r
e
-
C
o
m
p
u
t
a
t
i
o
n
B
a
s
e
d
M
u
l
t
i
p
l
i
e
r
4
-
b
i
t
C
a
r
r
y
P
r
e
-
C
o
m
p
u
t
a
t
i
o
n
B
a
s
e
d
M
u
l
t
i
p
l
i
e
r
A
H
B
H
A
H
B
L
A
L
B
H
A
L
B
L
C
a
r
r
y
S
a
v
e
A
d
d
e
r
C
a
r
r
y
L
o
o
k
A
h
e
a
d
A
d
d
e
r
C
a
r
r
y
L
o
o
k
A
h
e
a
d
A
d
d
e
r
P
r
o
d
u
c
t
[
1
5
:
1
2
]
P
r
o
d
u
c
t
[
1
1
:
4
]
P
r
o
d
u
c
t
[
3
:
0
]
A
[
7
:
4
]
A
[
7
:
4
]
A
[
3
:
0
]
A
[
3
:
0
]
B
[
7
:
4
]
B
[
7
:
4
]
B
[
3
:
0
]
B
[
3
:
0
]
P
1
[
7
:
0
]
P
2
[
7
:
0
]
P
3
[
7
:
0
]
P
4
[
7
:
0
]
P
1
[
7
:
4
]
P
4
[
3
:
0
]
C
a
r
r
y
[
7
:
0
]
S
u
m
[
7
:
0
]
C
1
4
'
b
0
0
0
0
Figure
4.
Bl
oc
k Diag
ram
o
f
8
-
bit M
ulti
plier
Using
4
-
bit Ca
rr
y P
re
-
C
om
puta
ti
on
Base
d
M
ulti
plier
The
seco
nd
sta
ge
in
the
bl
ock
diagr
am
is
the
carry
ge
ner
at
ion
ci
rc
uit.
He
r
e,
we
ha
ve
inte
gr
at
e
d
pre
-
com
pu
ta
ti
on
l
og
ic
al
ong
wit
h
the
Urdhva
-
Tiry
agbhyam
m
ul
ti
plica
ti
on
te
chn
iq
ue.
T
he
carry
eq
uatio
ns
a
re
gen
e
rated
sepa
ratel
y
for
eac
h
colum
n
of
par
t
ia
l
products
a
nd
the
in
pu
ts
f
or
these
e
quat
ions
are
ta
ken
f
rom
the
pr
e
vious c
olum
n.
Th
e e
qu
at
i
on
s
for p
re
-
co
m
pu
te
d
carries
are give
n belo
w.
c2
=
pp5 &
pp
2;
(3)
c3t1
=
(p
p6 & pp3
)
| (
pp9 &
(
pp3
|
pp6));
(4)
c3t2
=
(p
p9 & ~
pp6)
|
(pp
3 &
~pp9) |
(
~
pp3 & pp
6)
;
(5)
c31 = c
2
?
c3t
2:
c3t1;
(6)
c32 =
pp2 &
pp5 &
pp3 &
pp
6
&
pp
9;
(7)
c41t
1
=
pp13
?
((
pp10
&
~pp7)|
(
pp4
&
~pp10)
|
(~pp4 &
pp7))
:((
pp7
&
pp4)
|
(pp10
&
(pp4
|
pp7)))
(8)
c41t
2
=
pp13
?
((
~pp7 &
~pp4)|
(
~pp10 &
(~pp4
|
~pp7))):((~pp7 &
pp4)
|
(pp10 & ~pp4)
|
(~pp1
0
&
pp7))
;
(9)
c41 = c
31
?
c
41t
2:c4
1t1
;
(10)
c42
=
((c
31
&
p
p13)
&
((pp
10
&
(pp7
|
pp4))
|
(p
p7
&
pp4)))
|
((p
p10
&
pp7
&
pp
4)
&
(
c31
|
pp13
));
(11)
c51t
1
= c32
?
((p
p14
&
~pp11)|
(
pp8
&
~pp14)
|
(~pp8 &
pp11))
:(
(pp11
&
pp8)
|
(pp14
&
(pp8
|
pp11)));
(12)
c51t
2
=
c32
?
((
~p
p11
&
~pp8)|
(
~p
p14
&
(
~pp8
| ~
p
p11))
):
((
~pp11
&
pp8)
| (pp14
&
~
pp8) | (~p
p14
&
p
p11))
;
(13)
c51 = c
41
?
c
51t
2:c5
1t1
;
(14)
Evaluation Warning : The document was created with Spire.PDF for Python.
Ind
on
esi
a
n
J
E
le
c Eng &
Co
m
p
Sci
IS
S
N:
25
02
-
4752
ASI
C
d
esi
gn o
f
low
po
we
r
-
del
ay pr
oduct c
arry
p
re
-
c
omp
uta
ti
on base
d m
ul
ti
plier
(
Cha
it
an
ya
CVS
)
849
c52
=
((c
41
&
c
32)
&
((pp1
4
&
(pp11
|
pp8))
|
(pp11
&
pp8))
)
|
((
pp14
&
pp11
&
pp8)
&
(
c41
|
c3
2));
(15)
c6t1
=
(p
p12 & pp
15)
|
(c42
& (p
p12
|
pp15
))
;
(16
)
c6t2
=
(
c
42 &
~pp1
5)
| (
pp12
& ~c4
2) | (
pp15&~
pp12);
(17)
c61 = c
51
?
c
6t
2:
c6t1;
(18)
c62 = c
51 &
c
42 & p
p12 &
pp15;
(19)
c71 =
(c52
&
pp16
)
| (c
61 &
(c
52 | pp
16))
;
(20)
The
thir
d
sta
ge
in
the b
lock diagram
inv
olv
e
s the u
se of XOR log
ic
for
th
e
par
ti
al
p
rod
uc
ts and
car
ry
gen
e
rated
in
e
ach
c
olu
m
n.
T
he
ou
t
put
of
t
his
sta
ge
giv
e
s
the
final
16
bit
pro
duct
w
hich
is
obta
in
ed
i
n
a
par
al
le
l m
echan
ism
instead of
seque
ntial
m
e
chan
ism
.
2.2
.
Ca
rr
y pr
e
-
com
pu
tatio
n based
binar
y
mul
tipli
er u
sing oper
an
d
decom
po
si
tio
n
In
ope
rand
dec
om
po
sit
ion
[
12]
,
the
op
e
ra
nds
X
an
d
Y
ar
e
deco
m
po
se
d
into
fou
r
num
ber
s
A,
B,
C
and
D
to
re
duc
e
the
nu
m
ber
of
on
es
in
the
pa
rtia
l
pr
od
ucts.
The
oper
an
ds
are
dec
om
po
se
d
in
s
uch
a
wa
y
tha
t
the
num
ber
of
zero
s
in
dec
ompo
s
ed
opera
nd
will
be
m
or
e
w
hen
com
par
e
d
to
num
ber
of
ones.
As
the
nu
m
ber
of
ze
ro
s
a
re
m
or
e
,
the
switc
hi
ng
act
ivit
y
of
the
ci
rcu
it
wi
ll
be
reduced
wh
ic
h
in
tu
rn
reduce
the
dynam
ic
powe
r
c
on
s
umpti
on of t
he
a
rc
hitec
ture.
Assum
ing
that
the tw
o op
e
ra
nds a
re
X
a
nd Y ha
ve n
bits,
X
=
[Xn
-
1Xn
-
2.
.
.....
X1X
0], a
nd
Y
=
[Yn
-
1Yn
-
2.
.
.....
Y1Y
0]
(21)
The fo
ur
decom
po
sed op
e
rands
a
re
giv
e
n
in
the foll
owin
g
A
= ~
X
Λ
~Y,
B = X Λ
Y,
C = ~X Λ
Y, a
nd
D
=
X
Λ
~Y
(22)
Wh
e
re,
Λ is a
nd
op
e
rati
on &
~ i
s two’s c
omplem
ent
The final
pro
duct
is
determ
ined by u
sin
g
e
quat
ion 2
3.
X*Y
=
(
C
* D)
-
(A * B
);
(23)
The
pr
oducts
of
C
*D
a
nd
A
*B
are
dete
rm
i
ned
us
in
g
8
-
bit
carry
pr
e
-
c
om
pu
ta
ti
on
bas
ed
m
ulti
plier.
The
n
the
final
par
ti
al
s
um
a
nd
car
ry
f
ro
m
bo
t
h
products
can
be
c
om
bin
ed
ca
rr
y
sa
ve
add
e
r
a
nd
car
r
y
look
ahead ad
de
r.
T
he bloc
k diag
r
a
m
f
or ab
ove
m
ul
ti
plier is sh
own
i
n
F
i
gure
5.
3.
RESU
LT
S
A
ND AN
ALYSIS
The
pro
posed
arc
hitec
ture
m
od
el
ed
us
i
ng
Ve
rilog
H
DL
,
sim
ulate
d
usi
ng
Ca
de
nce
NCSI
M
a
nd
synthesiz
ed
us
i
ng
C
ade
nce
R
TL
Com
piler
with
65nm
TSMC
li
br
ary.
Di
ff
e
ren
t
im
ple
m
entat
ion
m
et
hodo
l
og
y
hav
e
bee
n
ta
ke
n
an
d
im
plem
ented
in
sam
e
te
chnolo
gica
l
env
ir
onm
ent
and
t
hen
c
om
par
ed
t
he
pe
rfo
r
m
ance
par
am
et
ers.
F
or
t
he
c
om
par
ison
point
of
view
t
he
idea
s
ha
ve
been
c
on
si
der
e
d
fro
m
the
ref
e
rence
s
a
nd
si
m
ulate
d
and
perform
ance
par
am
et
ers
was
com
pu
te
d
us
i
ng
the
sam
e
M
OS
FE
T
te
chno
log
y
file
.
Inp
ut
data
was
ta
ken
in
a
regular
fas
hion
f
or
e
xperim
ental
purpose.
T
he
delay
an
d
t
he
powe
r
m
easure
d
us
in
g
t
he
w
or
st
-
case patt
er
n
a
nd
from
the
ou
t
pu
t
w
her
e
the
delay
is m
axi
m
um
.
It
is
ob
se
r
ved
that
the
pro
pos
ed
ca
rr
y
pr
e
-
c
om
pu
ta
ti
on
ba
sed
m
ulti
plier
and
car
ry
pr
e
-
com
pu
ta
ti
on
base
d
m
ulti
pli
er
with
opera
nd
dec
om
po
sit
ion
offe
red
s
ub
sta
ntial
reducti
on
of
pro
pa
ga
ti
on
delay
a
nd
total
powe
r
c
on
s
umpti
on
s.
F
r
om
T
able
1
an
d
T
ab
le
2,
it
ca
n
be
ob
s
er
ved
that
t
he
pro
po
se
d
ca
rr
y
pr
e
-
com
pu
t
at
ion
base
d
m
ulti
pli
er
desi
gn
offe
r
ed
~2
3%,
~6
4%
,
~5
7%,
~
83
%,
~9
4%
wh
e
n
com
par
e
d
w
it
h
arr
ay
m
ultip
li
er,
wall
ace
m
ult
ipli
er,
colum
n
ba
sed
m
ulti
plier,
Nikhil
am
based
a
nd
c
om
pr
e
sso
r
base
d
m
ulti
pliers
res
pecti
vely
,
and
car
ry
pr
e
-
c
om
pu
ta
ti
on
ba
sed
m
ulti
plier
with
opera
nd
de
com
po
sit
ion
offer
e
d
~4
1%,
~72
%
,
~67%,
~87
%
,
Evaluation Warning : The document was created with Spire.PDF for Python.
IS
S
N
:
2502
-
4752
Ind
on
esi
a
n
J
E
le
c Eng &
Co
m
p
Sci,
Vo
l.
1
3
, N
o.
2
,
Fe
bru
ary
201
9
:
8
4
5
–
8
5
2
850
~95
%
w
he
n
c
om
par
ed
with
arr
ay
m
ulti
plier
,
wall
ace
m
ul
ti
plier,
col
um
n
base
d
m
ulti
plier,
Ni
khil
a
m
base
d
and com
pr
ess
or
based m
ulti
pl
ie
rs
res
pecti
vel
y.
O
p
e
r
a
n
d
D
e
c
o
m
p
o
s
e
r
8
-
b
i
t
C
a
r
r
y
P
r
e
-
C
o
m
p
u
t
a
t
i
o
n
B
a
s
e
d
M
u
l
t
i
p
l
i
e
r
8
-
b
i
t
C
a
r
r
y
P
r
e
-
C
o
m
p
u
t
a
t
i
o
n
B
a
s
e
d
M
u
l
t
i
p
l
i
e
r
C
a
r
r
y
S
a
v
e
A
d
d
e
r
X
[
7
:
0
]
Y
[
7
:
0
]
A
[
7
:
0
]
B
[
7
:
0
]
C
[
7
:
0
]
D
[
7
:
0
]
P
r
o
d
1
[
1
5
:
0
]
P
r
o
d
2
[
1
5
:
0
]
P
r
o
d
u
c
t
[
1
5
:
0
]
Figure
5.
Ca
rr
y
Pr
e
-
Com
pu
ta
ti
on Based
Mult
ipli
er U
si
ng Opera
nd
Deco
m
po
sit
io
n
Table
1.
Su
m
m
ary
of Sy
nth
esi
s Result
s
o
f
8
-
Bi
t M
ulti
plier A
rc
hitec
tures
S.No
Architectu
re
(
8
-
b
it
)
Delay
(ns
)
Dy
n
a
m
i
c
Po
wer
(u
W
)
Static Powe
r
(uW)
Total Po
wer
(uW)
Po
wer
-
D
elay
Prod
u
ct (
p
J)
1
Arr
a
y
Based
Multi
p
lier
[
6
]
1
.5
1
5
.09
6
2
1
.09
3
1
.63
2
W
allac
e Based
Multip
lier
[
2
]
1
.2
6
.27
4
9
.91
3
5
6
.18
4
6
7
.42
3
Co
lu
m
n
Based
Multip
lier
[
9
]
1
.95
2
6
.74
2
.8
2
9
.54
5
7
.6
4
Nik
h
ila
m
Based
M
u
ltip
lier
[
1
0
]
3
.2
4
2
.56
4
.3
4
6
.86
1
4
9
.95
5
Co
m
p
r
ess
o
r
Bas
ed
M
u
ltip
lier
[
1
1
]
4
.02
9
5
.2
6
.79
1
0
1
.99
4
1
0
.92
6
Pre
-
Co
m
p
u
tatio
n
Bas
ed
M
u
ltip
lier
0
.75
2
5
.77
7
.45
3
3
.23
2
4
.23
7
Pre
Co
m
p
u
tatio
n
Bas
ed
M
u
ltip
lier
with
Operand
Dec
o
m
p
o
sitio
n
1
.02
3
.36
1
4
.80
8
1
8
.17
2
1
8
.5
Table
2.
Su
m
m
ary
of Sy
nth
esi
s Result
s
o
f
16
-
Bi
t M
ulti
plier
Ar
c
hitec
tures
S.No
Architectu
re
(
1
6
-
b
it)
Delay
(ns
)
Dy
n
a
m
i
c
Po
wer
(u
W
)
Static Powe
r
(uW)
Total Po
wer
(uW)
Po
wer
-
D
elay
Prod
u
ct (
p
J)
1
Arr
a
y
Based
Multi
p
lier
[
6
]
2
.89
3
0
.18
12
4
2
.18
1
2
1
.90
2
W
allac
e Based
Multip
lier
[
2
]
2
.46
1
2
.54
9
9
.82
6
1
1
2
.366
2
7
6
.42
3
Co
lu
m
n
Based
Multip
lier
[
9
]
3
.82
5
2
.48
5
.4
5
7
.88
2
2
1
.10
4
Nik
h
ila
m
Based
M
u
ltip
lier
[
1
0
]
5
.96
8
0
.65
8
.1
8
8
.75
5
2
8
.95
5
Co
m
p
r
ess
o
r
Bas
ed
M
u
ltip
lier
[
1
1
]
8
.04
1
9
0
.4
1
3
.58
2
0
3
.98
1
6
3
9
.9
9
6
Pre
-
Co
m
p
u
tatio
n
Bas
ed
M
u
ltip
lier
1
.4
5
1
.54
1
4
.9
6
6
.44
9
3
.01
6
7
Pre
Co
m
p
u
tatio
n
Bas
ed
M
u
ltip
lier
with
Operand
Dec
o
m
p
o
sitio
n
1
.96
6
.72
2
9
.61
6
3
6
.33
6
7
1
.21
8
Fr
om
the
Ta
bl
e
1
an
d
T
able
2,
it
ca
n
be
ob
serv
e
d
t
hat
ca
r
ry
pre
-
c
om
pu
ta
ti
on
base
d
m
ulti
plier
with
op
e
ra
nd
decom
po
sit
ion
con
s
um
es
le
ss
po
w
er
wh
e
n
com
par
ed
to
car
ry
pre
-
c
om
pu
ta
ti
on
based
m
ulti
pli
er
wit
h
the
delay
tra
de
off.
P
r
opos
e
d
C
arr
y
pre
-
c
ompu
ta
ti
on
based
m
ulti
plier
with
ope
rand
dec
om
po
sit
ion
ga
ve
the
bette
r
powe
r
-
de
la
y
product
w
hen
c
om
par
ed
to
propose
d
ca
rr
y
pr
e
-
c
om
pu
ta
ti
on
base
d
m
ulti
plier
a
nd
e
xisti
ng
m
ul
ti
plier f
r
om l
it
eratu
re.
Evaluation Warning : The document was created with Spire.PDF for Python.
Ind
on
esi
a
n
J
E
le
c Eng &
Co
m
p
Sci
IS
S
N:
25
02
-
4752
ASI
C
d
esi
gn o
f
low
po
we
r
-
del
ay pr
oduct c
arry
p
re
-
c
omp
uta
ti
on base
d m
ul
ti
plier
(
Cha
it
an
ya
CVS
)
851
4.
CONCL
US
I
O
N
In
t
his
pa
per,
a
Ve
dic
m
a
t
hem
atics
base
d
m
ulti
plier
has
bee
n
pr
opose
d
wh
ic
h
use
s
Ca
rr
y
pr
e
-
com
pu
ta
ti
on
a
nd
ope
rand
de
com
po
sit
ion
m
et
hodo
l
og
y.
T
he
pro
po
se
d
ar
chite
ct
ur
e
c
ombines
the
be
ne
fits
of
Ved
ic
m
et
ho
d,
par
al
le
l
pr
e
-
c
om
pu
ta
ti
on
of
carr
ie
s,
an
d
ope
rand
dec
om
po
s
it
ion
there
by
resu
lt
ing
in
re
duct
io
n
of
powe
r
-
delay
product.
T
he
pro
pag
at
io
n
de
la
y
of
carry
pre
-
com
pu
ta
ti
on
base
d
m
ulti
pli
er
f
or
cal
culat
i
on
of
8
bit
an
d
16
bit
m
ul
ti
plica
ti
on
was
0.7
5n
s
an
d
1.4ns
w
hile
powe
r
c
on
s
umpti
on
wa
s
33.23
uW
an
d
66.
44
uW.
The
pro
pag
at
i
on
delay
of
ca
rry
pr
e
-
com
pu
ta
t
ion
base
d
m
ulti
plier
with
ope
rand
dec
om
po
sit
ion
f
or
cal
cul
at
ion
of
8
bit
and
16
bit
m
ult
ipli
cation
was
1.02ns
and
1.9
6ns
w
hile
power
c
onsu
m
ption
was
18.17
uW
an
d
36.13
uW.
T
he
delay
of
m
ulti
plica
t
ion
was
decre
ased
by
~6
8%
an
d
powe
r
consum
ption
was
reduce
d
by
~61
%
wh
e
n
c
om
par
e
d
to
N
i
kh
il
am
b
ase
d Ved
ic
m
ulti
plier.
REFERE
NCE
S
[1]
Xiangui
Kang,
Anjie
Peng,
Xi
an
y
uXu,
Xi
aoc
hun
Cao,
Perform
in
g
Scal
ab
le
Loss
y
Com
pre
ss
ion
O
n
Pixel
En
cr
y
pt
e
d
Im
age
s,
EURAS
IP Journal
on
Im
age
and
Vid
eo
P
roc
essing,
(2013
),
pp
.
1
-
6.
[2]
Nikolay
Ponom
a
ren
ko,
Serg
e
y
K
rive
nko,
Vladi
m
ir
Luki
n
,
Ka
ren
Egi
a
za
ri
an,
Jaa
k
ko
T,
As
tol
a
,
Lo
ss
y
Com
pre
ss
ion
of
Noisy
Im
ages
Based
on
Vis
ual
Quali
t
y
:
A
C
om
pre
hensive
Stud
y
,
EURAS
IP
Journal
on
A
dvanc
es
in
Signa
l
Proce
ss
ing,
(201
0),
pp
.
1
-
13
.
[3]
L.
-
K.
W
ang,
M.
A.
Erl
e
,
C.
Tse
n,
E.
M.
Schwar
z,
and
M.
J.
Sc
hult
e
,
A
surve
y
of
har
dware
des
igns
for
dec
ima
l
ari
thmet
ic
,
IBM
Journal
of
R
ese
a
rch
and
Deve
lop
m
ent
,
54
(2)
(20
10),
pp
.
8:1
-
8
:15
.
[4]
M.
Jee
vit
h
a,
R
.
Muthai
ah
,
P.
Sw
aminat
han,
Eff
icient
Mul
tiplie
r
Arch
it
e
ct
u
re
in
VLSI
De
sign,
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o
f
The
ore
ti
c
al a
nd
Applie
d
Inform
a
ti
on
Te
chno
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38
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(2012)
,
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196
-
201
.
2
[5]
J.
R.
Boddie,
G
.
T.
D
ar
y
ana
n
i,
I.
I.
El
dum
ia
t
i,
R.
N,
Gade
n
z,
J.
S.
Thomps
on,
S.
M.
W
al
t
er
s,
Digit
a
l
Signa
l
Proce
ss
or:
Archi
te
c
ture
and
Per
f
orm
anc
e, Be
l
l
S
y
stem
Te
chn
ical
Journal, 60 (7)
(
1981),
pp
.
1449
-
1462.
[6]
Ko
-
Chi
Kuo,
Chi
-
W
en
Chou,
Low
Pow
er
And
H
igh
Speed
Multi
pli
er
Design
W
it
h
Row
By
p
assing
And
Para
ll
el
Archi
tectur
e
,
Mi
cro
elec
tron
ic
s Jo
urna
l, 41
(2010)
,
pp.
639
-
650.
[7]
Constant
inos
Ef
stat
hiou
,
N.
M
oshopolous,
N.
Axelos,
K.
Pe
km
estz
i,
E
fficie
nt
Modulo
2n+
1
Multi
pl
y
An
d
Multi
pl
y
-
Add U
nit
s Ba
sed
On M
odifi
ed
Booth E
ncodi
ng,
Int
egr
a
ti
on,
the VLSI J
ourna
l, 47
(2014
),
pp
.
140
-
147
.
[8]
Mana
s
Ranj
an
Mehe
r,
Ching
C
huen
Jong,
and
Chip
-
Hong
Chang,
“
A
High
Bit
Rat
e
Serial
-
Seri
al
Multi
pl
ie
r
W
i
th
On
-
the
-
Fl
y
Ac
c
um
ula
ti
on
b
y
As
y
nchr
onous
Cou
nte
rs”,
IE
EE
trans
.
On
VLSI
sy
stems
,
Vol.
19,
No.
10,
pp.
1733
-
1745,
Octob
er,
2
011.
[9]
Bhara
t
iKrsnaT
ir
tha
ji
,
V
.
S Agra
wala
,
“
Vedic Ma
the
m
at
i
cs”
,
13th Edi
ti
on
,
Mot
il
a
l Bana
rsidass,
201
0.
[10]
P.
Saha,
A.
Ban
erj
e
e,
A.
Dand
a
pat
,
and
P.
Bhattac
h
ar
yy
a
,
“
AS
I
C
design
of
a
high
spee
d
low
p
ower
ci
rcu
it
for
fac
tor
ia
l
c
alculat
ion
using
anc
ie
n
t
Vedic
m
at
hematics”,
EL
SEVI
ER
Microe
l
ec
tro
nic
s
Journal,
vol
.
42,
issue
12,
pp.
1343
-
1352,
De
c
ember,
2011
.
[11]
MD
.
Bel
al
Rash
id,
Balaji
B.
S
an
d
Pro
f.
M.B.
Ananda
ra
ju,
“
VLSI
Design
and
Im
p
le
m
ent
a
ti
on
of
Bina
r
y
Multi
pl
ie
r
base
d
on
UrdhvaT
ir
y
a
gbh
y
am
Sutra
with
red
uc
e
d
Delay
and
Are
a”
,
Int
ern
a
ti
ona
l
Journal
of
Engi
nee
ring
Rese
arch
and
T
ec
hnolo
g
y
,
vol. 6, no. 2, pp. 269
-
278,
Marc
h
,
2013
.
[12]
Riz
wan
Mudass
ir,
Mohab
Anis,
and
Javid
Jaffa
r
i
,
“
Sw
it
chi
ng
Act
ivi
t
y
Redu
ct
ion
i
n
Low
Pow
er
bo
oth
Multi
plier”
,
IEE
E
S
y
m
posiu
m
on
Circ
ui
ts a
n
d
S
y
stems
,
Se
att
le
,
vol
.
1
,
pp
.
33
06
-
3309,
Ma
y
,
2
008.
BIOGR
AP
HI
ES OF
A
UTH
ORS
Chai
ta
n
y
a
CVS
rec
e
ive
d
h
is
Ba
che
lor
Degre
e
i
n
Elec
tron
ic
s
an
d
Com
m
unic
at
io
n
Engi
n
ee
ring
i
n
2006
from
JN
T
U,
Hy
d
era
b
ad
a
nd
his
M
S
degr
ee
in
VLSI
-
CAD
from
Manipa
l
U
nive
rsit
y
in
200
7.
In
2010,
he
st
arted
his
ca
r
ee
r
as
As
sistant
Profess
or
in
School
Of
Inform
at
i
on
Sc
ie
nc
es,
Manip
al
.
Curre
ntly
,
h
e
is doi
ng
Ph.D a
t
M
ani
pa
l
Univer
sit
y
.
His re
sea
r
ch
i
nte
rest
in
cl
udes
High
Perform
anc
e
Com
pute
r
Arith
m
et
ic
,
Adv
anc
e
d
Com
pute
r
Archi
t
ec
tur
e,
Low
-
power
VLSI
Design,
E
lectr
oni
c
Design
Autom
ation,
and
Par
al
l
el
Algorit
hm
s/Archi
tectur
es.
Dr
.
C
Sun
dar
e
san
com
plete
d
Ba
chelor
degre
e
in
Ele
ct
ro
nic
s
and
Com
m
un
ic
at
ion
in
2000
from
Ma
du
rai
Kam
araj
Un
i
ve
rsity
and
MS
degree
in
VL
S
I
CAD
in
20
03
from
Ma
nip
a
l
Un
i
ver
sit
y
an
d
PhD
i
n
2018
f
ro
m
Ma
nip
al
Acad
em
y
of
H
igh
e
r
E
du
cat
i
on.
He
sta
rted
hi
s
career
as
R
&
D
en
gin
ee
r
at
Ap
la
b
Ltd.
C
urren
tl
y
he
is
work
i
ng
as
Assistant
Profess
or
i
n
School
O
f
I
nfor
m
at
ion
Scie
nces.
His
rese
arch
inter
est
s
inclu
des
Com
pu
te
r
A
rithm
et
i
c,
Lo
w
-
P
ower
VLSI
Desi
gn, L
og
ic
Synthe
si
s,
Stat
ic
Ti
m
ing
An
al
ysi
s.
Evaluation Warning : The document was created with Spire.PDF for Python.
IS
S
N
:
2502
-
4752
Ind
on
esi
a
n
J
E
le
c Eng &
Co
m
p
Sci,
Vo
l.
1
3
, N
o.
2
,
Fe
bru
ary
201
9
:
8
4
5
–
8
5
2
852
Dr.
P.
R
.
Ven
kat
eswara
n
obt
a
ine
d
h
is
ba
che
l
or’s
degr
e
e
in
El
e
ct
roni
cs
and
Instrum
ent
atio
n
Engi
ne
eri
ng
fro
m
Nati
onal
Enginee
ring
Col
le
ge
,
Kovilpa
tt
i
in
1998
and
Master
s
in
Instrum
ent
at
io
n
and
Control
En
gine
er
ing
from
Te
chn
ic
a
l
T
ea
c
her
s’
Tra
in
ing
I
nstit
ute,
Chand
i
gar
h
in
2002.
He
complet
ed
h
is
doct
ora
l
rese
arc
h
in
2008
from
Manipal
Univer
sit
y
,
Manipal.
He
s
ta
rt
ed
his
caree
r
as
te
a
chi
ng
fac
u
lty
at
Sethu
Instit
ut
e
of
Te
chnol
og
y,
Madura
i
and
c
onti
nued
his
te
a
chi
ng
ca
r
ee
r
wit
h
Te
chn
ic
a
l
T
each
ers’
Tra
in
ing
In
stit
ute,
Chand
ig
arh
and
l
ater
a
t
Manipa
l
Inst
it
ut
e
of
T
ec
hnolog
y,
Manipa
l
.
Presently
,
he
is
worki
ng
as
Senior
Engi
nee
r
(Contro
l
and
Instrum
ent
a
ti
on)
at
W
el
din
g
Resea
rch
Insti
tu
te
,
BHEL
,
Ti
ru
c
hira
ppa
ll
i
and
is
associa
te
d
in
th
e
areas
of
W
el
ding
Autom
at
ion
and
W
el
ding
Pow
er
Source
s.
His
are
as
of
int
ere
st
are
l
i
nea
r
Control
t
heor
y
,
E
le
c
tron
ic
Instrum
ent
at
ion
and
Soft
Com
puti
ng
Techni
qu
es.
He
has
bee
n
a
rev
ie
wer
for
jou
rna
ls
li
ke
I
EEE
SM
C,
El
sevi
er,
AM
SE
et
c. He
is
a
m
ember
o
f
pr
ofe
ss
iona
l
bod
ies
of
ISTE
,
IW
S
and
IE
.
Dr.
Kee
rth
ana
Prasad
is
workin
g
as
Profess
or
i
n
School
of
Inf
orm
at
ion
Sci
ences,
a
constituen
t
insti
tution
of
M
ani
pa
l
Univer
si
t
y
.
Her
r
ese
a
r
ch
int
er
ests
are
ima
ge
an
aly
sis
and
it
s
applic
at
ions
i
n
m
edi
ci
ne
and
hi
gh
per
form
ance com
puti
ng
appr
o
ac
h
for
image
pr
oce
ss
ing.
Evaluation Warning : The document was created with Spire.PDF for Python.