TELKOM
NIKA
, Vol. 11, No. 8, August 2013, pp. 44
7
0
~4
476
e-ISSN: 2087
-278X
๏ฎ
4470
Re
cei
v
ed Ma
rch 1
5
, 2013;
Re
vised Ma
y 14, 2013; Accepted Ma
y 24
, 2013
0.18
ฮผ
m CMOS Low Voltage Power Amplifier for WSN
Application
Wu Ch
enjian
,
Li Zhiqun*,
Yao Nan, Zh
ang Meng, Chen Liang, Cao Jia
Institute of RF
- & OE-ICs, Southeas
t Un
iver
sit
y
, Nan
j
i
ng, 2
100
96
Engi
neer
in
g R
e
searc
h
Cent
e
r
of RF
-ICs &
RF
-S
y
s
tems
, Ministr
y
of Edu
c
ation, Sout
he
ast Univers
i
t
y
,
Nanj
in
g, 210
09
6
Jian
gsu Provi
n
cial Ke
y L
a
b
o
rator
y
of sensor
net
w
o
rk techn
o
lo
g
y
, W
u
xi, 2
141
35
*Corres
p
o
ndi
n
g
author: zhi
q
u
n
li@s
eu.e
du.c
n
A
b
st
r
a
ct
T
h
is pa
per pr
e
s
ents the d
e
si
gn of a C
l
ass
A/B pow
er amplifier (PA) for
2.4-2.48
35GH
z
W
i
reles
s
Sensor Network (WSN) syste
m
in
0.18
ฮผ
m C
M
OS technol
o
g
y. T
he PA ad
opts the sin
g
le
-stage differ
ent
ia
l
structure an
d the o
u
tput pow
er of the PA can b
e
contro
lle
d by sw
it
ching
the si
z
e
s of transistors. Sev
e
n
different lev
e
l
of output pow
e
r
can
be obtai
n
ed throu
gh a three-
bit cont
rol
code. T
he tested results sh
o
w
s
that the pro
pos
ed PA ac
hi
eve
s
pow
er ad
de
d
efficien
cy (PA
E
) of 26.73
%
w
h
ile d
e
liv
erin
g an
outp
u
t po
w
e
r
of 6.35d
Bm at
1dB co
mpressi
on p
o
int. Its po
w
e
r gain
is
1
5
.87dB. W
i
th a
l
o
w
DC volta
g
e
supp
ly of 1V, i
t
s
pow
er consu
m
ption is 1
5
.3
mW
. T
he PA die si
z
e
is 10
70ร
6
1
0
ฮผ
m
2
.
Ke
y
w
ords
:
class AB, PA,
WS
N, PAE, low vo
ltage
Copy
right
ยฉ
2013 Un
ive
r
sita
s Ah
mad
Dah
l
an
. All rig
h
t
s r
ese
rved
.
1. Introduc
tion
Wirel
e
s
s
sen
s
or
netwo
r
k
[1] (WSN
)
is
a se
lf-org
ani
zing n
e
two
r
k which co
nsi
s
ts of a
large
numb
e
r
of se
nsors using
wirel
e
ss commu
nic
a
tion tec
h
nologies
. Its
purpose is
t
o
coo
peratively perceive,
col
l
ect an
d p
r
o
c
ess info
rmati
on of target
i
n
the n
e
two
r
k a
r
ea, a
nd t
hen
the informatio
n is delive
r
ed
to obse
r
ver.
It c
an be ap
p
lied to variou
s area of env
ironm
ental an
d
ecol
ogi
cal
co
ntrol, medi
cal
,
home a
u
to
mation, traffi
c cont
rol, etc.
It is co
nsi
dered to be
a h
uge
impact in the
21st century
technol
ogy. With the
ra
pi
d develop
me
nt of wirele
ss commu
nications
and mi
cro-el
ectro
n
ics te
chnolo
g
y, hig
h
ly integr
ate
d
, low po
we
r and
lo
w-co
st the CMOS
[2
]
wirel
e
ss
RF
transceive
r
chip ha
s b
e
e
n
more an
d
more
appli
e
d in pe
opleโ
s daily life a
n
d
indu
strial p
r
o
ductio
n
of ele
c
troni
c devi
c
e
s
, the market potential is h
uge [3, 4].
As the core p
a
rt of the wi
reless
comm
u
n
icat
io
n sy
ste
m
in WS
N, the tran
sceiver
(Figu
r
e
1) ha
s bee
n the focu
s of the resea
r
ch in
recent
years. Powe
r amplifi
e
r lo
cated at the end pa
rt of
transmitter is
one of the ke
y modules of the trans
mitter. It amplifies radio freque
n
c
y (RF
)
sig
n
a
l
from mixer,
and d
e
livers
the sig
nal to
antenn
a fo
r
transmitting. Its function
is to imp
r
ove
the
ability of anti-interference
of t
he
RF
signal. Therefore, the perf
ormance of
PA is
closely
rel
a
ted
with the com
m
unication q
uality of a communi
cation
system.
Figure 1. Block
Diag
ram o
f
the Transcei
v
er
ย
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
e-ISSN:
2087
-278X
๏ฎ
0.18
ฮผ
m
CMOS Low Voltag
e Powe
r Am
plifier
for WS
N Application
(Wu Chenji
an)
4471
This
pap
er prese
n
ts th
e d
e
sig
n
of
a po
wer
am
plifier (PA)
fo
r Wire
les
s
Sen
s
o
r
Netw
o
r
k
(WS
N)
sy
st
e
m
in TS
MC
0.
18
ฮผ
m RF
CMOS te
chn
o
logy. Beca
u
s
e of the
re
quire
ment of
low
power co
nsu
m
ption
fo
r WSN system,
t
h
is po
we
r a
m
plifier
doe
snโt nee
d hi
gh
po
we
r g
a
in
and
output p
o
wer.
Ho
weve
r, hi
gh effici
en
cy
[5] is the
key target
and
p
o
we
r
cont
rol i
s
n
eed
ed. After
the tradeoff b
e
twee
n efficie
n
cy, output p
o
we
r gain
a
n
d
, a fully diffe
rential si
ngle
stage
Cla
ss
A/B
[6] casco
de
stru
cture is
adopte
d
and
power
contro
l is reali
z
ed
by controllin
g the switch
of
transi
s
to
rs. T
he pro
p
o
s
ed
PA has high
e
r
effici
en
cy under a lo
w DC voltage sup
p
ly of 1V.
This pa
per i
s
orga
nized a
s
follows. Section
II discu
sses pri
n
ci
ple
s
and the de
sig
n
of the
proposed PA
. Section III shows the m
i
crophotogra
ph of the proposed PA and descri
b
es the
experim
ental
results of the
prop
osed PA. Fina
lly, concl
u
sio
n
s a
r
e gi
ven in Sectio
n IV.
2. Po
w
e
r
Am
plifier Design
T
h
e
pr
op
os
ed
PA is sh
ow
n
in
F
i
gu
re 2
.
M
2
, M
4
, M
6
, M
8
, M
10
and
M
12
are po
we
r
trans
is
tors
. M
1
, M
3
, M
5
, M
7
, M
9
and
M
11
are switch trans
is
tors
. L
d1
and
L
d2
are
radio
fre
quen
cy
cho
k
e (RF
C
), and they a
r
e load
of the powe
r
tran
sisto
r
s. R
1
a
nd R
2
are st
ability adjusti
ng
resi
st
o
r
s.
C
g1
, L
g1
and
C
g2
, L
g2
are
in
p
u
t matching
netwo
rk.
C
g3
, L
g3
an
d
C
g4
, L
g4
are
outp
u
t
matchin
g
net
work. R0 a
n
d
M0 are comp
ose
d
of a bia
s
ci
rcuit of th
e PA.
Figure 2. The
Propo
sed Po
wer Amplifie
r
2.1. Size and
Bias of Po
w
e
r Transis
t
or
The si
ze of p
o
we
r tran
si
stor directly det
ermin
e
s maxi
mum output p
o
we
r of the propo
sed
PA. The tra
n
s
isto
r
can
wi
thstand
a m
a
ximum volta
ge of
bre
a
kd
own
voltage
(
V
max
), while
its
minimum voltage is limited
by the knee
voltage (
V
knee
).
V
knee
defined as a value
of
V
ds
when the
drain
cu
rrent
of the tran
sist
or rea
c
h to 9
5
% of its maximum current.
And
V
knee
divides wo
rk sta
t
e
of the tran
sistor into the li
near
regi
on a
nd the
satura
tion regi
on. Und
e
r n
o
rm
a
l
circum
stan
ces,
V
knee
compa
r
ed to
V
max
is a very
sm
al
l value. It ca
n be
ign
o
re
d
in the
de
sig
n
, i.e. ca
n b
e
c
o
ns
ide
r
ed
V
knee
โ
0. Ho
wever, this de
sign
is wo
rke
d
un
der 1V
supply voltage
and
the p
o
wer
transi
s
to
r ne
ed to wo
rk i
n
saturation re
gion,
V
knee
must therefore
be co
nsi
dered. Thro
ugh
DC
sweep curve,
V
knee
โ
0.5V is estim
a
ted. The output p
o
we
r of the PA can be exp
r
esse
d as:
CC
k
n
e
e
CC
ou
t
2
(V
-
V
)
I
P=
(1)
Whe
r
e
V
cc
is powe
r
suppl
y voltage an
d
I
cc
is drain
current of th
e power tran
sisto
r
. 5dBm
(
โ
3.16m
W) ma
ximum output
powe
r
is ne
e
ded, so:
๏ด
๏ฝ๏ฝ
๏ฝ
๏ญ๏ญ
ou
t
CC
DD
k
n
e
e
2
23
.
1
6
12.6
4
m
A
10
.
5
P
I
VV
(2)
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๏ฎ
e-ISSN: 2
087-278X
TELKOM
NIKA
Vol. 11, No
. 8, August 2013: 4470 โ
4476
4472
A
cco
rdi
ng t
o
I
cc
and a
bove
re
quirement,
width
to le
ng
th ratio
an
d b
i
as volta
ge
of po
wer
transi
s
to
r ca
n
be prob
ably
sele
cted. Co
nsid
erin
g th
e
existence of various
n
on-ideality factors,
the actual out
put powe
r
wil
l
certainly be
less t
han the expecte
d value, and there
f
ore the si
ze
of
the tran
sisto
r
and the bia
s
voltage must
leave som
e
margi
n
.
2.2. Radio Fr
equen
c
y
Ch
oke Induc
tor
TSMC 0.18
ฮผ
m RF CM
OS pro
c
e
ss p
r
ovi
des a vari
ety of on-chip spi
r
al indu
cto
r
s.
The on-
chip
ind
u
cto
r
is not
a
sim
p
le in
du
ctor,
but cont
ain
s
compl
e
x p
a
rasitic pa
ram
e
ters of a
circuit.
Nine
-pa
r
am
eter eq
uivalent
circuit of the
i
ndu
ctor i
s
sh
own in Fi
gu
re
3. Whe
r
e R
su
b1
and R
sub2
are
sub
s
trate p
a
rasitic resi
stan
ce, and C
sub1
and C
sub2
are
sub
s
trate pa
rasiti
c ca
pa
citance, and C
ox1
and C
ox
2
are t
he p
a
ra
sitic capa
citan
c
e b
e
twee
n the i
n
ducto
r a
nd th
e sub
s
trate
surface, an
d
C
s
is
the
pa
ra
sitic cap
a
cita
nce betwe
en
th
e main co
il
of
the ind
u
cta
n
c
e
and
the l
ead lin
e. Th
ese
para
s
itic
pa
ra
meters ma
ke
the poo
r pe
rf
orma
nce of
the on
-chip
sp
iral ind
u
cto
r
s. The Q val
u
e
is
low, gen
erall
y
less than
10. Usually the high
er
th
e freque
ncy,
the Q value is lowe
r, mainly
becau
se the t
op-level m
e
ta
l line of the in
ducto
r ex
ist
s
ski
n effect. T
he high
er the
freque
ncy, the
greate
r
the p
a
ra
sitic resi
st
ance, and thu
s
the Q value
is lowe
r.
Figure 3. Nin
e
-pa
r
am
eter
Equivalent Ci
rcuit of the In
ducto
r
Q value,
the
maximum
allowe
d
cu
rre
nt, accu
ra
cy of
the m
odel,
o
u
tput mat
c
hin
g
, loss,
and
many
oth
e
r fa
ctors are
nee
ded
to
be
take
n i
n
to a
c
cou
n
t, wh
en
cho
o
si
ng th
e
cho
k
e
ind
u
ct
or.
The
i
ndu
ctor must have a large
r
Q
val
u
e
ne
ar
2.
44
G
H
z.
Wid
e
r m
e
tal wi
dth
of the in
du
ctor can
increa
se Q v
a
lue an
d the maximum all
o
we
d cu
rrent
. Since the d
r
ain ind
u
cta
n
c
e is p
a
rt of the
output mat
c
hi
ng ci
rcuit, this ind
u
cto
r
sh
ould b
e
sele
cted to sim
p
lify matchin
g
n
e
twork. Ado
p
t
ing
the indu
ctor
with accu
ra
cy model will ca
use the
simul
a
tion re
sults
more reliabl
e.
2.3. Outpu
t
Po
w
e
r Co
ntr
o
l
Wirel
e
ss
sen
s
or
network node
s pla
c
ed ra
ndom
n
e
ss (often
sprea
d
ing th
rough the
aircraft), which re
sulted in
wirel
e
ss co
mmuni
cation
distan
ce i
s
n
o
t fixed. In o
r
de
r to the save
power
con
s
u
m
ption an
d e
x
tend battery
life, PA needs
to be adj
ust
ed the st
reng
th of the outp
u
t
power a
c
cord
ing to the len
g
th of the
distance of the wirele
ss
comm
unication.
In this desig
n
,
power tra
n
si
stor is divid
e
d
into three p
a
rts an
d co
ntrolled by Sig
nal Ctr
1
,
Ctr
2
a
nd
Ctr
3
, whi
c
h i
s
sh
o
w
n i
n
Fig
u
re
2. Wh
en th
e
sign
al is in
hi
gh level, it
ca
n en
able
one
part
of the transi
s
t
o
r. And wh
en
the signal i
s
in low le
vel, it can di
sa
ble o
ne part of the
transi
s
tor. Th
e
three
bits
con
t
rol si
gnal
ca
n ena
ble 7 l
e
vels (001
-11
1
)
of outp
u
t po
wer of the PA
, and shut do
wn
the PA when
it is 000 [7].
2.4. Diffe
ren
t
ial Cascod
e
Structure
D
i
ffe
r
e
n
t
ia
l s
t
r
u
c
t
ur
e h
a
s
ma
n
y
a
d
v
an
ta
g
e
s
fo
r th
e
PA. It c
a
n
s
u
p
p
r
ess
c
o
mmo
n
mode
noise; in
cre
a
s
e
output vol
t
age
swi
ng
o
f
the PA. It
can
offset
th
e pa
ra
sitic in
ducta
nce of t
h
e
power
tran
si
stor so
urce at
encap
sula
tion. And it
also
ca
n su
ppre
s
s
se
co
nd ha
rmo
n
ic and
improve the li
nearity.
ย
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
e-ISSN:
2087
-278X
๏ฎ
0.18
ฮผ
m
CMOS Low Voltag
e Powe
r Am
plifier
for WS
N Application
(Wu Chenji
an)
4473
In casco
de
structu
r
e of thi
s
de
sign [8], the
co
mmon
-
s
our
ce t
r
a
n
si
st
or (p
ow
er t
r
a
n
si
st
or
)
use
s
the thin gate tran
sisto
r
, which ca
n provi
de hi
ghe
r gain. The
co
mmon-gate transi
s
tor
(swit
c
h
transi
s
tor) uses the thick gate transistor, whic
h ensures its breakdown
voltage affordability.
2.5. Stabilit
y
Control
Stability must be con
s
ide
r
ed when d
e
si
gn a PA.
The
con
d
ition
s
of PA stability is K>1.
Whe
r
e:
๏ซ๏
๏ฝ
22
2
11
2
2
12
2
1
1-
-
2
SS
K
SS
(3)
๏๏ฝ
๏ญ
11
22
12
2
1
SS
S
S
(4)
Serie
s
conn
e
c
ting a
re
si
stor
with the i
n
put term
in
al o
r
pa
rallel
con
nectin
g
a
re
si
stor
with
the output te
rminal of the
PA can m
a
ke
the PA unco
nditionally
sta
b
le work [9]. In this d
e
si
gn,
a
low re
si
stan
ce resi
sto
r
is selecte
d
to series conn
ect with the input termin
al.
2.6. Load Pull
One of the
power am
plifier de
sig
n
target
s i
s
to o
b
tain the ma
x output po
wer
and
efficien
cy. In the desi
gn p
r
oce
s
s, load
pull [
10] sim
u
lation is
ad
opted to dete
r
mine the
out
put
matchin
g
net
work. Assumi
ng that outp
u
t load of th
e PA is a va
riable,
cha
ngi
ng this va
ria
b
le
once and
ga
ining an
out
put power
e
v
ery time, and a
s
mu
ch
as po
ssible
the value o
f
this
variable
is m
appe
d to
enti
r
e Smith
Cha
r
t, a
se
rie
s
e
qual
po
wer
ci
rcle
a
nd
equ
a
l
efficien
cy
circle
can
be obtai
ned. In the
cente
r
of the
s
e
circ
le
s, the maximum
output po
we
r point and t
he
maximum efficien
cy point
can be d
e
termi
ned.
Co
mpro
mising
betwe
en these two
points, the b
e
s
t
output load i
s
sele
ct. Figure 4 sho
w
s on
e
of the simul
a
tion re
sults
of load pull.
Figure 4. Simulation Result of Load Pull
2.7. Bias Cir
c
uit
The bia
s
circuit use
d
to generate the voltage V
bias
, which is shown in Figure 2.
Simulation fo
und that, und
er conditio
n
s of differ
ent pro
c
e
ss co
rn
ers have
a di
fferent
thre
sh
old
value voltage
V
th
of the po
wer tran
si
stor. V
th
was
sma
ll in the FF
proce
s
s, whil
e
V
th
w
a
s
la
r
ge in
the SS proce
ss. If a
con
s
tant voltage
o
f
V
bias
is
mai
n
tained, pro
c
ess corne
r
di
fference will be
more o
b
viou
s. The bias ci
rcuit is de
sign
ed to redu
ce t
he differen
c
e
s
in different
pro
c
e
ss
co
rn
ers.
It outputs a
varying volta
g
e
of V
bias
. In FF process
corne
r
, it outp
u
ts a l
o
wer v
o
ltage of V
bia
s
to
adapt V
th
red
u
ction. And In SS proce
s
s co
rn
e
r
, it output a highe
r voltage of V
bias
to adapt V
th
increa
se. Th
e sim
u
lation
results
of voltages
m
entio
ned a
bove i
n
different
co
rner
pro
c
e
s
s
are
sho
w
n in Ta
b
l
e 1.
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๏ฎ
e-ISSN: 2
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NIKA
Vol. 11, No
. 8, August 2013: 4470 โ
4476
4474
Table 1. Simulation Results of Voltages
in PA
Process corner
Vth(V)
Vg
s/ Vbias (
V
)
Vgs-
Vth(
mV)
TT
0.516
0.55
34
FF
0.463
0.498
35
SS 0.564
0.598
34
3. Experimental Re
sults
Figure 5 sh
ows the microph
otog
rap
h
of
the proposed PA. The PA die area is
1070
ร6
10
ฮผ
m
2
including b
ondin
g
pad
s. The radio f
r
equ
en
cy ch
oke ind
u
cto
r
s and the p
ads
determi
ne th
e area of th
e
PA. The two
indu
ctors
o
c
cupy m
o
st
of the a
r
ea
an
d set
on th
e
two
side
s of the layout. And the other pa
rts of t
he propo
sed PA use a comp
act a
r
ea to set in the
cente
r
of the die.
Figure 5. Microphoto
g
ra
ph
of the Propo
sed PA
Fi
gure 6. Photograp
h of the Printed Ci
rcuit
Board
Bonding te
st
wa
s ad
opted
to measure the pr
opo
se
d
PA. The phot
ogra
ph of the
printed
circuit boa
rd i
s
sh
own in Figure 6. Th
e part of
input and outp
u
t matchin
g
network i
s
co
mpo
s
e
d
by patch ind
u
c
tors and
cap
a
citors, whi
c
h
can be
see
n
on the printe
d
circuit boa
rd.
Figure 7 sho
w
s the S-p
a
rameter me
asured
re
sults
of the PA. The tested co
ndition
s
were set a
s
follows: input
power was
-3
0dBm,
input frequ
en
cy wa
s 2.44G
Hz, and po
wer
con
t
rol
cod
e
was
11
1. Then th
e control
cod
e
was
cha
nge
d g
r
adu
ally, and
measured the
S-pa
ramete
r
at
every step. And all the S-p
a
ram
e
ter me
as
u
r
ed
re
sult
s are
sum
m
arized in Ta
ble
2.
Figure 7. S-p
a
ram
e
ter Me
asu
r
ed
Re
sul
t
s
ย
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TELKOM
NIKA
e-ISSN:
2087
-278X
๏ฎ
0.18
ฮผ
m
CMOS Low Voltag
e Powe
r Am
plifier
for WS
N Application
(Wu Chenji
an)
4475
Table 2. S-pa
ramete
r Sum
m
ary at 2.44
GHz
Control
code
S11(dB)
S21(dB)
S12(dB)
S22(dB)
111
-11.16
13.57
-25.16
-5.16
110
-11.13
12.44
-25.64
-5.03
101
-11.23
10.91
-26.71
-4.99
100 -10.87
9.12
-26.44
-4.74
011 -10.96
6.59
-25.92
-4.68
010 -10.02
3.22
-26.18
-4.28
001
-9.94
-2.95
-26.67
-4.09
The output p
o
we
r, power
gain and
work cu
rre
nt
mea
s
ured re
sult
s are sho
w
n in Table 3.
The tested
condition
s we
re set as follo
ws: inp
u
t frequen
cy wa
s 2.44G
Hz, an
d powe
r
cont
rol
cod
e
wa
s 1
1
1
, and
chan
g
e
inp
u
t po
we
r fro
m
-
30dB
m to -8dBm.
From
Tabl
e
3, the m
e
a
s
u
r
ed
power
gain
o
f
the PA de
creases from
1
6
.88dB to
15.
87dB, when
i
nput p
o
wer i
n
crea
se
s fro
m
-
30dBm to
-9.63dBm. So
the in
put 1
d
B
refe
rred
co
m
p
re
ssi
on
poin
t
of the PA
is -9.6
3dBm, a
n
d
the PAโs po
wer gai
n is
15.
87dB, wh
en it
con
s
um
es
1
5
.3mA cu
rren
t. The 1dB co
mpre
ssion
po
in
t
is
s
h
own in Figure 7. So the PAE of the
1dB c
o
mpress
ion point is
:
๏ญ
๏ญ
๏ฝ๏ป
๏ป
ou
t
i
n
dc
4.
2
m
W
0
.
1
1
m
W
26
.
73%
15.
3
m
W
PP
PAE
P
(5)
Table 3. Outp
ut Power, Po
wer
Gain
an
d
Work Curren
t Measu
r
ed
Result
s
Input po
w
e
r (dB
m
)
Output p
o
w
er
(d
Bm)
Power gain(
dB)
Work current (
m
A)
-30
-13.12
16.88
6.9
-20
-3.33
16.67
7.4
-15
1.29
16.29
8.3
-13
3.04
16.04
10.4
-11
4.99
15.99
14.4
-9.63
6.24
15.87
15.3
-8
6.35
14.35
16.9
Figure 7. 1dB Comp
re
ssi
o
n
Point of the PA
The me
asure
d
re
sults
of p
r
opo
se
d PA and thei
r
co
mpari
s
o
n
to that of other
Cla
ss A/B
PAs are
sum
m
ari
z
ed in the Table
4. From Tabl
e 4, this
work has
higher PAE than others PA,
and it con
s
u
m
es le
ss p
o
wer.
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๏ฎ
e-ISSN: 2
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Vol. 11, No
. 8, August 2013: 4470 โ
4476
4476
Table 4. Pefo
rman
ce
Com
pari
s
on of Cl
ass A/B
Parameter
This
w
o
rk
[11]
[12]
[13]
Work frequenc
y (
G
Hz)
2.4-2.483
5
2.4-2.483
5
2.4-2.480
1.92
Suppl
y
voltage (
V
)
1
1.2
1.8
1.2
Power consumpti
on (mW)
15.3
22
24.25
NA
Output p
o
w
er
(d
Bm)
6.24
7.92
6.4
4
PAE (%)
26.73
25.34
18
26
4. Conclusio
n
A low voltage
of 1V class A
/
B power
am
plifie
r for
WS
N appli
c
atio
n
wa
s presente
d
in this
paper. After the measurement, it achieves 26.
73%
PAE at 6.24dBm output
power. And it only
con
s
um
es 1
5
.
3mW. T
h
is
work can
be
applie
d in
the transc
eiver for
WS
N
s
y
s
t
em. And it
als
o
can b
e
the ref
e
ren
c
e of the
further
re
sea
r
ch on
lo
w voltage an
d low
power for
WS
N tran
sceiver.
Ackn
o
w
l
e
dg
ments
The auth
o
rs
woul
d like to
ackno
w
le
dge
Instit
ute of RF- & OE-ICs,
Southea
st Un
iversity,
for the
re
se
arch e
n
viron
m
ent supp
orted and t
h
a
n
k fo
r the
suppo
rt by th
e Natio
nal
High
Tech
nolo
g
y Re
sea
r
ch an
d Devel
opme
n
t Program (No. 20
07AA0
1Z2A7)
and t
he Spe
c
ial F
u
n
d
of Jian
gsu Province fo
r th
e Tra
n
sfo
r
ma
tion of
Scient
ific and T
e
ch
nologi
cal A
c
h
i
evements
(No
.
BA20100
73).
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e
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n
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