TELKOM
NIKA Indonesia
n
Journal of
Electrical En
gineering
Vol. 14, No. 2, May 2015, pp. 270 ~ 27
9
DOI: 10.115
9
1
/telkomni
ka.
v
14i2.748
5
270
Re
cei
v
ed Fe
brua
ry 9, 201
5; Revi
se
d April 20, 201
5; Acce
pted Ma
y 1, 2015
QCA and CMOS Nanotechnology Based Design and
Development of Nanoelectronic Security Devices with
Encryption Schemes
S. Dev
e
ndra K. Verm
a*
1
, P. K. Barhai
2
, V. Nath
3
Birla Institute o
f
T
e
chnolo
g
y
(
A
Deeme
d
Uni
v
ersi
t
y
), Mesra
–
835 2
15, Ra
nchi, Jhark
h
a
n
d
, India
*Corres
p
o
ndi
n
g
author, e-ma
i
l
: SDKV@hotm
a
il.com,
pkb
a
rh
ai@b
itmesra.a
c
.in, vnath@b
i
tmesra.ac.in
A
b
st
r
a
ct
In
WiMAX/WiF
i
Wire
le
ss En
viro
nm
ent the Tr
ansfer of Data/Informati
on is
vuln
erab
le to e
x
terna
l
attacks as it takes place thr
ough
an open-
air medium
. The Data/Infor
m
at
ion is vulner
able to Jamm
ing,
Detectio
n, Interceptio
n, Ne
tw
ork Injecti
on,
Interruptio
n, Modific
a
tion, Pa
cket Scrambli
ng, F
abric
atio
n
,
Una
u
thoris
ed f
o
rw
ardin
g
an
d
Deni
al-of-S
e
r
v
ice (DoS
). O
u
r Research
Work focuses
on
‘
Q
CA & CMOS
Nan
o
tech
nol
og
y based D
e
si
gn & Dev
e
lo
p
m
e
n
t of Nan
o
e
lectronic Sec
u
rity De
vic
e
s with Encryption
Sche
mes to p
r
ovid
e/enh
anc
e Security an
d Privacy
for WiMAX/WiFi/Satellit
e
Wireles
s
Communic
a
t
i
o
n
Systems. T
h
e
Sche
mes
ar
e bas
ed
on
Dyna
mic
C
h
a
nne
l H
opp
in
g, Ran
d
o
m
Ch
ann
el S
e
lecti
o
n,
Cryptogr
aphy
and Encry
p
tio
n
of Informatio
n/Data/Co
n
trol C
odes.
Ke
y
w
ords
:
na
notech
n
o
l
ogy, CMOS,
QCA,
W
i
MAX,
W
i
F
i
,
cryptogra
phy, encrypti
on co
d
e
Copy
right
©
2015 In
stitu
t
e o
f
Ad
van
ced
En
g
i
n
eerin
g and
Scien
ce. All
rig
h
t
s reser
ve
d
.
1. Introduc
tion
WiMAX (Wo
r
ldwi
de Inte
roperability fo
r Mi
cr
o
w
ave
Access) su
pport
s
a
variety of
Wirel
e
ss Bro
adba
nd
Co
nn
ection
s,
su
ch
as Wi
rel
e
ssMAN, Wi
rel
e
ssWA
N,
Cellul
a
r Ba
se
Stations
& WiFi Internet, IPTV o
v
er WiMAX, etc
.
It pr
ovides high-data
-rat
e
comm
uni
ca
tions for Fixe
d-
Station (FS)
Subscri
bers t
o
a
dista
n
ce
of 30 mile
s from a Ba
se
-Station (BS)
and for M
obil
e
-
Station (MS)
Subscri
bers to 10 miles fro
m
a BS.
In our Research
Work, the
Security Prin
ciples used i
n
WiMAX (IEEE 802.16e) and WiFi
(IEEE 802.11i) are analyzed and it
is found that many sophi
sticat
ed Techniques
are embedded
into Wi
MAX
and
WiFi
for
Authenticatio
n an
d En
cryp
tion, but it
still expo
se
s to
variou
s Se
cu
rity
Attacks. There are Security Vu
lnerabilities i
n
both P
H
Y and MA
C Layers
of
Wi
MAX. It exposes
t
o
v
a
rious
cla
s
s
e
s of
Wi
rel
e
s
s
A
t
t
a
ck
s,
su
ch a
s
Jam
m
ing, Interce
p
tion, Modification, Fabri
c
a
t
ion,
Repl
ay, etc. Similarly WiFi
is also
exposed to s
u
c
h
Wireles
s
Attacks
.
WiMAX Pro
g
r
amma
ble T
r
ansceive
r
i
s
a Devi
ce,
which t
r
an
smit
s an
d receives
radi
o
sign
als si
mul
t
aneou
sly. It incre
a
ses it
s ca
pa
city and usability in real-tim
e applying F
D
D
(Freque
ncy
Division Du
ple
x
ing), whi
c
h provide
s
sim
u
ltaneo
us Ra
dio T
r
an
smi
s
sion
Chan
nel
s fo
r
the Subscribe
r
and th
e BS. In Cha
nnel/F
reque
ncy
Hop
p
ing a
numb
e
r
of Ch
ann
els are all
o
cated
.
At the XMTR-End, for a fixed interval th
e Tran
sm
itter transmit
s
in
one chan
nel
at a time and
the
RCV
R-En
d, the Receiver
synchro
n
izes with t
he T
r
a
n
smitter
by h
oppin
g
bet
we
en the
Cha
n
nels
and the Me
ssage is reconfi
gure
d
acco
rdi
ngly.
In our
Re
sea
r
ch
Wo
rk, a P
r
ogra
mmabl
e
Secu
rity Devi
ce
(PSD) i
s
d
e
sig
ned/ d
e
velope
d/
simulated for WiMAX/WiFi
/Satellite Wireless
Com
m
unication
Sy
stem
s.
The CMOS Model
is
develop
ed u
s
ing CA
DENCE Software
T
ool to the
scale of 45
nan
ometer &
1.0
v
, and the Q
C
A
Model u
s
ing
QCADesi
gne
r Tool with
Cell size <2
0 nanom
eter &
powe
r
ed
wit
h
Clo
ck Sig
n
als
only. The Mo
del is sim
u
lat
ed with four
Buse
s/
Ca
rri
ers/Ch
ann
els, tran
smitting
Messag
es from
four Sou
r
ces/Use
r
s to fo
ur Destin
ations
ho
ppin
g
among fo
ur
Cha
nnel
s an
d the Re
cei
v
er
synchro
n
izes with the Transmitte
r an
d the Mess
a
ges a
r
e reco
nfigure
d
accordin
gly for four
De
stination
s
. The PSD System is base
d
on Netw
ork, inco
rpo
r
atin
g Dynami
c
Ch
a
nnel Ho
ppin
g
,
Ran
dom
Cha
nnel Sele
ctio
n and En
cryp
tion of Messa
ges a
nd
Cont
rol Code
s to
provide Se
cu
rity
& Privacy in WiMAX/WiFi
Wirel
e
ss Co
mmuni
cation
Networks.
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
2302-4
046
QCA and
CM
OS Nanote
c
h
nolog
y Based
Desi
gn an
d De
velo
pm
ent… (S. Deven
d
ra K. Verm
a)
271
2.
Securit
y
Threats in WiM
A
X & WiFi
The
WiMAX
and
Wi
Fi P
r
otocols a
r
e
exami
ned
to
evaluate
th
e Se
curity M
easure
s
provide
d
. Th
e Secu
rity Archite
c
ture fo
r WiMAX
is ba
sed o
n
two m
a
jor con
c
ept
s: Requireme
n
t
s
,
appli
c
able to
the Netwo
r
k Elements a
nd Systems,
con
s
tituting the end to-e
nd network, are
addresse
d b
y
the Security Layer
s. Fo
r Data Encry
p
tion, there
are two Sch
e
mes – a
)
AES
(Advan
ced E
n
cryptio
n
Standard and b
)
3DES (Tripl
e Data Encry
p
tion Standa
rd). For the
WiFi
Protocol, the WEP (Wired
Equivalency
Privacy)
En
cryption S
c
h
e
me wa
s first introduced
and
later it was
modified and the WPA (WiFi Prot
ec
ted Acc
e
s
s
) Sc
heme was
adopted. A PSK (Pre-
Share
d
Key)
is create
d
to authori
z
e
con
t
act.
WPA is
further e
nha
n
c
ed a
nd
WPA2 Schem
e is
introduc
e
d [1-3].
The Security
Archite
c
ture
and Prin
cipl
es u
s
ed in t
he WiMAX (802.16
e Prot
ocol
) an
d
WiFi (8
02.11i
) are a
nalyse
d and foun
d that it is
not sufficient to prevent/prote
ct from Ja
mmin
g
,
Interce
p
tion
and
Data
T
r
affic M
odifi
cation. Ap
pli
c
ation
of Chann
el/Fre
qu
ency
Hop
p
i
n
g
Tech
niqu
e
wi
th Encryption
Key an
d
Co
ntrol
Co
des i
s
m
o
re
suita
b
le to
deal
wi
th Ja
mming
and
Interce
p
tion
and p
r
ovide
the re
quire
d preve
n
tion
and p
r
ote
c
tion. This
ki
nd of Se
curity
Manag
eme
n
t
is a Netwo
r
k-b
a
sed Def
ence
(NB
D
) Schem
e.
Its cap
ability
is enha
nced wi
th
appli
c
ation of
Control
Cod
e
and Key Co
de [4-7].
In WiMAX/Wi
Fi Wi
rele
ss/Mobile
Co
m
m
unication, t
here
a
r
e
different
types o
f
Secu
rity
Thre
ats, su
ch
as: Jammin
g
/
Interception
of the
Communication Li
nk, Intercepti
on/ Modificati
on/
Fabri
c
atio
n/ Forwarding
o
f
the Messa
g
e
, Cloni
ng/
S
e
cu
rity Co
de
Violation, et
c. The
Security
Services are
classified as:
Confid
entiality, Nonrepudi
ation,
Authentication, Integrity, Availability,
Prevention
of Secu
rity Violation, Securit
y
Dete
ct
io
n,
Re
cov
e
ry
,
et
c.
The
Te
chn
i
que
s (S
che
m
es
)
use
d
to p
r
ote
c
t Security a
nd Priva
c
y are: Ch
a
nnel/F
reque
ncy
Hop
p
ing, En
crypti
on of Me
ssag
e,
Source/Desti
nation Code
s, Au
thentication, etc [8-1
1].
The Secu
rity Device
s & Scheme
s
a
r
e ba
sed on
Chann
el/Freque
ncy Ho
pping, a
Tech
niqu
e in
whi
c
h a
nu
mber
of Cha
nnel
s a
r
e all
o
cate
d an
d t
he Tran
smitter tra
n
smits i
n
one
cha
nnel
at a
time for a
fixed interval
. Duri
ng t
hat
interval
so
me num
be
r
of bits
(data
)
is
transmitted u
s
ing
some e
n
c
odi
ng sche
me. A Receiv
er, hoppi
ng b
e
twee
n Cha
n
nels/F
r
eq
uen
cie
s
synchro
n
izes with the Tra
n
smitter a
nd
the messa
ge
is re
co
nfigure
d
acco
rdin
gly. There a
r
e t
w
o
basi
c
type
s
of Fre
que
ncy
Ho
pping, i
d
entified a
s
: a
)
S-F
H
(Slo
w-Freque
ncy
Hop
p
ing
)
, wh
ere
several Symbols/Multipl
e
Bits are tran
smitt
ed on
e
a
ch F
r
e
que
n
c
y Ho
p, and
b) F-FH
(F
ast-
Freq
uen
cy Hoppin
g
). It enable
s
the Carrie
r Fre
q
uen
cy durin
g
the Transmissi
on of one
Symbol/Bit to
chan
ge/ho
p several times.
In this
Re
sea
r
ch
Work a
PSD (P
rog
r
am
mable Se
cu
ri
ty Device
) i
s
desi
gne
d, ba
sed
on
Cha
nnel/F
req
uen
cy Hoppi
ng Te
ch
niqu
e
alon
g
with
E
n
cryptio
n
of
Messag
es an
d Control
Co
des
for providi
ng
Secu
rity and Privacy in Wi
MAX/WiFi Wi
rele
ss
Comm
unication.
3.
CMOS & Q
C
A Tech
nolog
y
CMOS (Com
plementa
r
y Metal-oxid
e Semico
ndu
ct
or) L
ogi
c is a
combi
nation
of PMOS
and NM
OS Logic. The
CMOS Logi
c Functio
n
s a
r
e desig
ned u
s
ing both P-Type and N-Type
Tran
si
stors.
The Po
we
r
Dissip
ation i
n
CM
OS
takes pl
ace onl
y when
Ci
rcuit swit
che
s
and it
con
s
um
es ve
ry little po
we
r. It sup
port
s
fabri
c
at
ion
of VLSI Circuits
with ma
ny more CM
O
S
Gates o
n
an IC having mu
ch better pe
rfo
r
man
c
e.
QCA rep
r
e
s
e
n
ts an
eme
r
g
i
ng Te
ch
nolo
g
y, which wa
s first intro
d
u
c
ed
by Lent
et al in
1993.
QCA
L
ogic States
a
r
e
rep
r
e
s
ente
d
with
Qua
n
t
u
m Wells ha
ving 4
Quant
um-Dots an
d
2
mobile Ele
c
trons. In th
e
QCA
Cell, th
e Electr
on T
unnellin
g fa
ci
litates the m
o
vement of t
he
Electro
n
s
to different Qua
n
tum-Dots
p
o
sitioni
ng
dia
gonally, b
a
sed o
n
the
Columbi
c
F
o
rce.
There are t
w
o p
o
ssibl
e
Polari
zation
s:
+1
(Bina
r
y 1) an
d -1 (Binary 0),
d
epen
ding
on
th
e
Electro
n
s’
po
sition
s. In QCA a Logi
c Sig
nal Tr
an
smission Cha
nnel is
kno
w
n
a
s
Binary
Wi
re. The
Cell
s tran
smi
t
information
in Co
ded fo
rm (0 o
r
1
)
from one
Cell
to anothe
r in
the Binary
Wire
without any
current flow. E
a
ch
Cell’
s Po
lariza
tion d
e
p
end
s upo
n its previou
s
nei
ghbo
ring
Cell
’s
Polari
zation. I
n
the case of
Inverter
Chai
n, t
he tran
sm
issi
on of
Cod
e
take
s pl
ace
with inve
rsio
n
of the Code o
f
the previous neighb
orin
g Cell.
Majority G
a
te
is u
s
e
d
to im
plement
QCA
.
It con
s
ist
s
of one
Ce
nter
(Device
)
, three Input
and one O
u
tput Cells. If A, B, C are Inputs then O
u
t
put (the ma
jority of A,B,C) = M(A,B,C) =
AB+BC+CA. The
A
N
D
logi
cal ope
ration
is
p
e
rfo
r
med
if the inp
u
t p
o
lari
zation
of
Control Inp
u
t
is
fixed to -1
(lo
g
ic 0
)
a
nd th
e OR logi
cal
operation
i
s
p
e
rform
ed i
n
the case of
+1 (lo
g
ic
1).
When
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 23
02-4
046
TELKOM
NI
KA
Vol. 14, No. 2, May 2015 : 270 – 279
272
the Cell
s are
placed diag
o
nally, the NO
T logical o
p
e
r
ation is pe
rfo
r
med. The M
a
jority AND,
OR
and NOT Gat
e
s are sh
own
in Figure 1.
Figure 1. Majority Gates
A Multizon
e
Clo
ck
Mecha
n
ism i
s
requi
red fo
r Data
Propa
gation i
n
the Q
C
A Circuit. It
has fou
r
Clo
c
k Signal
s wit
h
90 deg
ree
relative pha
se differen
c
e
with each oth
e
r. Zone 0, Z
o
n
e
1, Zone 2 an
d Zone 3 are
identified as four Cl
o
ckin
g
Zone
s, and
Switch, Hold
, Release an
d
Relax States are ide
n
tified as fou
r
Clo
ck Ph
ase/
States. Each
Ce
ll is con
n
e
c
te
d to one of four
Phase
s
of the QCA
Clo
ck in a
Clo
cki
ng
Zone.
De
p
e
n
d
ing
o
n
the p
o
lari
zation of the
neig
hbo
ri
ng
Cell, the S
w
itch and
Hold
Stat
es determine the
QCA Cell’s Polari
zation while the Rel
e
ase
and
Relax States are un
pola
r
i
z
ed. With th
e
chan
ging of
the Clo
ck Sig
nal ea
ch Cell
is latche
d a
n
d
unlatched. Th
e QCA Clo
c
k
and Q
C
A Clo
ck Z
one
s are sho
w
n in Fig
u
re 2 [12
-
17].
Figure 2. QCA Clock Sign
al
4. Metho
dolog
y
Our
app
roa
c
h will b
e
to d
e
sig
n
, develo
p
, qualify and
optimize
PSD-CMOS M
o
del to the
Scale
of
4
5
nanom
eters and Voltage
= 1.0V, usin
g CADENCE
Software To
ol. Also simu
late,
layout and verify PSD-Q
CA Model
with QCA-
Cell
size < 20 na
nomete
r
, usi
ng QCA
D
e
s
i
gner
Tool. Th
e ‘
M
olecula
r
Nanoel
ectroni
cs’ T
e
ch
nolo
g
y
and th
e ‘
T
op-do
wn’
a
ppro
a
ch i
s
more
suitabl
e for o
b
taining
Nan
o
stru
ctu
r
e wit
h
in the si
ze o
f
< 50 nm scale and
Cell size < 2
0nm. PSD
will be a new
Device to pro
v
ide/enha
nce
Security
and
Privacy for WiMAX/WiFi/Satellite Wirel
e
ss
Comm
uni
cati
on Systems. [18-2
0
].
5.
Simulation Tools & Setup
Two Sim
u
lat
i
on To
ols a
r
e u
s
e
d
to
de
sign, d
e
velop, mod
e
l
and
qualif
y PSDs
(Prog
r
am
mab
l
e Security Device
s). Ca
d
ence So
ftware Tool is use
d
to model PSD-CMOS a
n
d
QCADesi
gne
r Tool is u
s
e
d
to model PSD-QCA Devices.
5.1. CADENCE Soft
w
a
re
Tool
The Cade
nce Software T
ool is a
n
Ele
c
troni
c
De
sig
n
Automation
Software, u
s
ed fo
r
CMOS Ci
rcui
ts Simulation
. It is kno
w
n
as
Ca
den
ce
Analog and
Digital Syste
m
Desi
gn To
ols
(GPDK
46nm
). The Pro
c
e
s
s Ge
ometri
e
s
in
clud
e th
e
length a
nd
width of a T
r
an
sisto
r
to t
h
e
scale
s
of 45n
m and 65n
m respe
c
tively.
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
2302-4
046
QCA and
CM
OS Nanote
c
h
nolog
y Based
Desi
gn an
d De
velo
pm
ent… (S. Deven
d
ra K. Verm
a)
273
5.2. QCADe
s
i
gner
The Q
C
ADe
s
ign
e
r T
ool i
s
u
s
ed
for
Q
C
A Ci
rcuits
Simulation, constructe
d
wi
th QCA
Cell
s (e
ach cell size =
20
nm). The T
o
ol having
CAD capabilitie
s, helps to lay
out and
simul
a
te
QCA
Circuits. To facilitate rapi
d and accurate sim
u
l
a
tion, QC
A
D
esigner has t
h
ree Simulati
on
Engine
s: a)
DLSE (Digital
Logi
c Simula
tion Engine
),
whi
c
h d
e
term
ines
Cell
s to
be eithe
r
null
or
fully polariz
ed; b) NASE (Nonli
near Approximation Simulation E
ngine), whic
h determines
t
he
stable
state
o
f
the Cells,
d
epen
ding
on
the n
onlin
ear cell-to
-cell re
spo
n
se
fun
c
ti
on;
an
d c)
TS
SE
(Two-State S
i
mulation Engine),
whic
h forms
an
ap
proximation of
the full qu
ant
um me
ch
anical
model. In Q
C
A Ci
rcuits,
the co
ntrol of
the flow
of i
n
formatio
n is perfo
rmed
u
s
ing fo
ur
Clo
ck
Signals: Cl
ock Zone
0, Clo
ck Z
one 1,
Cl
ock Zone 2 a
nd Clo
c
k Zon
e
3.
6. Simulation
Model
A PSD (Programmabl
e Se
curity
Device) is de
sig
ned
with Swit
che
s
/Tran
s
mi
ssio
n
Gate
s
(TG
)
for XM
TR-En
d
a
n
d
RCV
R-E
nd.
The Simul
a
tion Mod
e
l (defined fo
r
comm
uni
cati
on),
comp
ri
se
s of
four Bu
s Carriers/
Cha
nnel
s (as B
0
, B1, B2, B3), four
Source/Use
r
Comm
uni
cati
o
n
Links (a
s S0, S1, S2, S3), four Destin
ation Links
(as
D0, D1, D2,
D3), an
d four
Control Lin
ks
(as
C0, C1,
C2
, C3). The
r
e are fou
r
Freq
uen
ci
es as
s
i
gned (as
f0, f1, f
2
, f3) for Bus
Carrie
rs/
C
ha
nnel
s
(a
s B0,
B1, B2, B3
).
The
Co
ntrol
L
i
nk i
s
used
to
sel
e
ct
a Bu
s
Carrie
r fo
r e
a
c
h
User/Sou
rce
Link i
n
thi
s
configuration f
o
r tr
an
smitting Me
ssage/
Data. Similarly
,
for re
ceivin
g
Data, the
Co
ntrol Lin
k
i
s
use
d
to syn
c
hroni
ze th
e transmitte
r an
d sel
e
ct Bu
s
Carrie
r for
e
a
ch
De
stination
L
i
nk. T
he PS
D (Programma
ble Se
cu
rity
D
e
vice) is show
n in Figure 3. The C
M
OS
Tran
smi
ssi
on
Gate
Circuit
and th
e T
r
an
smissio
n
G
a
te Ci
rcuit Anal
ysis
are
sho
w
n i
n
Fig
u
re
4 &
Figure 5.
Figure 3. Pro
g
ramm
able S
e
cu
rity Device
Figure 4. CM
OS Tran
smi
s
sion G
a
te Circuit
Fi
gure 5. CM
OS Tran
smi
s
sion G
a
te Analysis
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274
There are two Model
s: PSD-CMOS M
o
del an
d PSD-QCA Mo
del,
desi
gne
d, de
veloped,
simulate
d a
nd analysed
,
having a set of 4 Bus Carri
e
rs
(Ch
ann
e
l
s), Source/
U
ser
Comm
uni
cati
on Links an
d Control Links and it
can be expan
ded to a set
of 8, 12 or 16
Cha
nnel
s.
6.1. PSD-CMOS
Model
The PSD-CM
O
S Model
is
desi
gne
d an
d
develop
ed u
s
ing
CA
DENCE Softwa
r
e
Tool to
the scale of
45 nm an
d
1.0V. CMOS
Switche
s
/T
ransmi
ssion Gates (TG
)
Matrix
is
u
s
e
d
to
desi
gn PS
D for XM
TR-End a
nd
RCVR-End. T
he
PSD Swi
t
ch M
a
trix i
s
nee
ded
at
both
Tran
smitting
and
Receivin
g Ends fo
r co
nfigurin
g diffe
rent Pattern
s.
The same P
a
ttern is
used
b
y
both the XMTR and
RCV
R for tran
sm
itting and re
ceiving the
Data/Me
s
sag
e
. A set of four
Switche
s
/T
ra
nsmi
ssi
on G
a
tes a
r
e
con
necte
d to ea
ch
Contrl
Lin
k
. One
Co
ntrol Lin
k
is
sel
e
cted
at a time and each Switch
conne
cts o
n
e
Use
r
/Sou
rc
e Link to one
Bus Link at the Tran
smitti
ng
End and si
mil
a
rly one Desti
nation Lin
k
to
one Bus Lin
k
at the Receiv
ing End.
In this Mod
e
l, for four
Cont
rol Lin
k
s (a
s
C0, C1, C2,
C3), a
set of f
our
Cont
rol Code
s (a
s
CC1, CC2, CC3, CC4) a
r
e
defined hav
i
ng different value
s
as follo
ws:
CO
NTR
O
L LI
NK
CO
NTR
O
L
C
O
DE
C0
CC1 = 11
0
0000
1
C1
CC2 = 11
0
0001
0
C2
CC3 = 11
0
0001
1
C3
CC4 = 11
0
0010
0
For e
a
ch Ch
annel/F
req
u
e
n
cy Hoppi
ng,
the Co
ntrol
Cod
e
is
sel
e
cted ra
ndomly,
and the
asso
ciated
Control Li
nk i
s
activated a
c
cordingl
y for
allocating Bu
s Carriers (Chann
els) to the
User/Sou
rce Links at
the
T
r
an
smi
tting E
nd, an
d
simil
a
rly allo
catin
g
the B
u
s Ca
rrie
r
s (Ch
ann
els)
to the
De
stination
Lin
k
s at the
Re
ceiving
End. Duri
ng ea
ch
Ch
ann
el/Fre
quen
cy Hop
p
ing,
Messag
e/Dat
a
is tran
smit
ted from
the
User/S
o
u
rce
Lin
k
s to th
e corre
s
po
nd
ing
De
stination
Links. Again
for the next Chann
el/Freque
nc
y Ho
pping, a ne
w Co
ntrol Code is
sele
cted
rand
omly, the asso
ciated
Control Lin
k
is activa
ted,
Chan
nel
s are allocated a
nd tran
sa
ctio
n of
Messag
e/Dat
a
take
s pl
a
c
e a
s
m
enti
oned
above.
For
en
cryp
ting the Co
ntrol
Code
and
transmitting to the Re
ceivi
ng End, an Encryptio
n
Key is defined.
A set of
Transmi
ssion
Gates (T
G)
are
used fo
r Switch
Mat
r
ix. Usi
ng
CADENCE
Software To
o
l
, a PSD-CM
O
S Model is
simulate
d (for 1.0V and 45
nm scal
e
). T
he PSD-CM
O
S
Model an
d the PSD-CMO
S Model Anal
ysis are sh
own in Figure 6 & Figure 7 re
spe
c
tively.
Figure 6. PSD-CMOS Mo
del
Figure 7. PSD-CMOS Mo
del Analysi
s
6.1.1. Simula
tion Re
sults
& Analy
s
is
A PSD-Cha
nnel/Frequ
en
cy Hoppin
g
Pattern i
s
simul
a
ted
in which
for e
a
ch
Cha
nnel/F
req
uen
cy Ho
ppi
ng Time Slot
s (as t0, t1,
t2, t3), the Control Code
s a
r
e
sele
ct
ed
rand
omly in
the
seq
uen
ce
of CC2,
CC4,
CC1
and
CC3. For e
a
ch
Cha
nnel
Hop
p
ing
Time
Slots,
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QCA and
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Desi
gn an
d De
velo
pm
ent… (S. Deven
d
ra K. Verm
a)
275
the Source/User Li
nks are
alloca
ted to the Bus Ca
rri
ers (Ch
ann
el
s) where the S0 is linked t
o
B1, B3, B0 and B2 in
seq
uen
ce
corre
s
pondi
ng to th
e Ch
ann
el/Freque
ncy
Hop
p
ing Tim
e
Slots
t0, t1,
t2 and t3 as sho
w
n b
e
low. The PS
D-Ch
a
nnel
Hoppin
g
Pattern is sh
own in Figure 8.
Figure 8. PSD-Cha
nnel
Hoppin
g
Pattern
BUS C
A
RRI
ER
HOPPING TIME SLOT
(Linked to
Source
)
t0
t1
t2
t3
B0
S1
S3
S0
S2
B1
S0
S2 S3 S1
B2
S3 S1 S2
S0
B3
S2
S0
S1 S3
The Simulati
on Model u
s
i
ng CADE
NCE (for
1V and
45 nm scal
e
) is analysed
and it is
found that th
e perfo
rma
n
c
e of the
Ci
rcuit M
odel f
o
r Swit
ch M
a
trix is verifi
ed an
d quali
f
ied
function
ally.
6.2. PSD-Q
CA
M
O
DEL
The PSD_
Q
CA Model i
s
desig
ned
an
d develop
ed
usin
g the Q
C
ADe
s
ig
ne
r Tool with
QCA Cell si
ze < 20
nm, a
nd its pe
rformance is
a
n
a
lysed a
nd q
ualified. The
PSD-Q
CA M
odel
and PSD-QCA Model Anal
ysis are sh
own in Figure 9 & Figure 10.
Figure 9. PSD-QCA Mod
e
l
Figure 10. PSD-QCA Mod
e
l
Analysis
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276
The PSD-QCA Logic is d
e
fined a
s
follo
w
s
:
Cas
e
1: C0 Control Link is selected:
QCA AND Lo
gic 0: B0 = m
(
C0,S0,0
)
=
m(1,S0,0)
= S0
QCA AND Lo
gic 1: B1 = m
(
C0,S3,0
)
=
m(1,S3,0)
= S3
QCA AND Lo
gic 2: B2 = m
(
C0,S2,0
)
=
m(1,S2,0)
= S2
QCA AND Lo
gic 3: B3 = m
(
C0,S1,0
)
=
m(1,S1,0)
= S1
Cas
e
2: C1 Control Link is selected:
QCA AND Lo
gic 0: B0 = m
(
C1,S1,0
)
=
m(1,S1,0)
= S1
QCA AND Lo
gic 1: B1 = m
(
C1,S0,0
)
=
m(1,S0,0)
= S0
QCA AND Lo
gic 2: B2 = m
(
C1,S3,0
)
=
m(1,S3,0)
= S3
QCA AND Lo
gic 3: B3 = m
(
C1,S2,0
)
=
m(1,S2,0)
= S2
Cas
e
3: C2 Control Link is selected:
QCA AND Lo
gic 0: B0 = m
(
C2,S2,0
)
=
m(1,S2,0)
= S2
QCA AND Lo
gic 1: B1 = m
(
C2,S1,0
)
=
m(1,S1,0)
= S1
QCA AND Lo
gic 2: B2 = m
(
C2,S0,0
)
=
m(1,S0,0)
= S0
QCA AND Lo
gic 3: B3 = m
(
C2,S3,0
)
=
m(1,S3,0)
= S3
Cas
e
4: C3 Control Link is selected:
QCA AND Lo
gic 0: B0 = m
(
C3,S3,0
)
=
m(1,S3,0)
= S3
QCA AND Lo
gic 1: B1 = m
(
C3,S2,0
)
=
m(1,S2,0)
= S2
QCA AND Lo
gic 2: B2 = m
(
C3,S1,0
)
=
m(1,S1,0)
= S1
QCA AND Lo
gic 3: B3 = m
(
C3,S0,0
)
=
m(1,S0,0)
= S0
7.
PSD (Progra
mmable Securit
y
De
v
i
ce)–2
There are three types of E
n
cryptio
n
-ba
s
ed
PSD-2 Mo
dels: a
)
PSD-2 Model
-A, b) PSD-2
Model
-B and
c) PSD-2 M
odel-C. The
r
e are 1
6
Encryption Code
s (ECs) defin
ed and i
denti
f
ied
with
Cod
e
No. (Cn).
One
Co
de
No. i
s
sel
e
cte
d
ran
domly an
d th
e corre
s
po
nd
ing En
cryptio
n
Cod
e
(EC) is identified an
d use
d
for E
n
cryptio
n
Scheme
s
. A Ta
ble with
Cod
e
No. (Cn
)
a
nd
Encryptio
n
Code
s (ECs) i
s
define
d
as f
o
llows:
CO
DE NO. (
C
n)
:
ENC
R
YPTIO
N CO
DE (E
C
)
:
C0:
1111
1111
C1:
1010
1010
C2:
0101
0101
C3:
1100
1100
C4:
0011
0011
C5:
1111
0000
C6:
0000
1111
C7:
1100
0011
C8:
1110
0111
C9:
0001
1000
C10:
1100
0011
C11:
0011
1100
C12:
1000
0001
C13:
0111
1110
C14:
1100
1111
C15:
1111
0011
7.1. PSD-2
Mod
e
l-A
In this model
, at the XMTR-En
d
, one
Cod
e
No. (Cn) is
sele
cte
d
ran
domly and the
corre
s
p
ondin
g
8
-
bit En
cry
p
tion
Cod
e
(EC) i
s
i
dentifi
ed, an
d 8
-
bit
Data
(D) to
be tran
smitted is
XOR
with it
and tran
smitted alo
ng
wit
h
the
En
cryption Code
(E
C). At the
RCVR-End, th
e
received En
crypted
Data i
s
XO
R with t
he En
cryptio
n
Co
de
(EC)
and the t
r
an
smitted Data
(D) i
s
retrieve
d. A PSD-2 Mo
del
-A is sho
w
n in
Figure 1
1
.
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QCA and
CM
OS Nanote
c
h
nolog
y Based
Desi
gn an
d De
velo
pm
ent… (S. Deven
d
ra K. Verm
a)
277
Figure 11. PSD-2 M
odel
-A
7.2. PSD-2
Mod
e
l-B
In this model
, at the XMTR-En
d
, one
Cod
e
No. (Cn) is
sele
cte
d
ran
domly and the
corre
s
p
ondin
g
8-bit En
cry
p
tion
Cod
e
(EC) i
s
i
dentifi
ed, 8-bit Data
(D) to
be
tra
n
smitted
is XOR
with it. Th
e
XOR
Data
a
nd the
En
cry
p
tion
Cod
e
(EC)
both
are
furthe
r inve
rted o
r
XO
R
with
‘1111
1111’
separately an
d tran
smitted
.
At the
RCVR-En
d, the Encrypte
d Data and En
cryp
tion
Cod
e
are first inverted or XOR with ‘11
1
1111
1’
sep
a
rately and then they are XOR togethe
r and
the trans
m
itted Data (D) is
retrieved.
A PSD-2 Mo
del
-B is sho
w
n in
Figure 1
2
.
Figure 12. PSD-2 M
odel
-B
7.3. PSD-2
Mod
e
l-C
In this
model
, the Ta
ble
with
Cod
e
No. (Cn) an
d
Encryptio
n
Code
s (E
C) is available
at
both
XMTR-E
nd a
nd RCVR-En
d
. At the XMTR-En
d
, a
Code No. (Cn
)
is sele
cted
randomly an
d
th
e
corre
s
p
ondin
g
8-bit En
cry
p
tion Co
de
(EC) i
s
sel
e
ct
ed and th
e 8
-
bit Data (D) t
o
be tra
n
smitt
ed is
XOR with it and tra
n
smitt
ed alon
g wit
h
the Co
d
e
No. (Cn). At the RCV
R-E
nd, the re
cei
v
ed
Encrypte
d Data is XOR
with the Encryption Co
d
e
(EC)
co
rresp
ondin
g
to the
Code
No. (Cn)
received, and
the transmitt
ed Data (D) is retr
i
e
ved. A PSD-2 Mod
e
l
is sho
w
n in
Figure 13.
Figure 13. PSD-2 M
odel
-C
8.
PSD-2 Logic
Circuit Mod
e
l
A PSD-2 Log
ic Ci
rcuit for
both XMTR-END
a
nd RCVR-END i
s
d
e
sig
ned a
s
shown in
Figure 14.
Figure 14. PSD-2 L
ogi
c Ci
rcuit
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278
8.1.
PSD-2 CMO
S
Model
The PSD-2 X
O
R-CM
OS M
odel a
nd th
e
PSD-2 X
O
R-CMOS M
odel
Analysi
s
a
r
e
sh
own
in Figure 15 a
nd Figu
re 16.
Figure 15. PSD-2
CMOS M
odel
Figure 16. PSD2 CM
OS M
odel Analysi
s
8.2. PSD-2
Q
CA
Model
The PSD-2 Q
C
A Model is
desi
gne
d and
developed a
nd its perfo
rm
ance is analy
s
ed an
d
qualified. T
h
e
PSD-2 Q
C
A
Model
and
th
e PSD-2
QCA Model
Anal
ysis
are
sho
w
n in
Figu
re l
7
&
Figure 18.
Figure 17. PSD-2
QCA Mo
del
Figure 18. PSD-2
QCA Mo
del Analysi
s
The PSD-2 Q
C
A Logi
c is d
e
fined a
s
follows:
QCA NA
ND L
ogic 1: x
1
= (
m
(EC,D,
0)
)’
QCA NA
ND L
ogic 2: x
2
= (
m
(EC,x
1
,0)
)
’
QCA NA
ND L
ogic 3: x3 = (m(x1,D,0
))’
QCA NA
ND L
ogic 4: x4 = (m(x2,x3,0))’
9. Conclu
sion
Our Re
se
arch Wo
rk
i
s
fo
cu
sed on
Appli
c
ati
on of
CM
OS-VLSI an
d Q
C
A
Nan
o
technol
ogy in WiMA
X/WiFi/Satellite and ot
h
e
r Wirel
e
ss Co
mmuni
cation Systems.
A PSD
(Prog
r
am
mab
l
e Security Device) is d
e
sig
ned, dev
elope
d mode
lled and qua
lified base
d
on
CMOS
Nan
o
tech
nolo
g
y (to
the scale
of
45 nm
and
1.0v) and
Q
C
A Nan
o
technol
ogy (to the
scale
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2302-4
046
QCA and
CM
OS Nanote
c
h
nolog
y Based
Desi
gn an
d De
velo
pm
ent… (S. Deven
d
ra K. Verm
a)
279
of Cell
size < 20 nm
), appl
icabl
e to Wi
MAX/WiFi
/Satellite Wirel
e
ss Commu
nication System
s i
n
Real
-time En
vironme
n
t to
provide Se
cu
rity and Prim
acy. This Research Work will lead to Design
& Develop o
f
Smart &
Small Device
s and p
r
ovid
e Archite
c
tu
ral Innovation
,
Value Added
Service
s
, Full
Scale QoS (Quality of Serv
ice) an
d Hig
her Se
curity & Privacy.
10. Futur
e
Wor
k
Our
Re
sea
r
ch Wo
rk
will a
ddre
s
s Lon
g
term Te
chni
cal Chall
eng
e
s
, and it will focu
s on
De
sign,
Dev
e
lopme
n
t an
d Tra
n
sfo
r
ma
tion of CM
OS-VLSI Circ
uits
/Devices
/S
ys
tems
int
o
QCA
Nan
o
technol
ogy for WiM
AX/WiFi/Satellite and
oth
e
r Wi
rele
ss
Comm
uni
cati
on Systems to
achi
eve Lo
w Power, L
o
w
Voltage,
Miniaturi
z
atio
n, Added F
eature
s
/Fu
n
ct
ionalitie
s an
d
Reliability.
Referen
ces
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