TELKOM
NIKA Indonesia
n
Journal of
Electrical En
gineering
Vol. 12, No. 10, Octobe
r 20
14, pp. 7253
~ 726
1
DOI: 10.115
9
1
/telkomni
ka.
v
12i8.551
2
7253
Re
cei
v
ed
De
cem
ber 2
7
, 2013; Re
vi
sed
May 26, 20
14
; Accepte
d
Ju
ne 17, 201
4
Design of ECC Controller and its Validation Based on
FPGA
Cao Yan*, Du Lixia, Wan
g
Zheng
y
u
Lanz
ho
u Jiaoto
ng Un
iversit
y
, Lanz
ho
u, Chin
a
*Corres
p
o
ndi
n
g
author, e-ma
i
l
: 1917
20
356
@
qq.com
A
b
st
r
a
ct
With the developm
ent of embedded system
s and
t
he
mobile internet, embedded sys
tem
s
ar
e
equ
ipp
ed w
i
th mor
e
an
d mor
e
me
mory cap
a
city. Memory
relia
bi
lity beco
m
es a foc
u
s to us. T
hough p
a
rit
y
checki
ng h
a
s bee
n ap
pli
ed i
n
e
m
be
dd
ed s
ystems, it
on
ly
can detect er
rors, but cann
ot correct the
m
.
T
herefore, r
e
s
earch
ing
b
e
tter dat
a
protect
i
on
bec
o
m
es
an
importa
nt
topic
for
the deve
l
op
ment o
f
embe
dde
d sys
tems. In dev
el
opi
ng a
new
a
l
gorit
hm
an
d a
pplyi
ng
it to e
m
b
e
d
ded syst
ems, trans
pl
an
ting
goo
d d
a
ta pr
otection tec
h
n
o
l
ogy us
ed
in
H
P
Cs are
poss
i
ble s
o
luti
ons.
Of these tw
o optio
ns, the fo
rme
r
requ
ires a l
o
n
g
deve
l
o
p
m
ent
time, w
h
ile th
e latter may b
e
easi
e
r to rea
l
i
z
e
a
nd a
pply,
saving ti
me
a
n
d
m
o
ney. In the
HPC fiel
d, ther
e are
m
any data protecti
on technologies s
u
c
h
as EC
C, chipkill, lockstep a
n
d
so on. Taking t
he featur
es
of the embedded
system
s in
to c
onsideration, E
CC
m
a
y be the best technology
for transpl
anta
t
ion to th
e e
m
b
e
d
ded syst
em. Th
ere
ar
e
tw
o reasons.
First, becaus
e of the syste
m
’s
portability, it is hard to
suppor
t 4 DIMMs. Th
ere is no poss
i
bility t
hat chipk
ill or l
o
ckst
ep c
an be
appli
ed i
n
the embedded
system
. Se
condly, ECC is
more general
and can support all series
of SDRAM, either
4-bit
or 8-bit. Henc
e this
paper f
o
cuses
on E
C
C applic
ation
on embedded system
s.
ECC is an advanced
techno
lo
gy for
me
mory
erro
r detecti
on
an
d correct
i
on,
w
h
ich is
use
d
to su
pport
h
i
gh r
e
li
ab
ility
of
computers. It i
s
w
i
dely
use
d
in s
e
ver
me
mo
ry w
h
ile
it
ca
n
detect 2-
bit
error a
nd c
o
rrect
1-bit
error. T
h
i
s
pap
er intro
duc
es the ECC
al
g
o
rith
m, an
d the
n
discuss
es th
e more g
e
n
e
ral
correction c
o
d
i
ng
mat
h
e
m
atic
s,
reali
z
i
n
g it
by
p
r
ogra
m
mi
ng
w
i
th VHD
L
. After
finis
h
in
g th
ese
parts, a
d
e
b
u
g
exp
e
ri
me
nt is
execute
d
on t
h
e
Altera Stratix
IV fami
ly F
P
GA. F
i
nally, t
he
pap
er
ana
ly
z
e
s th
e si
mulati
on r
e
sults
an
d g
i
ves s
o
m
e
sugg
estio
n
s for impr
ovin
g the
perfor
m
a
n
ce of
ECC control
l
er
s.
Ke
y
w
ords
: ECC, Ha
mmin
g codi
ng, FPGA,
VHDL
Copy
right
©
2014 In
stitu
t
e o
f
Ad
van
ced
En
g
i
n
eerin
g and
Scien
ce. All
rig
h
t
s reser
ve
d
.
1. Introduc
tion
Memory is a
n
electroni
c stora
ge devi
c
e,
and all ele
c
troni
c
stora
ge devices h
a
ve the
potential to i
n
co
rrectly ret
u
rn info
rmati
on diffe
re
nt from what was o
r
igin
ally store
d
. Some
techn
o
logie
s
are
mo
re li
ke
ly than oth
e
rs to
do
this.
DRAM
mem
o
ry, be
cau
s
e
of its n
a
ture, is
likely to return occa
sional
memory e
rro
rs. As an
imp
o
rtant pa
rt of the co
mp
uter, memory errors
can
cau
s
e
some un
expe
cted results [
1
]. With t
he increa
se of t
he u
s
e of DRAM mem
o
ry in
mode
rn serv
ers a
nd PCs,
memory RA
S features
a
r
e encounte
r
e
d
more a
nd more by ente
r
pri
s
e
and commo
n use
r
s [2].
There are t
w
o kind
s of errors th
at can t
y
pica
lly occur in a memory
system. The first is
calle
d a
rep
e
a
table o
r
h
a
rd erro
r which
is
ca
u
s
e
d
by
defect
s
withi
n
the
DRAM
packa
ge a
m
o
n
g
other thing
s
. It cannot be
correcte
d. The
second i
s
cal
l
ed a tran
sien
t or soft erro
r
whi
c
h is mai
n
ly
cau
s
e
d
by ch
arge
d pa
rticle
s from natu
r
al
ly occu
rri
ng b
a
ckgroun
d ra
diation or
co
smic ray
s
. It can
be te
chn
o
logi
cally det
ecte
d an
d corre
c
ted. Parity
ch
ecking,
as
a
basi
c
fo
rm of
error dete
c
ti
on,
has be
en ad
opted in mod
e
rn PCs. It o
n
ly can dete
c
t 1-bit erro
rs
but cann
ot correct them. This
error dete
c
tio
n
may satisfy
PC RAS de
mand
s, but it
is far from
sat
i
sfying the de
mand
s of se
rve
r
RAS. In mod
e
rn
se
rvers,
ECC
m
e
mo
ry provid
es
a g
ood level
of reliability and
has
be
com
e
the
stand
ard te
ch
nology today
on almo
st every se
rver.
This thes
is firs
t introduces
the ECC
algor
ithm, th
e
n
ba
se
d o
n
the ECC
alg
o
rithm,
sho
w
s a de
si
gn for an E
C
C co
ntroll
er,
whi
c
h c
an be
used fo
r me
mory syste
m
s or
som
e
ECC
related
ap
plications, a
nd
concl
ude
s
with a valid
at
io
n of the
algo
rithm on
the
Altera Stratix
IV
family FPGA
[3-5].
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 23
02-4
046
TELKOM
NI
KA
Vol. 12, No. 10, Octobe
r 2014: 725
3
– 7261
7254
2. ECC Encodi
ng Algorith
m
ECC
co
ding
i
s
a
n
SEC-DED (Sin
gle
-
bi
t Erro
r Co
rre
ction, Dou
b
le
-bit
Er
ror
D
e
tection
)
codi
ng
whi
c
h is for obtai
ni
ng hi
gher
reli
ability.
The
origin of E
C
C
codi
ng i
s
Hamming
coding,
whi
c
h was first prop
osed b
y
Hamming in
1950.
Hammi
ng co
de is a co
de that permit
s
correctin
g
sin
g
l
e bit erro
rs.
He a
s
sume
s that the
data to be tra
n
smitted con
s
ist
s
of a cert
ain numb
e
r o
f
information bits u, and he
adds to these a
numbe
r
of ch
eck bit
s
p
su
ch th
at if a
bl
ock i
s
re
ceiv
ed that
ha
s
a
t
most
a bit
e
rro
r, the
n
p
can
identify the erro
r bit po
siti
on (eith
e
r the
error o
c
cu
rred in the bl
o
ck
of inform
a
t
ion bits o
r
in
the
block of the check bits, it can be ide
n
tified). Sp
e
c
ially
, in Hamming
code p i
s
interp
reted a
s
a
n
integer which
is
0 if the
r
e i
s
n
o
e
r
ror, a
n
d
othe
rwi
s
e
is 1-o
r
igi
n
ind
e
x
of the bit th
at is i
n
e
r
ror.
Let
k be the
num
ber of info
rm
ation bits a
n
d
m the num
b
e
r of che
ck
bits. Becau
s
e t
he m che
ck b
i
ts
must ch
eck n
o
t only the informatio
n bits but also
them
selve
s
, the value of p must be interpret
e
d
as
an inte
ger, rangi
ng fro
m
0 to m
+
k,
whi
c
h h
a
s m
+
k+1
distin
ct
values. B
e
cause m
bits
can
dist
ing
u
is
h 2
m
ca
se
s,
we
must
hav
e:
Error! Re
fere
nce
s
o
urce not
found.
;
(1)
This i
s
kn
own a
s
the
Ha
mming
rule. I
t
applie
s to
a
n
y singl
e bit
error
co
rrecti
ng (SE
C
)
binary FE
C (Forward Erro
r Co
rrectin
g
, just a me
th
od that pe
rm
it the receiver to corre
c
t a
transmissio
n
error
witho
u
t asking t
he send
er
f
o
r mo
re i
n
formatio
n ab
out it or fo
r a
retra
n
smi
s
sio
n
) blo
c
k co
d
e
in whi
c
h all
of the
transmitted bits m
u
st be
che
cked. Accordi
n
g to
Hammi
ng rul
e
, we can
ca
lculate that the numb
e
r of
check bits f
o
r 64-bit information bits is 7
.
Based o
n
these ad
ded
check bits, ECC
codin
g
a
dds an
othe
r bit for parity che
c
k of all bits.
Con
s
e
quently
, to a 64-bit informatio
n bl
ock, ECC
co
ding n
eed
s 8
bit che
c
k blo
c
k. The foll
owi
ng
are the
steps
to generate a
che
ck bl
ock
p:
1) Cal
c
ul
ate the numb
e
r of
che
ck bit
s
according to the
Hammin
g
rul
e
;
2) Put the ch
eck bits in th
e power of 2
pos
ition
s
, a
nd put the in
formation bit
s
in the
other po
sition
s [6];
3) Cal
c
ul
ate the ch
eck bits
the SEC nee
ds. The meth
od is a
s
follo
ws:
a) Let the l
e
a
s
t sig
n
ifica
n
t bit of p be p
0
.
The value
of p0 is th
e p
a
rity che
c
k re
sult of
the bits in the
position
s
1,3
,
5,7….(in bin
a
ry, the
least
signifi
cant of these po
sition
s numb
e
r i
s
1
)
;
b) Let the ne
xt from the least sig
n
ifica
n
t
bit of p be
p1. The valu
e of p1 is the parity
che
c
k re
sult
of the bits i
n
the po
sitio
n
s 2,
3,6,7,1
0
,
11….(in bi
n
a
ry, the next from the le
ast
signifi
cant of the po
sition n
u
mbe
r
is 1);
c) Simil
a
rly, l
e
t the third
from lea
s
t si
gni
fic
ant bit of p
be p2. T
he va
lue of p
2
is
m
ade a
n
even parity check on tho
s
e positio
ns th
at have a 1
in their third f
r
om lea
s
t sig
n
ificant po
siti
on
numbe
r, nam
ely position
s
4, 5, 6, 7, 12,
13, 14, 15, 20
, …
d) Co
ntinuin
g
,
calcul
ate the other
che
c
k bits in the sa
me way;
4) Fin
a
lly, add a pa
rity ch
eck bit, the value of
which
is the pa
rity che
c
k re
sult
of the
informatio
n bi
ts u and the check bits p.
Table 1 is the
che
ck tabl
e for 64
-bit data
ECC en
codi
ng.
Table 1. 64
-bi
t
Data ECC E
n
co
ding
111
110 101 100 011 010
001
000
1000
D63
D62
D61
D60
D59
D58
D57
CB7
0111
D56
D55
D54
D53
D52
D51
D50
D49
0110
D48
D47
D46
D45
D44
D43
D42
D41
0101
D40
D39
D38
D37
D36
D35
D34
D33
0100
D32
D31
D30
D29
D28
D27
D25
CB6
0011
D25
D24
D23
D22
D21
D20
D19
D18
0010
D17
D16
D15
D14
D13
D12
D11
CB5
0001
D10
D9 D8 D7 D6 D5
D4
CB4
0000
D3
D2
D1
CB3
D0
CB2
CB1
No
err
o
r
From table 1,
we ca
n cal
c
u
l
ate each ch
e
ck bit (CB1
～
CB7), for exa
m
ple,
CB1=
D0
⊕
D1
⊕
D3
⊕
D4
⊕
D6
⊕
D8
⊕
D1
0
⊕
D1
1
⊕
D1
3
⊕
D1
5
⊕
D1
7
⊕
D1
9
⊕
D2
1
⊕
D2
3
⊕
D25
⊕
D26
⊕
D28
⊕⊕
D30
⊕
D3
2
⊕
D3
4
⊕
D3
6
⊕
D3
8
⊕
D4
0
⊕
D4
2
⊕
D4
4
⊕
D4
6
⊕
D4
8
⊕
D5
0
⊕
D
52
⊕
D54
⊕
D56
⊕
D57
⊕
D59
⊕
D61
⊕
D63
；
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
2302-4
046
De
sign of ECC Co
ntrolle
r
and its Va
lida
t
ion Based o
n
FPGA (Cao
Yan)
7255
After cal
c
ul
ating
CB1
～～
CB
7 out,
we
d
o
an
overall
parity
che
c
k fo
r
D0
D63 a
n
d
CB1
～
CB
7, and the re
sult is CB8.
2.1. ECC De
coding and
Corre
cting
Algorithm
As me
ntione
d above, E
C
C e
n
co
ding
a
pplie
s
an
SEC-DED co
de.
So the
re
cei
v
er can
detect
errors by the
ch
e
c
k bit. Tabl
e
2 d
e
mon
s
trates
ho
w th
e re
ceive
r
d
e
tects erro
rs.As
indicated in
Table 2, if t
here
are no
errors, t
he o
v
erall pa
rity (the p
a
ri
ty of the entire n
-
bit
received
code word)
will be even
and the syndrome of
the (n-1)-bit
SEC port
ion
of the bl
ock
will
be 0. If there
is on
e-bit e
r
ror, then the
o
v
erall pa
rity of the received
block
will be
odd. If the error
occurre
d
in the overall pa
rity bit,
then the syndro
m
e wil
l
be 0. If the erro
r occu
rred
in some oth
e
r
bit, then the syndrom
e will
be non
ze
ro a
nd it will indica
te whi
c
h bit i
s
in erro
r. If there i
s
a two
-
bit
error, then th
e overall p
a
rit
y
of the recei
v
ed bloc
k
will
be even. If one of the two
erro
rs is in t
he
overall
parity
bit, then the
o
t
her i
s
in t
he
SEC po
rti
on
of the blo
c
k. In this
ca
se
th
e syn
d
ro
me
will
be non
ze
ro
(and will i
ndicate the bit in the SEC po
rt
ion that is in
error). If the errors are bot
h in
the SEC po
rtion of the blo
ck, th
e
n
the
syndrome
will
also b
e
n
o
n
z
ero, althou
g
h
the proble
m
is
hard to explai
n this two bits location [7-1
0].
Table 2. Re
ceiver Co
ncl
u
sion of Erro
r Detection
Possibi
lity
Receiver Conclusion
Errors
Ov
eral
l
Pari
t
y
S
y
ndro
m
e
0
even 0 No
err
o
r
1 odd
=0
O
v
er
all par
ity
bit is in er
r
o
r
≠
0
S
y
ndro
m
e indicates the erro
r
2 even
≠
0
Double er
ror, ca
nnot be corr
ecte
d
If there is one-bit error, t
he correction
will be execut
ed when
the
error i
s
detected. The
syndrome
wil
l
indi
cate the
error lo
catio
n
. The
synd
rome i
s
cal
c
u
l
ated a
s
follo
ws. After the
receiver
re
cei
v
es the data,
it will cal
c
ulat
e t
he ch
eck b
i
ts again
by the ECC en
co
ding alg
o
rith
m,
if the cal
c
ulat
ed re
sult i
s
r,
then do XO
R op
eratio
n
with the
che
c
k blo
c
k p an
d
the re
sult r,
and
the result is syndrom
e [11].
2.2. More Ge
neral Con
s
id
eration
s
of E
rror Corr
ec
tion.
In the last two se
ction
s
, th
e ECC
algo
ri
thm
ba
sed on
Hammi
ng co
ding wa
s
discussed.
This sectio
n will take level
s
of error correc
tio
n
and d
e
tection
cap
a
b
ility greater
than SEC-DE
D
into con
s
id
eration.
The ce
ntral
con
c
e
p
t in the theory of ECC is tha
t
of Hamming Distan
ce,
whi
c
h is
approp
riate t
o
call thi
s
a
distan
ce fu
nction
be
ca
u
s
e it satisfie
s the d
e
finition of a di
st
ance
function u
s
e
d
in linear alg
e
b
ra:s
Here
d(x, y)
denote
s
th
e
Hammi
ng
distance
bet
wee
n
code
word
x and
y, wh
ich fo
r
brevity we wil
l
call simply the dista
n
ce b
e
twee
n x and
y.
Based
o
n
th
e ab
ove
co
n
c
ept,
we
will
now turn thi
s
que
stion
a
r
o
und
and
a
s
k, “F
or a
given co
de le
ngth n and mi
nimum di
stan
ce d, ho
w ma
ny code
word
s are p
o
ssibl
e?”
For minim
u
m distan
ce 1, suppo
se the
code word
s a
c
cording to the
following forum:
A (n, 1) =2
n
For mi
nimum
distan
ce
2,
we
kno
w
fro
m
the
si
ngle
parity bit exa
m
ple that b
u
t A (n, 2
)
can
not ex
cee
d
fo
r th
e fo
llowing
rea
s
o
n
. Suppo
se
there
is a
co
d
e
of le
ngth
n
and
minim
u
m
distan
ce
2 th
at has mo
re t
han
cod
e
wo
rds.
Del
e
te a
n
y one
col
u
m
n
from th
e
co
de words. T
h
is
prod
uces
a
code of le
ngth
and mi
nimu
m dista
n
ce
at
least
1 (d
elet
ing
a colum
n
can red
u
ce
the
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 23
02-4
046
TELKOM
NI
KA
Vol. 12, No. 10, Octobe
r 2014: 725
3
– 7261
7256
minimum di
st
ance by at most 1), an
d of size ex
ce
e
d
i
ng. Thu
s
it has cont
radi
cting equ
ation (6).
H
e
nc
e
A(
n
-
2)=
2
n-
1
What
abo
ut t
he di
stan
ce
3
?
Th
at is an
unsol
ved
pro
b
lem, in
the
sen
s
e
that n
o
formul
a
or re
asona
bl
y easy mean
s of cal
c
ul
ating it is kn
own. Of cou
r
se
many spe
c
if
ic value
s
of are
kno
w
n, and
some b
oun
d
s
are kno
w
n,
but the ex
a
c
t value is unkn
o
wn in most ca
se
s. When
equality hold
s
in Equation
(1), it
represents the solu
tion to this
problem for the
case d=3. Let
Equation (1)
be re
written:
Here k is the
numbe
r of informatio
n bi
ts,
so is the
numbe
r of co
de wo
rd
s. Hence we
have:
Similarly, for the dista
n
ce n
=
7, and
so on
. An interestin
g relation i
s
that for
,
This i
s
kno
w
n as th
e sp
h
e
re
-pa
c
king
boun
d,
whi
c
h
can
achieve
a highe
r lev
e
l of error
corre
c
tion a
n
d
detectio
n
capability than
SEC-DE
D
[12].
3. ECC Co
nt
roller Design
Based o
n
the research of
ECC the error
dete
c
tion
and co
rrectio
n
algorithm,
with the
top-do
wn a
n
d
modular d
e
sign method
ol
ogy, an ECC controll
er ha
s bee
n desi
g
ned. Figu
re 1
is
the block dia
g
ram of a 64
-bit ECC co
ntroller
an
d its a
pplication in the memo
ry system.
Figure 1. ECC Co
ntrolle
r
Blo
ck
Diag
ra
m and its App
lication
From th
e Fi
g
u
re
1, we
ca
n see, the E
C
C c
ontroll
er co
nsi
s
ts of
an
ECC
en
co
de
r
,
ECC
control logi
c and ECC de
cod
e
r an
d co
rre
ctor. Th
e ECC en
co
der is in charge of encodi
ng the
informatio
n d
a
ta with
che
c
k bits,
while t
he ECC de
co
der a
nd
co
rre
ctor i
s
in
cha
r
ge of de
co
din
g
the re
ceived
block a
nd do
ing erro
r det
ection
and
correctio
n
. If a two-bit error dete
c
ted
and
uncorre
ctable
,
the ECC c
ontrol logi
c
will se
nd an
interru
pt to the upper
use
r
logi
c, which
indicates that
an uncorre
ctable error
o
c
curred. EC
C co
ntrol log
i
c co
nsi
s
ts of
many regi
sters
whi
c
h can be
divided into three type
s as follows:
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
2302-4
046
De
sign of ECC Co
ntrolle
r
and its Va
lida
t
ion Based o
n
FPGA (Cao
Yan)
7257
Config
uratio
n
Regi
ste
r
(CR),
whi
c
h i
s
use
d
for
re
co
rding
the thre
shol
d of the
occurrin
g
1-bit or 2
-
bit errors. On
ce
over the thre
s
hold, the co
ntrol logi
c will send an inte
rrupt.
Status Regi
ster (S
R),
whi
c
h is
used for
reco
rding th
e
type of erro
r
whi
c
h o
c
cu
rred, erro
r
locatio
n
and
ECC syn
d
ro
me.
Cou
n
ter, use
d
for re
co
rdin
g the numbe
r of 1-bit and 2
-
bit errors.
After the design
of ECC cont
roller archit
ecture, each
module
will be
realized by
prog
ram
m
ing
with the VHDL langu
age [1
3-15].
4. FPGA Validation
Validation
an
d sim
u
lation
is an
impo
rt
ant
step
in t
he EDA
de
si
gn. The
pu
rpose of
validation i
s
t
o
en
su
re
the
desi
gn
accu
racy. A
fter finis
h
ing the ECC
c
ont
roller des
i
gn, a
FPGA
validation h
a
s
be
en
executed on
the
Altera Straix
family FGPA. Ac
cording to the Altera E
D
A
desi
gn
sol
u
tion, two
devel
opment
kit
s
(Quartu
s II 10
.1 and
Mo
del
Sim 6.6c)
ha
ve bee
n
cho
s
en
for this valida
t
ion. At first,
a proje
c
t was created
in th
e Qu
artu
s II
10.1, then
so
urce file
s
were
adde
d to the
proje
c
t and
a full compil
ation mad
e
. Figure 2 is t
he full co
mpil
ation re
sult [
16].
Figures 3 a
n
d
4 sho
w
the a
nalysi
s
& synthesi
s
re
sult a
nd the fitter result individu
ally.
Figure 2. ECC Co
ntrolle
r
Full Com
p
ilati
on Re
sult
Figure 3. Analysis & Synthesi
s
Com
p
ilat
i
on Re
sult
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 23
02-4
046
TELKOM
NI
KA
Vol. 12, No. 10, Octobe
r 2014: 725
3
– 7261
7258
After finishin
g a full
comp
ilation, an
RT
L sim
u
lation i
s
exe
c
uted i
n
the Mod
e
lSim 6.6c.
The pu
rpo
s
e
of the RTL si
mulation is to
find some un
strain
ed tra
c
e
in the desig
n
.
Before an RTL
simulatio
n
, you should
de
sign
a test b
ench, usi
ng a
PCB equip
p
ed with you
r
device.
Here, the
device i
s
j
u
st
the ECC
cont
rolle
r. In ad
dition, a te
st
be
nch sh
ould
contain som
e
sign
al
stim
ula
t
or
to drive the c
i
rc
uit to work
, whic
h is
al
so
desi
gne
d by VHDL p
r
o
g
ra
mming [17].
The
ECC con
t
roller RTL
si
mulation con
s
ist
s
of
an en
cod
e
r RTL si
mulation
a
nd decode
r
RTL sim
u
lation.
To a
memory sy
stem,
the
ECC encoder will work
if
a processor
executes a
write mem
o
ry
comma
nd. Fi
gure 5 i
s
the simulatio
n
re
sult of ECC e
n
co
ding.
Figure 4. Fitter Co
mpilatio
n
Re
sults
In Figure 3, dn is the inp
u
t data while
dq is
the ou
tput data, and cb
is the check bits
cal
c
ulate
d
by
the E
C
C en
coder.
Seein
g
from Fi
gur
e 5
,
we
ca
n find
the value
of
dq i
s
the
sam
e
as d
n
. In a m
e
mory
syste
m
, the ECC
d
e
co
der
and
correcto
r will
work if a p
r
o
c
e
s
sor
rea
d
s
data
from the me
mory. Due to
memory e
rro
rs occu
rri
ng ra
ndomly, to better obse
r
ve the de
code
r a
nd
corre
c
tor
RT
L
simulatio
n
; some e
rro
rs were inj
e
cte
d
i
n
to the si
gnal
stimulato
r
. Table 3 a
n
d ta
ble
4 are the VHDL source
co
des
of error injection [18].
Table 3
and
4 individually
use
d
a state
mach
i
ne to
stimulate the d
e
co
der
and
correcto
r
function. Fro
m
the source
code
s,
we know the stim
ulator contai
n
ed all types of 1-bit and 2
-
bit
errors. After
importin
g
the
test b
e
n
c
h
and
so
urce f
iles to
the
M
odel
sim a
nd
doing
an
RT
L
simulatio
n
, the result is sh
own a
s
the Fi
gure 6
Figure 5. ECC Enco
ding S
i
mulation Result
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
2302-4
046
De
sign of ECC Co
ntrolle
r
and its Va
lida
t
ion Based o
n
FPGA (Cao
Yan)
7259
Table 3. Errors
Injec
t
ed to the Information Bits
data:process
begin
wait for 40 ns;
Dp<=X"000000
000000000
1"; --inject single bit er
ror
,
Dp
(0) flip
wait for 40 ns;
Dp<=X"FF
F
F
F
FFF
FF
FF
FFEF
"
;
--i
nj
ec
t single bit error
,
Dp(4
) flip
wait for 40 ns;
Dp<=X"AAAAAAAAAAAAAAAF"; --inject double
b
i
t error
,
both
occurred at
the data
bits. Dp(0),Dp
(2)
both flip
wait for 40 ns;
Dp<=X"CCC
CC
CCCCC
CCC
CC
D";--inject doubl
e bit error; one
occurred at the data bit, the other occurred at t
he
check bit. Dp(0),
cb(0) both flip.
wait for 40 ns;
Dp<=X"F0
F
0F0
F
0F0
F
0F0
F
0";
--inject double bit error
,
b
oth occurred at the check bits, cb(1), cb(2) b
oth flip
wait for 40 ns;
Dp<=X"FF
FF0
0
00FF
FF00
00";
--inject single b
i
t error
,
cb(3
) flip
wait for 40 ns;
Dp<=X"FF
F
F
F
FFF0
000000
0"; -
-
no er
ror
end process;
Table 4. Errors Injecte
d
to the Ch
eck Bits
check_bit: process
begin
--inject single bit
error,Dp(0) flip
wait for 40 ns;
cb<=X"08";
--inject single bit
error,Dp(4) flip
wait for 40 ns;
cb<=X"EF";
--inject double bit erro
r; both occurred at the
data bi
ts. Dp(0),
Dp(2
)
both flip
wait for 40 ns;
cb<=X"58";
--inject double bit error
,
o
ne occurr
ed at the data
bit, the other
occurred at the check --bit. Dp(0
),cb(0)
both flip
wait for 40 ns;
cb<=X"30";
--inject double bit erro
r, both occurred at
the check
bits,cb(1),cb(2) b
oth flip
wait for 40 ns;
cb<=X"0A";
--inject single bit
error, cb(3) flip
wait for 40 ns;
cb<=X"E6";
-- no e
rro
r
wait for 40 ns;
cb<=X"CE";
end process;
Figure 6. ECC De
co
der a
nd Co
rrecto
r RTL Simulati
on Re
sult
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 23
02-4
046
TELKOM
NI
KA
Vol. 12, No. 10, Octobe
r 2014: 725
3
– 7261
7260
From Fi
gure
6 we
see, all
data is d
e
co
ded to
64
-bit
origin
al data
.
All 1-bit errors
are
corre
c
ted, in
addition, when it
occurred, the singl
e_bit_e
r
ror r
egiste
r
is in
cre
m
ente
d
b
y
1
automatically. Whe
n
2-bit errors o
c
curred, the
de
co
der
can
not d
e
co
de the
rig
h
t data, so t
h
e
state of o
u
tp
ut data
(dn
)
i
s
hig
h
imp
e
d
ance,
whi
c
h
i
s
sho
w
n i
n
t
he pe
rio
d
fro
m
131
744
ps
to
2101
44p
s, b
e
ca
use 2-bit error o
c
cu
rre
d 3 time
s in
the pe
riod, t
he do
uble
_bi
t_error
cou
n
t to
“0x03
”
as
sho
w
n in Figu
re
6.
In the Figure
6, each
sign
a
l
definition is
sho
w
n in the
Table 5.
Table 5. Sign
al Definition o
f
ECC De
cod
e
r and
Co
rre
ctor
S
y
m
b
ol
T
y
pe
Defini
tio
n
en
Input
Enable the deco
der and cor
r
ector
dp
Input
information bits of input data
，
6
4bit
cb
Input
check bits of inp
u
t data
，
8bit
dn Output
output
data
，
64b
it
single_bit_error
Output
1-bit err
o
r re
gi
ster, the thr
e
shold o
f
which is 3F
double_bit_err
o
r
Output
2-bit err
o
r re
gist
er, the thr
e
shold o
f
which is 1F
se_over
Output
interrupt
when ov
er the th
reshold
of 1-bit er
ror
de_over
Output
interrupt
when ov
er the th
reshold
of 2-bit er
ror
5. Impro
v
ement Sugge
sti
ons
From the FP
GA validation
results of th
e ECC
co
ntroller d
e
si
gn i
n
this the
s
is,
for better
perfo
rman
ce,
two sug
g
e
s
tions a
r
e given
as follows:
The ECC con
t
roller
wa
s on
ly validated in 64-bit mo
de i
n
this the
s
is, for some a
ppli
c
ation
needi
ng
sup
p
o
rt for
128
-bi
t
or mo
re, th
e timing i
s
p
r
elimina
r
y and
not validate
d
. The
r
efore, a
validation of a 128-bit or
more mo
de E
CC
controlle
r sho
u
ld be ex
ecute
d
after this the
s
is.
On the
flexibi
lity aspe
ct, d
y
namic re
co
n
f
igurabl
e a
r
ch
itecture
may
be a
go
od
ch
oice
for
desi
gning
a
n
ECC contro
ller whi
c
h suppo
rts
128
-b
it or mo
re
mode. T
h
is i
s
a
n
a
r
e
a
f
o
r
improvem
ent.
The
ECC co
ntrolle
r
only can co
rrect 1-bit
e
r
rors,
for some
ap
p
lication
s
whi
c
h
nee
d
highe
r reli
abil
i
ty,
the ECC
controlle
r is i
nade
quat
e. T
herefo
r
e, a n
e
w data p
r
ot
ection te
chn
o
l
og
y
maybe a
go
od choi
ce fo
r solving
su
ch p
r
o
b
lem
s
. Ho
w to d
e
s
ign
a ne
w
data p
r
ote
c
tion
techn
o
logy suppo
rting mul
t
iply bits correct
ion
will be
the next job after this thesi
s
.
6. Conclusio
n
ECC
coding
is important for ensuring
dat
a reliabilit
y. On the
aspect
of ECC coding
algorith
m
re
search, this th
esi
s
re
alize
d
a 64-
bit ECC controller by
VHDL p
r
og
ramming a
nd
its
validation on
the Altera Stratix IV Family FPGA.
The controlle
r can
apply to a me
mory controll
er
and some oth
e
r ECC relate
d appli
c
ation
s
pe
rfectly
be
cau
s
e it is smart and e
a
sy to transpla
n
t
in
an EDA appli
c
ation.
Referen
ces
[1]
Slay
man C, Ops A La carte.
Soft error tre
nds a
nd
mitig
a
tion tec
h
n
i
qu
es in
me
mory
devic
es.
Th
e
Confer
ence
of Reli
ab
ilit
y an
d Mainta
in ab
ilit
y S
y
mp
osium. 2
011.
[2]
Li Z
h
ang
hu
i, N
i
Xia
o
q
i
an
g, W
ang
Yo
ng
w
e
n.
Im
p
l
em
en
ta
ti
on
an
d
D
e
sg
i
n
Of Error-correc
t
ing
Codes In
High
Perfor
ma
nce Pr
ocessor
.
T
he 15th
Co
mputer E
ngi
ne
erin
g a
n
d
Ind
u
s
trial Me
etin
g (
C
onfer
ence)
.
201
1; A: 3-4.
[3]
HUA Bin, H
U
ANG Jie-
w
e
n, Z
H
OU Z
hang-
lun, SU
N
Jian-tao, Z
H
ANG Ping.
Desig
n
an
d
Impleme
n
tatio
n
of the
Data
ECC i
n
Hi
gh
Spee
d
a
nd
La
rge C
apac
it
y
Soli
d State St
orag
e S
y
stem
Based o
n
F
P
GA.
Journal of s
c
ienc
e of technol
ogy an
d en
gin
eeri
ng (Pu
b
l
i
catio
n_N
a
m
e)
.
2010; 18: 2-
3.
[4]
Chin-
L
u
ng S
u
, Yi-T
ing Yeh,
Che
ng-
w
e
n W
u
.
An inte
grate
d
ECC
and r
e
dun
da
ncy rep
a
i
r sche
m
e for
me
mory reli
ab
i
lity enh
anc
e
m
ent. T
he Defec
t
and F
ault T
o
l
e
ranc
e in VLSI
Systems.
DF
T
2005. 20t
h
IEEE Internatio
nal S
y
mp
osiu
m (Confere
n
ce
). 2005; 81-
89.
[5]
RW Hamming.
Error Detecti
ng an
d Error Correctin
g Co
des.
Journ
a
l o
f
the Bell System T
e
ch
nic
a
l
(Pulicati
o
n
_
Na
me)
. 1
950;
XXIX(2): 1-1
4
.
[6]
Nikol
ov H, Ste
f
anov. Efficient
Extern
al Mem
o
r
y
Interfac
e for Multi-Proc
e
ssor Platforms
Real
ized
on
FPGA Chips.
Journal of IEEE Com
p
uter
Society (Pulication_Name)
. 2005;
8(3): 23-27.
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
2302-4
046
De
sign of ECC Co
ntrolle
r
and its Va
lida
t
ion Based o
n
FPGA (Cao
Yan)
7261
[7]
F
eng Qin, Sh
an Lu, Yu
an
yuan Z
h
o
u
.
Exploiting ECC-
Memory for
Detecting Memory Leaks an
d
Memory C
o
rrut
i
on
Duri
ng Pr
o
ductio
n
R
uns.
High-P
e
rforma
nce
C
o
mp
uter Architecture.
H
P
CA-11,1
1
th
Internatio
na
l Symp
osi
u
m (Co
n
ferenc
e). 200
5; 291-3
02.
[8]
Xi
ng
jun Z
h
ang
, Endon
g W
a
n
g
, Dong Z
h
an
g etc.
Softw
are-Base
d Dete
cting an
d Rec
o
veri
ng fr
o
m
ECC-Mem
o
ry
Faults”
,
In In
tel
lige
n
t Netw
orki
ng an
d Coll
ab
o
r
ative System (
I
NcOS).
T
h
ird
Internati
o
n
a
l
Confer
ence (C
onfere
n
ce
). 20
11; 715-
71
9.
[9]
Doe Hy
un Yoon, Mattan Erez.
Memory M
app
ed ECC: L
o
w
-
Cost Error Protection for L
a
st Leve
l
Cach
e
.
Procee
din
g
IS
CA 0
9
Proc
ee
din
g
s of t
he
36th
an
nua
l I
n
ternati
o
n
a
l S
y
mp
osi
u
m (C
o
n
ferenc
e) o
n
Comp
uter Arch
itecture. 200
9; 116-
127.
[10]
Doe
H
y
u
n
Y
oon, M
a
ttan
Erez.
Virtual
i
z
ed a
n
d
F
l
exi
b
le E
CC for
Main
Me
mor
y
.
Procee
din
g
ASPLOS’10 Pr
oceedings of the 15t
h E
d
ition of ASPLOS on Architec
tur
e
Support for Programming
Lan
gu
ages a
n
d
oper
atin
g S
y
stems. 2010; 9
7
-40
8
.
[11]
K RajaS
e
kh
ar, BKV Prasad, T Madnu, P Sati
sh Ku
mar. Impl
ementati
on of
Fault Secur
e
Encod
e
r a
n
d
Deco
der for Memor
y
A
p
p
licat
ion.
Jour
nal
of T
r
ends in N
e
tw
ork and C
o
mmunic
a
tions.
1
9
7
(
1): 33-43.
[12]
CL Chen, MY
Hsiao.
Error-co
rrecting c
o
des
for Seniconduc
tor Memo
r
y
A
p
plicati
on:A Stat
e-of-the-ar
t
Revie
w
. IBM
Journ
a
l of Res
e
arch an
d Dev
e
l
o
p
m
e
n
t
. 1984;
28(2): 12
4–
134
.
[13]
RW Hamming. Errror Correct
ing and Err
o
r De
tecing Codes.
Bell Syste
m
T
e
chnic
a
l Jo
u
r
nal.
1
950
;
29(1): 14
7–
160
.
[14]
MY Hsiao. A Class of Optimal Min
i
mum
O
dd-
w
e
ig
ht-c
olum
n SEC-D
ED codes. IBM Journal of
Reser
a
ch an
d
Devel
opm
ent. 197
0; 14(3): 39
5–3
01.
[15]
C Sla
y
ma
n. C
a
che
an
d me
mor
y
error d
e
tection,
corr
ecti
on, an
d re
duct
i
on tec
hni
qu
es
for terrestrial
servers an
d
w
o
rkstations.
IEEE Transactions
on Devic
e
and Materials Reliability.
200
5; 5: 397–
40
4.
[16]
D W
ang, B G
anes
h, N T
uaych
aro
en, K B
a
ynes, A Ja
le
el, B Jaco
b. D
R
AMsim: A memor
y
-s
ystem
simulat
o
r.
SIGARCH Co
mput
er Architecture
New
s
(CAN).
2005; 33: 1
00–
1
07.
[17]
Xi
nq
uan Ji
ao, Peiji
ao Ma, Yu
gua
ng Z
h
a
n
g
. ECC alg
o
rith
m and the rea
l
i
z
ation of the V
HDL for hig
h
-
capac
ity sol
i
d-
state storag
e.
T
he Electro
n
ics a
n
d
Optoel
ectronics
(IOEOE) 2011
Internati
o
n
a
l
Confer
ence. 2
011; 23
9-2
42.
[18]
A
y
me
n F
,
Bel
gacem
H, Ch
i
r
az K.
A new
efficient s
e
lf-
c
hecki
ng Hs
ia
o SEC-DE
D
me
mory Error
Correctin
g Co
d
e
.
T
he Microel
ectronics(ICM).
Internation
a
l C
onfere
n
ce. 20
1
1
; 1-5.
Evaluation Warning : The document was created with Spire.PDF for Python.