TELKOM
NIKA Indonesia
n
Journal of
Electrical En
gineering
Vol. 12, No. 9, September
2014, pp. 66
6
7
~ 667
2
DOI: 10.115
9
1
/telkomni
ka.
v
12i9.472
7
6667
Re
cei
v
ed
No
vem
ber 7, 20
13; Re
vised
May 15, 20
14
; Accepte
d
Ju
ne 10, 201
4
Design of a Current Starved Ring Oscillator Based VCO
for Phase-Locked Loop
Khairun
Nis
a
’ Minhad, Zainab Ka
zem
i, Mamun Bin IbneRe
az,
Juba
y
e
r Jalil*,
Noorfaz
ila Kamal
Dep
a
rtment of Electrical, El
ec
tronic an
d S
y
st
em
s Engi
ne
eri
ng, Univ
ersiti K
eba
ngs
aan Ma
la
ysia,
436
00 UKM Ba
ngi, Sel
a
n
gor, Mala
ysi
a
*Corres
p
o
ndi
n
g
author, em
ail
:
juba
yer.j
a
li
l@
gmail.c
o
m
A
b
st
ra
ct
A desi
gn of th
e pro
pose
d
V
C
O w
a
s devel
ope
d for
PL
L i
n
radi
o freq
ue
ncy id
entificati
on (RF
I
D
)
app
licati
on. By
usi
ng c
u
rre
nt
star
ved r
i
ng
os
cillator, t
he
des
ign
ed c
i
rcuit
is
simulat
ed
usin
g 0.1
8
-
μ
m CM
O
S
process i
n
Men
t
or Graphics e
n
viro
nment. T
he results show
that the voltag
e draw
n
is aro
und 5V s
upp
lie
d
a
t
VDD, an
d the
prod
uct of this
current a
nd v
o
l
t
age h
a
s a
ppr
o
x
imate 1
05.3
m
W
pow
er cons
umptio
n w
h
il
e th
e
VCO gener
ate
s
212MH
z
at 1.
4V.
Keywo
r
d
s: low
pow
er, current starved VC
O
Copy
right
©
2014 In
stitu
t
e o
f
Ad
van
ced
En
g
i
n
eerin
g and
Scien
ce. All
rig
h
t
s reser
ve
d
.
1. Introduc
tion
In modern
world, modules are being
utiliz
ed i
n
sm
art
home
syst
ems, advanced image
pro
c
e
ssi
ng
impleme
n
tatio
n
s, a
n
d
nu
mero
us net
works [1
-8]. Du
e to
a
d
vent, of
CMOS
techn
o
logy, semico
ndu
cto
r
device
s
perv
ade in
ev
ery discipline
of engin
eeri
ng, and
to activa
te
these
devi
c
e
s
, o
scill
ators
become
co
re
co
mpon
ent
s [9-15]. A vol
t
age
controlle
d o
scill
ator i
s
a
module in which the o
sci
llation frequ
e
n
cy is
co
ntro
lled by voltage input. Voltage cont
roll
ed
oscillator
(VCO) form
s a key element in the des
ign of high frequency component using phased
locked lo
op
s (PLLs). In very larg
e scale inte
g
r
atio
n (VLSI) technolo
g
y, VCOs devel
ope
d in
CMOS
pro
c
e
s
s are utili
ze
d in a
nu
mbe
r
of a
ppli
c
atio
ns
as the
sou
r
ce
s
of si
gnal
gen
eratio
n a
n
d
as d
a
ta o
r
clo
ck
re
cove
ry system
s a
s
well a
s
RF
ID appli
c
atio
ns [16
-
21]. I
n
this pl
ace, we
recomme
nd
that a
wid
e
tu
ning
ran
g
e
is co
mprehe
nd
ed by
digital
and i
n
cessa
n
t
(an
a
log
)
tun
i
ng
circuits to red
u
ce the V
C
O
gain. The di
gital tuning schem
e dist
rib
u
tes a wi
deb
and tunin
g
ra
nge
into slight
er b
and
s. The
co
ntinuou
s tuni
ng cont
rol i
s
a mechani
sm
techni
que fo
r the PLL. A PLL
adju
s
tment circuit is u
s
e
d
to apporti
on the accu
rate su
b ba
nd for an a
s
sumed
cha
nnel
freque
ncy
so
that the PLL can lo
ck withi
n
t
uning volta
ge ra
nge. PL
L adju
s
tment
techni
que
s are
defined a
nd a
new auto
-
cal
i
bration
circui
t is offered.
Voltage co
ntrolled o
scill
ato
r
s pl
ay an important
role in
modern digit
a
l system
s, p
r
oviding
sign
als
req
u
ired for timin
g
in digital
circuits
and fre
quen
cy tran
sl
ation in radio
freque
ncy
RF
Circuits.
Thei
r o
u
tput fre
q
uen
cy is a f
unctio
n
of
a
control in
put
usually a
voltage. An
id
eal
voltage-cont
rolled voltag
e
oscillator i
s
a
circuit
wh
o
s
e
output fre
q
u
ency i
s
a lin
e
a
r fun
c
tion
of its
control voltag
e. Most
appli
c
ation
re
quired that o
s
cill
ator b
e
tuna
b
l
e, i.e. their o
u
tput freq
uen
cy
be a fun
c
tion
of a control
input, u
s
uall
y
a volt
age.
There a
r
e two differe
nt types
of voltag
e
controlled o
s
cillators u
s
ed
in PLL, Curre
n
t
starved VCO and Sou
r
ce cou
p
led VCO [22-2
4
].
In recent years LC tank os
cillators have shown good phase-
noi
se performance with
low
power
con
s
u
m
ption. However, there a
r
e so
me di
sa
d
v
antage
s. First, the tunin
g
ran
ge of a
n
LC-
oscillator app
roximately a
r
ound
10%-2
0%, and thi
s
is relatively low
whe
n
compa
r
ed to
ring
oscillators which a
c
comm
odate
s
>5
0%. So the
output freque
ncy may fall o
u
t of the desired
rang
e in the presen
ce of process variation.
Secon
d
, the phase
-
noi
se pe
rformance of the
oscillators
hi
ghly depends on the
quality factor of
on-chi
p
spiral inductors.
For m
o
st
digital
CMOS p
r
o
c
e
s
ses, it is
di
fficult to obtain a q
ua
lity factor
of the indu
ctor l
a
rge
r
than th
ree.
Therefore,
so
me extra
pro
c
e
ssi
ng
step
s may
be
re
q
u
ired. A
nd fin
a
lly, on-chip
spiral in
du
cto
r
s
occupy a lot of chip are
a
, typically larg
e whic
h is un
desi
r
abl
e for co
st and yield con
s
ide
r
ati
on
[25].
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 23
02-4
046
TELKOM
NI
KA
Vol. 12, No. 9, September 20
14: 66
67 – 667
2
6668
The VCO gai
n sugg
estivel
y
varies over the wide tuni
ng ran
ge, this, in turn, damage
s the
PLL pe
rform
ance. One
el
ucid
ation i
s
t
o
split th
e
tu
ning
ran
ge in
to a di
screte
smalle
r b
and
it is
use
d
as a lo
cal oscillator
(LO) to up
-co
n
vert
and d
o
w
n-co
nvert th
e incomi
ng RF sign
als. It is the
purp
o
seful bl
ock in mod
e
rn RF commu
nicatio
n
sy
ste
m
s. Cu
rrent market ha
s a
d
vanced in such
way that everything is available in co
mp
act and a
ffordable p
r
ices.
In orde
r to re
alize this, fully
integrate
d
circuits are ma
n
datory. Th
us
a lot of
re
sea
r
ch
ha
s
bee
n
don
e in th
e f
i
eld of
wirele
ss
comm
uni
cati
ons. Desi
gni
ng a freq
ue
ncy synthe
si
zer
com
m
issioning a V
C
O is a maj
o
r
experim
ent.
A PLL i
s
fun
d
a
mentally a
feedb
ack l
oop
that
lo
cks th
e on
-chip
clo
c
k ph
ase to t
hat of a
n
input clo
ck o
r
signal. Pha
s
e locked loo
p
is closed lo
o
p
control syst
em that asso
ciate
s
the output
pha
se with
the input ph
ase. Hi
gh-pe
rforma
nc
e di
gital system
s use clo
c
ks to sequ
en
ce
operation
s
an
d synchro
n
ize betwe
en pu
rpo
s
eful unit
s
and betwe
en
ICs. Clo
ck freque
nci
e
s an
d
data rates h
a
ve bee
n
swelling
with e
a
c
h
gene
ratio
n
of p
r
o
c
e
ssi
ng te
chnol
og
y and p
r
o
c
e
s
sor
architectu
re.
Within th
e di
gital sy
stems,
well
-t
imed
cl
ocks are g
e
n
e
rate
d
by p
h
a
se
-lo
c
ked l
o
ops
(PLL
s). Th
e
prom
pt up
surge
of the
system’
s
cl
ock fre
quen
cy po
ssesse
s challe
nge
s in
gene
rating a
n
d
distrib
u
ting
the clo
ck
with
low un
certai
nty.
2.
Metho
dolog
y
and Desig
n
Conside
r
ation
It is actually signifi
cant to
sele
ct the
accurate te
ch
nology library
and pro
c
e
ss before
desi
gning
a
circuit [22]. T
he technol
og
y expresse
s
the model
pa
ramete
rs a
s
sociate
d
with t
he
device
s
th
at
are
used i
n
t
he
schemati
c
and
it al
so provide
s
th
e grou
nd rul
e
s for
laying
out
a
circuit. In the anticip
ated
desig
n Men
t
or Gra
phi
cs Desi
gn Architect IC (DA-IC) Te
ch
n
o
logy
CMOS proce
ss
wa
s use
d
. The
cu
rre
nt-sta
rved VCO is
sho
w
n in Figure 1. The VCO
is
comp
osed of 7 ca
scade
d inverters. The
inve
rter sch
e
m
atic is given
in Figure 2.
Figure 1. Current-sta
rved VCO
Figure 2. Inverter Schemati
c
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
2302-4
046
De
sign of a Current Starve
d Ring O
s
cill
ator Based VCO for… (Kh
a
irun
Nisa
’
Minhad
)
6669
2.1. Design
Step
s
De
sign
step
s as follo
w:
1)
The inverte
r
size
s M2 and
M3, of Figure
1, are cal
c
ul
ated.
2)
The ca
pa
cita
nce i
s
cal
c
ul
a
t
ed as:
5/2
WPLP
WNLN
(1)
3)
The num
ber
of stages of
the oscillator is sel
e
cted
The circuit of
current starv
ed
V
C
O
i
s
same as
the ri
ng
oscillator.
Middle
P
MO
S
M1 a
nd
N
MO
S
M2 play role a
s
inverter
while
u
pper P
MO
S
M13 and l
o
wer N
MO
S
M14 operate
as
cu
rrent
sou
r
ces. T
h
e
curre
n
t sou
r
ce
s limit the
curre
n
t available to the i
n
verter. In ot
her
words, t
h
e
inverter i
s
st
arved fo
r
current. Th
e current in th
e first N
MO
S
and
PMOS are m
i
rro
red
in e
a
c
h
inverter/
c
urre
nt sou
r
ce sta
ge. P
MO
S
M11 and N
MO
S
M11 drain currents a
r
e the
same
and a
r
e set
by the input control voltag
e The VCO o
u
tput wave
forms are in sh
own Fig
u
re 1
.
It is noted that
the input Voltage = 2.5V, so the circuit transfe
rs
fro
m
the unde
sired
balance poin
t
to
the desire
d
balan
ce poi
nt Q. On the basi
s
of the start circ
uit, this wo
rk d
e
si
g
ned an en
abl
e-control circuit,
throug
h an e
nable te
rmin
al EN to co
n
t
rol the ci
rcui
t work or
not
. This de
sig
n
wa
s ba
sed
on
TSMC 0.5
-
µ
m
pro
c
e
s
s, a
nd u
s
ing T
T
(typical typi
cal
)
pr
oc
es
s
cor
ner
s f
o
r
cir
c
u
i
t
simulat
i
on.
B
y
looki
ng to th
e
model
library
file, we
can
get the
foll
owing p
a
ra
mete
rs
(TT
process
corne
r
mo
d
e
l)
that may be used for m
anu
al cal
c
ulation
in Table 1.
Table 1. De
si
gn Param
e
ters
De
v
i
ce
ty
p
e
Maximu
m
chan
nel(le
ng
th
)
Minimum
chan
nel(le
ng
th
)
Model
Gate
thick
n
ess
Thres
hold
v
o
l
t
ag
e
N MOS
0.5E-10
0.2E-6
49
0.2-0.5
0.5-1.8
P MO
S
0.55E-10
0.2E-6
49
0.2-0.5
0.5-1.8
Acco
rdi
ng to
the
simulati
on mo
del, M
1
’s th
re
shol
d
is
about
0.5
V,to ensure
the M1
workin
g in
sa
turated
zone,
nee
d a
bout
200
mV, over
drive voltag
e. So the
volta
ge b
e
twe
en
M1’s
gate and
sou
r
ce is a
bout 1
V
. When calculate the wid
e
long ratio of
M1, accordi
n
g to Figure 2,
I
K
V
V
,
5
We sele
ct gate’s len
g
th L=0.2 um, so W = 10 um. Th
e next sele
ction:
,
CEDE
C 0.1
8
μ
m process
h
a
s
bee
n u
s
e
d
to de
sig
n
a
n
d
sim
u
late th
e ci
rcuit dia
g
ram an
d
the layout of
the co
mpon
ents. Fin
a
lly, all
com
pon
ents h
a
ve b
een a
s
sembl
ed togeth
e
r
and
tested
at phy
sical d
e
scri
ption level
ba
se
d on
availabl
e CM
OS te
ch
nology. P
MO
S
and
N
MO
S
s
i
zes
descri
bed a
s
in Table 2.
Table 2. Devi
ce Size
s
De
v
i
ce
num
ber
De
v
i
ce
ty
p
e
Chan
nel
w
i
dth
Chan
nel
lengt
h
De
v
i
ce
num
ber
De
v
i
ce
ty
p
e
Chane
l
w
i
dth
Chan
nel
lengt
h
M1 N
MO
S
10
0.5
M12
P
MO
S
10
0.5
M2 N
MO
S
10
0.5
M13
P
MO
S
10
0.5
M3 N
MO
S
10
0.5
M14
P
MO
S
10
0.5
M4 N
MO
S
10
0.5
M15
P
MO
S
10
0.5
M5 N
MO
S
10
0.5
M16
P
MO
S
10
0.5
M6 N
MO
S
8
0.2
M17
P
MO
S
8
0.2
M7 N
MO
S
8
0.2
M18
P
MO
S
8
0.2
M8 N
MO
S
8
0.2
M19
P
MO
S
8
0.2
M9 N
MO
S
8
0.2
M20
P
MO
S
8
0.2
M10 N
MO
S
8
0.2
M21
P
MO
S
8
0.2
M11 N
MO
S
8
0.2
M22
P
MO
S
8
0.2
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 23
02-4
046
TELKOM
NI
KA
Vol. 12, No. 9, September 20
14: 66
67 – 667
2
6670
3. Resul
t
s
and
Discus
s
ion
Acco
rdi
ng
to
the pre
-
sim
u
lation wavef
o
rm of
curre
n
t so
urce
de
sign
ed
by thi
s
p
ape
r,
whe
n
the po
wer
sup
p
ly voltage chan
g
e
from 1 to
6
.
5V and the power voltag
e bigge
r than
3 V,
whe
n
po
we
r
sup
p
ly voltag
e fluctuate
s
f
r
om 4V
to
5.
5V and th
e fl
uctuatio
n ran
ge was 15.7
9
%,
the pre-simul
a
tion temp
erature
co
effici
ent of
curre
n
t
sou
r
ce i
s
5
03 p
p
m; the
enabl
e pin
can
effectively co
ntrol the
circu
i
t open o
r
cl
o
s
ed. After
ext
r
act the
pa
ra
sitic p
a
ra
met
e
rs
of layout take
layout sim
u
l
a
tion, and
d
o
a d
e
tailed
com
pari
s
o
n
betwe
en p
r
e-si
mulatio
n
data an
d lay
o
u
t
simulatio
n
da
ta, the re
sult
s
sho
w
ed
tha
t
besid
es the
temperature
coeffi
cient
chang
e a l
o
t, the
three othe
r i
ndicators of layout simula
tion ar
e ba
si
cally sam
e
with pre
-
sim
u
lation data,
the
para
s
itic pa
ra
meters of lay
out influen
ce
the functio
n
o
f
circuit is sm
all. The
circui
t diagram of t
he
V
co
by using 11 P
MO
S
and N
MO
S
that
parall
e
l connected. A cu
rrent starved ring oscillator for
pha
se-l
ocke
d
loop (PLL
) whi
c
h
h
a
s 1
1
P
MO
S
and 11 N
MO
S
has su
ccessfully
develop
ed
and
verified with
DRC an
d LVS clean.
Figure 3. VCO Schem
atic
Figure 4. Current Starved
VCO Outp
ut Wavefo
rm
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
2302-4
046
De
sign of a Current Starve
d Ring O
s
cill
ator Based VCO for… (Kh
a
irun
Nisa
’
Minhad
)
6671
Table 3. Co
ntrol Voltage vs. Fr
eque
ncy o
f
Current Starved VCO
Con
t
rol v
o
lta
g
e
Frequ
e
nc
y
(
MHz
)
0.5 129.3
0.6 147.05
0.7 161.29
0.8 178.57
0.9 188.67
1 192.30
1.1 203.99
1.2 208.62
1.3 212.24
1.4 212.77
Figure 5. Current Starved
VCO Layout
De
sign
4. Conclu
sion
A simple V
C
O circuit
r
y has be
en d
e
signed u
s
in
g
the 0.18-µm
CMOS tech
nology.
Acco
rdi
ng to
the pre
-
si
mul
a
tion wavefo
rm of current
sou
r
ce de
sig
ned by this p
a
per,
whe
n
the
power
su
pply
voltage
ch
a
nge f
r
om
1.8
to 6.5V
and
the p
o
wer voltage
bigg
er than
3 V
when
power
sup
p
ly voltage fluct
uates from 4
V
to 5.5V
and
the fluctuatio
n ran
ge is
15.
79%, the ena
b
le
pin ca
n effectively control
the circuit op
en or
cl
o
s
ed.
After extract
the
para
s
itic param
eters
of
layout take l
a
yout simul
a
tion, and d
o
a deta
iled
co
mpari
s
o
n
bet
w
ee
n pre-sim
u
lation data
and
layout simulat
i
on data, the results sho
w
e
d
that bes
ide
s
the tempera
t
ure co
efficie
n
t chang
e
a lot,
the thre
e oth
e
r in
dicators
of layout si
m
u
lation a
r
e
b
a
si
cally same
with p
r
e
-
si
m
u
lation d
a
ta,
the
para
s
itic p
a
rameters of layout influence the functi
o
n
of circuit little, and the layout this pa
per
desi
gne
d is p
e
rfect. T
h
is p
aper ad
opts the
stand
ar
d
CMOS te
ch
n
o
logy, therefo
r
e, the
de
sign
of
curre
n
t source unit
can
be
used a
s
a
module
ap
pe
ared
in
a
co
mplete
chip
desi
gn to
pro
v
ide
static d
c
bia
s
for othe
r ci
rcu
i
t module, an
d make
them
work in th
e a
ppro
p
ri
ate dc
operating p
o
i
n
t
to ensu
r
e the
whol
e chi
p
ca
n work no
rma
lly.
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