Indonesian
J
our
nal
of
Electrical
Engineering
and
Computer
Science
V
ol.
25,
No.
1,
January
2022,
pp.
105
∼
112
ISSN:
2502-4752,
DOI:
10.11591/ijeecs.v25.i1.pp105-112
❒
105
Lightweight
hard
war
e
nger
printing
solution
using
inher
ent
memory
in
off-the-shelf
commodity
de
vices
Mohd
Syaq
Mispan
1,4,5
,
Aiman
Zakwan
Jidin
1,4,5
,
Muhammad
Raihaan
Kamaruddin
2,4,5
,
Haslinah
Mohd
Nasir
3,4,5
1
Micro
and
Nano
Electronics
(MiNE),
Melaka,
Malaysia
2
Machine
Learning
and
Signal
Processing
(MLSP),
Melaka,
Malaysia
3
Adv
ance
Sensors
and
Embedded
Controls
System
(ASECs),
Melaka,
Malaysia
4
Centre
for
T
elecommunication
Research
and
Inno
v
ation
(CeTRI),
Melaka,
Malaysia
5
F
akulti
T
eknologi
K
ejuruteraan
Elektrik
dan
Elektronik,
Uni
v
ersiti
T
eknikal
Malaysia
Melaka,
Melaka,
Malaysia
Article
Inf
o
Article
history:
Recei
v
ed
Mar
9,
2021
Re
vised
Oct
22,
2021
Accepted
No
v
16,
2021
K
eyw
ords:
A
TMe
g
a2560
Hardw
are
security
Ph
ysical
unclonable
function
SRAM-PUF
ABSTRA
CT
An
emer
ging
technology
kno
wn
as
Ph
ysical
unclonable
function
(PUF)
can
pro
vide
a
hardw
are
root-of-trust
in
b
uilding
the
trusted
computing
system.
PUF
e
xploits
the
intrinsic
process
v
ariations
during
the
inte
grated
circuit
(IC)
f
abrication
to
generate
a
unique
response.
This
unique
response
dif
fers
from
one
PUF
to
the
other
similar
type
of
PUFs.
Static
random-access
memory
PUF
(SRAM-PUF
)
is
one
of
the
memory-
based
PU
Fs
in
which
the
response
is
generated
during
the
memory
po
wer
-up
process.
Non-v
olatile
memory
(NVM)
architecture
lik
e
SRAM
is
a
v
ailable
in
of
f-the-shelf
mi-
crocontroller
de
vices.
Exploiting
the
inherent
SRAM
as
PUF
could
wide-spread
the
adoption
of
PUF
.
Therefore,
in
this
study
,
we
e
v
aluate
the
suitability
of
inherent
SRAM
a
v
ailable
in
A
TMe
g
a2560
microcontroller
on
Arduino
platform
as
PUF
that
can
pro-
vide
a
unique
ngerprint.
First,
we
analyze
the
start-up
v
alues
(SUVs)
of
memory
cells
and
select
only
the
cells
that
sho
w
random
v
alues
after
the
po
wer
-up
process.
Subsequently
,
we
statistically
analyze
the
characteristic
of
fteen
SRAM-PUFs
which
include
uniqueness,
reliability
,
and
uniformi
ty
.
Based
on
our
ndings,
the
SUVs
of
fteen
on-chip
SRAMs
achie
v
e
42.64%
uniqueness,
97.28%
reliability
,
and
69.16%
uniformity
.
Therefore,
we
concluded
that
the
a
v
ailable
SRAM
in
of
f-the-shelf
com-
modity
hardw
are
has
good
quality
to
be
used
as
PUF
.
This
is
an
open
access
article
under
the
CC
BY
-SA
license
.
Corresponding
A
uthor:
Mohd
Syaq
Mispan
F
akulti
T
eknologi
K
ejuruteraan
Elektrik
dan
Elektronik,
Uni
v
ersiti
T
eknikal
Malaysia
Melaka
T
aman
T
asik
Utama,
75450
A
yer
K
eroh,
Melaka,
Malaysia
Email:
syaq.mispan@utem.edu.my
1.
INTR
ODUCTION
Ph
ysical
unclonable
function
(PUF)
is
a
promising
technology
as
a
hardw
are
ngerprinting
s
olution
for
a
trusted
computing
system
by
pro
viding
a
root-of-trust.
PUF
e
xploits
the
intrinsic
manuf
acturing
process
v
ariations
during
inte
grated
circuit
(IC)
f
abrication.
The
intrinsic
process
v
ariations
embodied
in
the
silicon
chip
acts
as
a
random
function
for
a
PUF
which
can
uniquely
map
a
set
of
challenges
to
a
set
of
responses,
kno
wn
as
challenge-response
pairs
(CRPs).
These
CRPs
are
random
and
sho
w
a
de
vice-specic
property
that
can
be
applied
in
IC
identication
and
authentication,
and
cryptographic
k
e
y
generation
application
[1].
Se
v
eral
PUFs
ha
v
e
been
proposed
in
the
past
[2],
[3].
Static
random-access
memory
PUF
(SRAM-
PUF)
is
one
of
the
pre
viously
proposed
PUFs
and
it
is
cate
gorized
as
memory-based
PUF
[4],
[5].
Further
,
J
ournal
homepage:
http://ijeecs.iaescor
e
.com
Evaluation Warning : The document was created with Spire.PDF for Python.
106
❒
ISSN:
2502-4752
SRAM-PUF
has
been
sub-cate
gorized
as
W
eak-PUF
due
to
limitations
in
its
CRPs.
The
terminology
of
‘Strong’
and
‘W
eak’
PUF
is
not
meant
to
indicate
that
one
PUF
is
superior
to
the
other
PUFs,
rather
it
is
to
indicate
the
corresponding
CRPs
number
of
one
PUF
able
to
generate
[4],
[6],
[7].
T
ypical
SRAM
cells
con-
sist
of
a
cr
oss-coupled
in
v
erter
and
tw
o
access
transistors.
The
cross-coupled
in
v
erter
is
v
ery
susceptible
to
the
process
v
ariations,
hence
lead
to
the
threshold
v
oltage,
V
th
mismatches
between
n-channel
metal-oxide
semi-
conductor
(nMOS)
and
p-channel
metal-oxide
semiconductor
(pMOS)
transistors.
Due
to
the
V
th
mismatch,
a
racing
condi
tion
to
char
ge
the
l
oading
capacitances
of
cross-coupled
in
v
erter
occurs
during
the
po
wer
-up
pro-
cess
[8].
An
in
v
erter
that
has
a
strong
pMOS
(i.e.,
lo
w
V
th
)
dri
v
es
more
current
and
turns
the
nMOS
of
another
in
v
erter
to
ON
state.
Ev
entually
,
the
load
capacitance
corresponding
to
the
strong
pMOS
being
pulled-up
to
V
dd
and
another
load
capacitance
being
pulled-do
wn
to
0
V
.
The
phenomenon
mentioned
abo
v
e
causes
each
SRAM
cell
to
settles
at
a
random
start-up
v
alue
(SUV)
either
‘1’
or
‘0’
during
the
po
wer
-up
process.
The
SUVs
across
dif
ferent
memory
blocks
within
an
SRAM
and
across
multiple
SRAMs
sho
w
de
vice-specic
and
random
patterns.
Hence,
it
is
suitable
to
be
used
as
PUF
as
proposed
earlier
in
[4],
[5].
Ne
v
erthel
ess,
the
question
remains
is
the
suitability
of
on-chip
or
inherent
SRAM
in
an
y
computing
de
vice
to
be
used
as
a
PUF
.
Exploiting
the
on-chip
SRAM
as
PUF
can
further
reduce
the
total
cost
of
b
uilding
the
hardw
are
root-of-trust
feature
and
could
wide-spread
the
adoption
of
PUF
in
a
computing
system
[9].
Moti
v
ated
by
the
cost
reduction
and
potential
wide-spread
adoption
of
PUF
in
computing
systems,
the
focus
of
this
paper
is
to
analyze
and
e
v
aluate
the
suitability
of
on-chip
SRAM
as
PUF
.
W
e
used
the
A
T
-
Me
g
a2560
microcontroller
on
the
Arduino
platform
as
a
case
study
to
e
v
aluate
the
performance
of
SRAM-PUF
.
The
main
contrib
utions
of
this
w
ork
are
highlighted
belo
w:
i
W
e
study
the
SUVs
of
on-chip
8kB
SRAM
in
A
TMe
g
a2560
microcontroller
de
vice.
W
e
sho
w
that
the
SUVs
in
the
memory
address
range
of
0x0281
to
0x20D0
are
random
and
suitable
to
be
used
as
PUF
.
ii
W
e
e
v
aluate
the
quality
of
PUF
which
includes
uniqueness,
reliability
,
and
uniformity
on
fteen
on-chip
8kB
SRAMs
by
randomly
selecting
4096
bits
from
the
aforementioned
memory
address
range
for
each
SRAM.
The
on-chip
SRAM
sho
ws
good
quality
and
suf
cient
entrop
y
of
PUF
which
achie
v
e
42.64%,
97.28%,
and
69.16%,
respecti
v
ely
for
uniqueness,
reliability
,
and
uniformity
.
The
rest
of
the
paper
is
or
g
anized
as
follo
ws.
Section
2
describes
the
background
which
related
to
this
w
ork.
Section
3
describes
the
methods
used
in
this
study
.
The
e
xperimental
analysis
and
results
are
presented
in
section
4.
Finally
,
conclusions
are
dra
wn
in
section
5.
2.
RELA
TED
W
ORK
A
dual
function
of
SRAM
as
memory
and
PUF
has
been
suggested
in
the
pre
vious
studies
[10]–
[12].
Hof
fmann
et
al.
,
[11],
[12]
were
focused
on
reusing
the
on-chip
cache
a
s
PUF
,
while
Mispan
et
al.
,
[10]
proposed
the
ageing
mitig
ation
te
chnique
(i.e.,
to
impro
v
e
the
reliability
of
SUVs)
e
xperiences
by
the
SRAM
cells
when
it
is
being
used
as
memory
and
PUF
.
Other
studies
ha
v
e
been
focusing
on
using
on-chip
SRAM
as
PUF
in
ARM-based
lo
w-end
commodity
microcontroller
de
vices
[13],
[14].
These
st
udies
sho
w
that
the
inherent
SRAM
in
ARM-based
microcontroller
contains
suf
cient
entrop
y
to
be
e
xploited
as
PUF
.
In
other
studies,
Platono
v
et
al.
,
[15]
and
Aung
et
al.
,
[16]
in
v
estig
ate
the
entrop
y
of
SUVs
in
an
on-chip
memory
in
A
TMe
g
a1284P
and
A
TMe
g
a328P
microcontrollers,
respecti
v
ely
.
The
results
from
both
studies
sho
w
that
the
SUVs
ha
v
e
a
good
entrop
y
that
can
uniquely
distinguish
each
chip.
Else
where,
microcontrollers
in
Arduino
platforms
ha
v
e
been
used
for
a
proof-of-concept
of
internet-of-things
(IoT)
de
vice
authentication
[17]–[19].
Besides,
the
on-chip
SRAM
in
A
TMe
g
a328P
microcontroller
de
vices
ha
v
e
been
used
as
a
case
study
to
perform
in
v
asi
v
e
attacks
as
discussed
in
[20],
[21].
All
of
the
abo
v
e
studies
sho
w
that
the
feasibility
of
using
on-chip
SRAM
in
A
TMe
g
a256
microcontroller
on
Arduino
platform
as
PUF
has
ne
v
er
been
studied.
In
our
study
,
we
focus
on
e
v
aluating
the
PUF
entrop
y
of
on-chip
8
kB
SRAM
in
an
A
TMe
g
a256
microcontroll
er
de
vice
and
we
specify
which
memory
address
can
be
used
to
generate
a
unique
identier
.
3.
METHODOLOGY
The
a
v
ailable
on-chip
memory
of
8
kB
SRAM
in
A
TMe
g
a2560
microcontroller
on
the
Arduino
plat-
form
is
used
in
this
study
.
The
on-chip
SRAM
in
A
TMe
g
a2560
is
di
vided
into
4
allocations
of
memories
which
are
the
Re
gister
File,
the
I/O
memory
,
Extended
I/O
memory
,
and
the
internal
data
SRAM
[22].
Each
address
is
used
to
store
a
byte
(i.e.,
8-bit)
of
data.
The
rst
32
locations
address
the
re
gister
le,
the
ne
xt
64
locations
Indonesian
J
Elec
Eng
&
Comp
Sci,
V
ol.
25,
No.
1,
January
2022:
105–112
Evaluation Warning : The document was created with Spire.PDF for Python.
Indonesian
J
Elec
Eng
&
Comp
Sci
ISSN:
2502-4752
❒
107
the
standard
I/O
memory
,
then
416
locations
of
e
xtended
I/O
memory
,
and
the
ne
xt
8,192
locations
address
the
internal
data
SRAM.
All
memory
location
addresses
are
analyzed
in
searching
for
unique
and
random
pat-
terns
of
SUVs
during
the
po
wer
-up
process.
T
o
read
the
SUVs
of
SRAM-cells,
we
modied
the
start-up
code
(i.e.,
setup()
function)
to
display
the
ra
w
SUVs
via
uni
v
ersal
asynchronous
recei
v
er
-transmitter
(U
AR
T)
(i.e.,
Arduino
on-board
USB-to-Serial)
before
the
SRAM
gets
initialized.
The
start-up
code
is
essential
to
e
v
ery
microcontroller
as
it
initializes
v
ariables,
pin
modes,
and
libraries.
T
o
measure
the
reliability
of
SUVs
under
dif
ferent
po
wer
-up
c
ycles,
v
e
po
wer
-up
processes
ha
v
e
been
conducted
on
each
of
fteen
de
vices
with
a
time
interv
al
of
5
minutes
before
the
ne
xt
po
wer
-up
process
tak
es
place
to
eliminate
the
ef
fect
of
data
remanence
in
SRAM
cells
[23].
It
is
assumed
that
the
suppl
y
v
oltage
and
surrounding
temperat
u
r
e
remain
c
o
ns
tant
dur
-
ing
the
po
wer
-up
e
xperiment.
All
SUVs
e
xtracted
from
the
on-chip
SRAM
are
recorded
in
a
CSV
le
and
MA
TLAB
R2016b
is
us
ed
as
a
post-processing
softw
are
to
e
v
aluate
the
uniqueness,
reliability
,
and
uniformity
performances.
4.
SIMULA
TION
RESUL
TS
AND
AN
AL
YSIS
In
this
section,
the
rele
v
ant
simulation
and
analysis
are
discuss
ed
bas
ed
on
the
descri
bed
m
ethodology
in
section
3.
First,
the
randomness
of
the
SUVs
in
the
A
TMEGA2560’
s
SRAM
is
analyzed.
Subsequently
,
the
quality
of
SRAM-PUF
such
as
uniquenes
s,
reliability
,
and
uniformity
is
e
v
aluated
according
to
the
mathemati-
cal
formulation
described
in
[24],
[25].
4.1.
Analysis
of
the
A
TMEGA2560’
s
SRAM
W
e
e
v
aluated
the
SUVs
patterns
of
A
TMe
g
a2560
microcontroller
de
vice
on
Arduino
platform
that
inte
grates
an
on-chip
8
kB
(i.e.,
range
of
address:
0x0000
to
0x21FF)
of
SRAM.
The
randomness
of
SUVs
of
SRAM
cells
is
assessed
using
fteen
A
TMe
g
a2560
de
vices
by
e
xtracting
the
SUVs
in
each
memory
location.
Figure
1
illustrates
the
bitmap
of
SUVs
measurement
of
all
the
addresses
in
an
8
kB
on-chip
SRAM
in
the
A
TMe
g
a2560
microcontroller
.
The
bitmap
has
been
illustrated
such
that
each
ro
w
consists
of
16-byte
of
data
(i.e.,
128-bit).
As
can
be
seen
in
Figure
1,
the
bitmap
indicates
that
there
are
repeating
patterns
in
the
lo
w
address
(0x0000
to
0x027F)
and
high
address
(0x20D0
to
0x21FF)
re
gions
for
all
fteen
de
vices.
Figure
1.
Bitmap
of
SUVs
measurement
of
an
A
TMEGA2560
on-chip
8
kB
SRAM
Lightweight
har
dwar
e
ng
erprinting
solution
using
inher
ent
memory
...
(Mohd
Syaq
Mispan)
Evaluation Warning : The document was created with Spire.PDF for Python.
108
❒
ISSN:
2502-4752
As
mentioned
in
section
3
the
rst
512
locations
addressed
the
re
gister
le,
the
standard
I/O
memory
,
and
the
Extended
I/O
memory
.
Therefore,
we
assume
that
the
observ
ed
repeating
patterns
represent
structures
used
by
the
on-board
R
OM
code
embedded
with
e
v
ery
Arduino
board.
Another
observ
ation
of
repeating
patterns
is
at
the
high
address
re
gion
which
corresponding
to
the
address
of
internal
data
SRAM
that
could
be
caused
by
the
application
programming
interf
ace
(API).
The
most
important
observ
ation
is
the
SUVs
generated
by
the
SRAM
cells
within
the
address
re
gion
of
0x0280
to
0x20CF
which
sho
ws
randomness
and
uniqueness
characteristics.
Hence,
the
subsequent
analysis
of
PUF
quality
is
based
on
the
SUVs
e
xtracted
from
this
address
re
gion.
4.2.
Uniqueness
Uniqueness
measures
the
ability
of
a
PUF
to
generate
a
response
that
dif
fer
from
the
other
responses
generated
by
the
other
similar
types
of
PUFs
when
a
challenge
C
is
applied.
Ideally
,
the
uniqueness
should
be
distrib
uted
around
50%
with
a
v
ery
small
standard
de
viation.
Uniqueness
can
be
e
v
aluated
using
hamming
distance
(HD)
as
dened
in
(1):
In
ter
−
HD
=
2
m
(
m
−
1)
m
−
1
X
i
=1
m
X
j
=
i
+1
HD(
R
i
(
n
)
,
R
j
(
n
))
n
×
100%
(1)
where
i
and
j
represent
tw
o
PUF
instances
under
e
v
aluation
that
generates
n
-bit
of
response.
m
represents
the
total
number
of
similar
types
of
PUFs.
Based
on
the
ndings
of
random
SUVs
patterns
as
discussed
in
section
4.1,
only
4096-bit
is
se
lected
randomly
within
the
address
re
gion
of
0x0280
to
0x20CF
for
each
de
vice.
Figure
2
depicts
the
uniquenes
s
for
fteen
SRAM-PUF
inst
ances
with
a
4096-bit
of
response
is
e
xtracted
for
each
SRAM-PUF
.
The
uniqueness
of
0.4264
(42.64%)
with
a
standard
de
viation
of
0.0102
is
obtained.
The
uniqueness
and
its
standard
de
viation
are
closed
to
an
ideal
v
alue
of
50%
with
a
v
ery
small
standard
de
viation.
Inter-HD (Uniqueness)
0
0
.1
0.2
0
.3
0.4
0
.5
0.6
0
.7
0.8
0
.9
1
Hamming Distance (HD)
0
5
10
15
20
25
30
35
40
45
Frequency of Occurances
Figure
2.
Uniqueness
of
fteen
SRAM
PUF
instances
Indonesian
J
Elec
Eng
&
Comp
Sci,
V
ol.
25,
No.
1,
January
2022:
105–112
Evaluation Warning : The document was created with Spire.PDF for Python.
Indonesian
J
Elec
Eng
&
Comp
Sci
ISSN:
2502-4752
❒
109
4.3.
Reliability
Reliability
is
a
measure
of
reproducibility
of
the
PUF
response.
Ideally
,
a
100%
reliability
is
desired
for
PUF
circuits.
Ho
we
v
er
,
because
of
the
noise
e
xperienced
by
the
PUF
circuit,
it
is
not
possible
to
achie
v
e
100%
reliability
.
The
SUVs
for
reliability
e
v
a
luation
ha
v
e
been
e
xtracted
according
to
the
methodology
de-
scribed
in
section
3.
Subsequently
,
the
reliability
is
computed
using
(2),
dened
as:
Reliabilit
y
=
1
−
1
m
m
X
j
=1
HD(
R
i
(
n
)
,
R
′
i,j
(
n
))
n
×
100%
(2)
where
i
represents
PUF
under
e
v
aluation
which
generate
n
-bit
response,
R
i
(
n
)
at
reference
po
wer
-up,
R
′
i,j
(
n
)
is
the
response
at
dif
ferent
condition
(i.e.,
ne
xt
po
wer
-up
process
),
and
m
represents
the
total
number
of
po
wer
-
up
processes.
The
SUVs
which
w
as
generated
for
uniqueness
e
v
aluation
in
Section
4.2.
is
set
as
a
response
at
the
reference
po
wer
-up.
Figure
3
depicts
the
reliability
for
each
of
the
SRAM-PUFs
that
has
been
subjected
to
v
e
po
wer
-up
processes.
Based
on
the
reliability
e
v
aluation,
one
de
vice
sho
ws
reliability
of
93.29%,
lo
wer
as
compared
to
the
reliability
of
the
other
fourteen
de
vices.
Despite
an
outlier
,
it
can
be
observ
ed
that
the
SRAM-PUFs
achie
v
e
high
reliability
under
dif
ferent
po
wer
-up
processes,
on
a
v
erage
of
about
97.28%,
close
to
an
ideal
v
alue
of
100%.
0
2
4
6
8
10
12
14
16
90
92
94
96
98
100
#
SRAM-PUF
Reliability
(%)
Figure
3.
Reliability
of
fteen
SRAM-PUFs
subjected
to
v
e
po
wer
-up
processes
4.4.
Unif
ormity
Uniformity
measures
the
number
of
1’
s
and
0’
s
distrib
ution
in
a
binary
res
ponse
of
a
PUF
.
A
bal-
anced
distrib
ution
of
1’
s
and
0’
s
is
required
which
indicates
the
randomness
in
a
response.
Uniformity
can
be
e
v
aluated
using
hamming
weight
(HW)
as
dened
in
(3):
Uniformit
y
=
1
m
×
n
m
X
i
=1
n
X
j
=1
r
i,j
×
100%
(3)
where
r
i,j
is
the
j
-th
binary
bit
of
an
n
-bit
response
from
a
PUF
i
,
for
a
total
of
m
PUFs.
Figure
4
depicts
the
uniformity
distrib
ution
of
fteen
SRAM-PUFs
with
4096-bit
e
xtracted
from
each
PUF
.
The
SUVs
e
xtracted
from
fteen
SRAM-PUFs
achie
v
e
0.6916
(69.16%)
of
uniformity
with
a
standard
de
viation
of
0.0182.
The
SUVs
are
sk
e
wed
to
w
ards
one,
therefore
the
uniformity
v
alue
is
more
than
50%
as
can
be
seen
in
Figure
4
which
indicates
more
1’
s
than
0’
s
in
the
PUF
responses.
A
similar
observ
ation
of
a
strong
bias
to
w
ards
one
in
another
A
TMe
g
a
f
amily
is
described
in
[26].
Despite
this
observ
ation,
the
uniqueness
which
has
been
e
v
aluated
earlier
in
Section
4.2.
is
closed
to
an
ideal
v
alue
of
50%
(i.e.,
able
to
distinguish
a
PUF
from
a
group
Lightweight
har
dwar
e
ng
erprinting
solution
using
inher
ent
memory
...
(Mohd
Syaq
Mispan)
Evaluation Warning : The document was created with Spire.PDF for Python.
110
❒
ISSN:
2502-4752
of
similar
PUFs).
Hence,
on-chip
SRAM
in
the
A
TMe
g
a2560
microcontroller
still
holds
a
good
quality
to
be
a
PUF
.
Inter-HD (Uniqueness)
0
0
.1
0.2
0
.3
0.4
0
.5
0.6
0
.7
0.8
0
.9
1
Hamming Distance (HD)
0
5
10
15
20
25
30
35
40
45
Frequency of Occurances
Figure
4.
Uniformity
of
fteen
SRAM
PUF
instances
5.
CONCLUSION
SRAM-PUF
is
one
of
the
pre
viously
proposed
memory-based
PUFs.
SRAM
memory
is
a
v
ailable
in
an
y
computing
system,
hence
it
is
interesting
to
in
v
estig
ate
the
suitability
of
using
on-chip
memory
in
of
f-the-
shelf
commodity
de
vices.
In
this
study
,
the
on-chip
memory
of
8kB
SRAM
in
A
TMe
g
a2560
microcontroller
on
the
Arduino
platform
has
been
used
as
a
case
study
.
Our
ndings
sho
w
that
the
uniqueness
is
distrib
uted
close
to
an
ideal
v
alue
of
50%
with
a
small
standard
de
viation.
The
a
v
erage
reliabi
lity
of
fteen
SRAM-PUFs
under
v
e
dif
ferent
po
wer
-up
c
ycles
is
approxi
mately
about
97.28%.
The
uniformity
of
SUVs
e
xtracted
from
fteen
SRAM-PUFs
sho
ws
biasing
to
w
ards
one
whereby
the
uniformity
is
distrib
uted
around
69.16%.
Despite
the
sk
e
wed
uniformity
,
on-chip
SRAM
in
the
A
TMe
g
a2560
microcontroller
still
sho
wing
good
uniqueness
and
reliability
.
Hence,
it
can
be
concluded
that
the
on-chip
SRAM
in
the
A
TMe
g
a2560
microcontroller
on
the
Arduino
platform
is
suitable
to
be
used
as
a
hardw
are
root-of-trust
solution
kno
wn
as
PUF
.
A
CKNO
WLEDGEMENT
The
authors
w
ould
lik
e
to
t
hank
Uni
v
ersiti
T
eknikal
Malaysia
Melaka
and
the
Ministry
of
Higher
Education
Malaysia
for
the
nancial
funding
under
Grant
No.
FRGS/1/2020/TK0/UTEM/02/56
for
completing
this
project.
Indonesian
J
Elec
Eng
&
Comp
Sci,
V
ol.
25,
No.
1,
January
2022:
105–112
Evaluation Warning : The document was created with Spire.PDF for Python.
Indonesian
J
Elec
Eng
&
Comp
Sci
ISSN:
2502-4752
❒
111
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(Mohd
Syaq
Mispan)
Evaluation Warning : The document was created with Spire.PDF for Python.
112
❒
ISSN:
2502-4752
BIOGRAPHIES
OF
A
UTHORS
Mohd
Syaq
Mispan
recei
v
ed
B.Eng
Electrical
(Electronics)
and
M.Eng
Electrical
(Com-
puter
and
Microelectronic
System)
from
Uni
v
ersiti
T
eknologi
Malaysia,
Mala
ysia
in
2007
and
2010
respecti
v
ely
.
He
had
e
xperienced
w
orking
i
n
semiconductor
industries
from
2007
until
2014
before
pursuing
his
Ph.D.
de
gree.
He
obtained
his
Ph.D.
de
gree
in
Electronics
and
Electrical
Engineering
from
Uni
v
ersit
y
of
Southampton,
United
Kingdom
in
2018.
He
is
currently
a
senior
lecturer
in
F
akulti
T
eknologi
K
ejuruteraan
Elektrik
dan
Elektronik,
Uni
v
ersiti
T
eknikal
Malaysia
Melaka.
His
current
research
interests
include
hardw
are
security
,
CMOS
reliability
,
VLSI
design,
and
Electronic
Systems
Design.
He
can
be
contacted
at
email:
syaq.mispan@utem.edu.my
.
Aiman
Zakwan
Jidin
obtained
his
M.Eng
in
Electronic
and
Microelectronic
System
Engineering
from
ESIEE
Engineering
P
aris
France
in
2011.
He
has
2
years
of
w
orking
e
xperience
in
designing
digital
IC
and
digital
system
in
FPGA
at
Altera
Corporation
Malaysia,
before
joining
Uni
v
ersiti
T
eknikal
Malaysia
Melaka
as
lecturer
and
researcher
,
in
Electronics
and
Computer
Engi-
neering.
His
research
interests
include
FPGA
D
esign
and
Digital
System
Design.
He
can
be
contacted
at
email:
aimanzakw
an@utem.edu.my
.
Muhammad
Raihaan
Kamaruddin
recei
v
ed
the
B.Eng
(Electronics
and
Computer
Sys-
tems)
and
M.Eng
(Electronics
and
Information
Science)
de
grees
from
T
akushoku
Uni
v
ersity
,
Japan,
He
is
w
orking
to
w
ard
the
PhD
de
gree
in
Electronics
and
Computer
Engineering
with
the
Uni
v
ersiti
T
eknikal
Malaysia
Melaka
(UT
eM).
His
PhD
is
on
the
Implementation
of
bio-inspired
robotic
na
vig
a-
tion
system
using
stochastic
computing.
He
has
w
orking
e
xperience
as
lecturer
in
Uni
v
ersiti
T
eknikal
Malaysia
Melaka
(UT
eM)
for
10
years
(2010-present).
His
research
interest
includes
machine
learn-
ing,
robotic
and
stochastic
computing.
He
can
be
contacted
at
email:
raihaan@utem.edu.my
.
Haslinah
Mohd
Nasir
recei
v
ed
her
Bachelor
De
gree
in
Electrical
-
Electronic
Engineering
(2008)
from
Uni
v
ersit
i
T
eknologi
Malaysia
(UTM),
MSc
(2016)
and
PhD
(2019)
in
Electronic
Engi-
neering
from
Uni
v
ersiti
T
eknikal
Malaysia
Melaka
(UT
eM).
She
had
5
years
(2008-2013)
e
xperience
w
orking
in
industry
and
currently
a
lecturer
in
UT
eM.
Her
research
interest
includes
microelectronics,
articial
intelligence
and
biomedical.
She
can
be
contacted
at
email:
haslinah@utem.edu.my
.
Indonesian
J
Elec
Eng
&
Comp
Sci,
V
ol.
25,
No.
1,
January
2022:
105–112
Evaluation Warning : The document was created with Spire.PDF for Python.