TELKOM
NIKA Indonesia
n
Journal of
Electrical En
gineering
Vol.12, No.6, Jun
e
201
4, pp. 4603 ~ 4
6
0
8
DOI: 10.115
9
1
/telkomni
ka.
v
12i6.544
3
4603
Re
cei
v
ed
De
cem
ber 2
8
, 2013; Re
vi
sed
F
ebruary 27,
2014; Accept
ed March 1
4
, 2014
The Research and Desige of the CNC Constant Voltage
Power
Shi
w
ei Lin
Jilin Institute of
Chemic
al T
e
chno
log
y
, Jil
i
n, Chin
a
Che
ngd
e Str.45, Jilin Cit
y
email: 1
384
32
255
57@
12
6.co
m
A
b
st
r
a
ct
CNC c
onstant
voltag
e p
o
w
e
r i
s
compos
ed
by
the
a
nal
og
po
w
e
r circuit, MC
U contro
l circu
i
t, pulse
w
i
dth mo
du
lati
on circu
i
t, a p
o
w
e
r driver a
m
p
lifier, a
n
a
l
o
g
to di
gital c
o
nversi
on circ
ui
t, the input vo
l
t
age
setting circ
uit a
nd the
outp
u
t voltag
e dis
p
lay
circuit. T
he po
w
e
r possesses
the functio
n
s
of digit
a
l re
gul
a
t
or,
hig
h
precis
ion
output, short-ci
rcuit & over-cu
rrent pr
otectio
n
and a
l
ar
m fu
nctions, esp
e
ci
ally for a hig
h
er
accuracy requirements for var
i
ous occ
a
sions
.
Ke
y
w
ords
:
C
NC pow
er, C8
051F
4
10, T
L49
4, constant volt
age
Copy
right
©
2014 In
stitu
t
e o
f
Ad
van
ced
En
g
i
n
eerin
g and
Scien
ce. All
rig
h
t
s reser
ve
d
.
1. Introduc
tion
The
role
of t
he
con
s
tant
voltage p
o
we
r i
s
o
u
tput co
nstant voltag
e, which i
s
one of the
device
s
com
m
only used i
n
ele
c
troni
c t
e
ch
nolo
g
y an
d widely u
s
e
d
. Traditio
nal
DC p
o
wer
supply
feature
s
a si
mple, difficult to control, low
efficie
n
cy
, low accura
cy, bulky, bu
t all have th
e
followin
g
pro
b
lems: T
he o
u
tput voltage
is
set by
co
urse (ban
d switch
) a
nd fin
e
(p
otentiom
e
ter)
to adju
s
t. The difficulty is very greate
r
whe
n
t
he o
u
tput voltage
requi
re
s a
c
curate o
u
tput
or
requi
re
cha
n
ges
within a
small ra
nge
of (1.02~
1.03V). In add
ition, with the use of ti
me
increa
se
s, th
e ba
nd
switches an
d p
o
te
ntiometers
i
n
evitably bad,
have a
n
im
pa
ct on
the
out
put,
often carried
out by the
ha
rdware limit f
o
r ove
r
lo
ad p
r
otectio
n
o
r
cl
osu
r
e type,
ci
rcuit
co
mplexi
ty,
regul
ation a
c
curacy i
s
n
o
t
high. Thi
s
p
a
per
pre
s
e
n
ts
a micro
c
ont
ro
ller a
s
the
co
re of the
pul
se
-
width-adju
s
ta
ble high
-p
re
ci
sion n
u
me
rical con
s
t
ant voltage po
we
r supply, a DC voltage so
urce
to overco
me the tradition
al sho
r
tco
m
ing
s
, with a high appli
c
ation va
lue.
2. The Gener
a
ting Princip
l
e of the Con
s
tan
t
Cu
rren
t
Po
w
e
r
In this de
sig
n
, the output
voltage thro
ugh the mi
croco
n
trolle
r
C8051F
410
re
al-time
sampli
ng, th
e sam
p
ling
value co
mpa
r
ed
with the
settings, u
s
e the re
sult
s to adju
s
t the
comp
ari
s
o
n
SCM
DA o
u
tput, TL4
94
u
s
ing
mi
cro
c
o
n
trolle
r
DA o
u
tput voltage
adju
s
t th
e P
W
M
duty cycle, b
y
feedback control,
to achieve the pu
rpo
s
e of th
e
con
s
tant voltage output [1].
TL494 i
s
a fixed frequ
en
cy pulse width
modulatio
n
ci
rcuit, built-i
n linear
sa
w too
t
h oscill
ator, the
oscillation fre
quen
cy ca
n be an extern
al re
sisto
r
an
d a cap
a
cito
r for adju
s
ting
, the oscillati
on
freque
ncy is
as follo
ws:
T
T
osc
C
R
f
1
.
1
(1)
If the capa
cit
o
r unit i
s
"mi
c
ro
-L
aw", the
re
si
stan
ce
u
n
it with "thou
san
d
s
of Europe", the
unit of freq
uen
cy is th
e "kHz." After
co
m
m
issi
oning, th
e
output frequ
ency
ran
g
e
of
25KHz~35K
Hz be
st output waveform mo
re stabl
e.
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 23
02-4
046
TELKOM
NI
KA
Vol. 12, No. 6, June 20
14: 4603 – 4
608
4604
3. The Desig
n
of the
Circ
uit
The de
sign o
f
the circuit, the micro
c
ont
rolle
r C80
5
1
F
410 to achi
eve the overall control
circuit, in
ord
e
r to
ma
ke th
e ci
rcuit mo
re sta
b
le
a
nd
joined t
w
o filt
ers.
The
filter is
calle
d by t
he
cap
a
cito
rs, in
ducto
rs
and
d
i
ode
s an
d oth
e
r ele
c
troni
c
origin
als
com
posed. The
role of the filte
r
is
part of the power
sup
p
lied
to the load using the
energ
y
, while the other part of energy sto
r
ed
in
sho
r
t
sup
p
ly
whe
n
the
po
wer
supply
is interrupte
d
o
r
in
adeq
uate,
the
cap
a
cito
r and
the
indu
ctor
is rele
ased to
put the store
d
energy, power
sup
p
li
ed
to the load to continu
e
in orde
r to en
su
re
uninterru
pted
power
su
ppl
y can p
r
ov
id
e
cu
rre
nt to th
e load. T
he m
a
in pa
rt of the
circuit
sho
w
n
in
Figure 1:
Figure 1. Main Part of the Circuit
As sh
own ab
ove, the first (1) feet for the
firs
t gro
up of
the erro
r am
plifier AMP1 inverting
input. By the output voltag
e is fed throu
gh the sa
mpli
ng ci
rcuit sa
mpling
se
ctio
n (1) fo
ot. Section
(2) feet fo
r th
e first group
of the e
r
ror a
m
plifier AMP
1
invertin
g in
put. Sectio
n (1)
pin voltag
e
and
the se
co
nd
(2
) pin volta
ge f
o
r
comp
ari
s
o
n
. Whe
n
the
power
sup
p
ly output voltag
e ch
ang
e, loa
d
voltage
cha
n
ge
with the
sampling
resi
stor voltag
e al
so
ch
ang
es,
and
se
nt to t
he T
L494
first (1)
foot, and sub
s
e
c
tion (2
) fe
et of the voltage re
main
s
con
s
tant, so
that the internal PWM chi
p
comp
ari
ng th
e sample
d v
o
ltage
with t
he voltage
will cha
nge, if
the outp
u
t voltage
rises,
the
comp
arator v
o
ltage in
crea
se
s alo
ng
with the co
mp
arator A2 o
u
tp
ut pulse be
comes na
rro
wer,
and finally the FET cond
uction time
become
s
sh
orter, the ou
tput vo
ltage redu
ce
d, thereby
inhibiting th
e
output voltag
e incre
a
ses,
so th
at
to a
c
hieve a
stabl
e output volt
age p
u
rpo
s
e
s
. If
the output vol
t
age is
re
du
ced, the comp
arison volt
ag
e is follo
we
d
¬ ¬ re
du
ced,
the output of
the
comp
arator A
2
pul
se
s wi
de
r, finally the F
E
T con
d
u
c
tio
n
time be
com
e
s lo
nge
r, so
that the outp
u
t
voltage incre
a
se
s, thereby
supp
re
ssing
the output
vol
t
age, the out
put voltage st
ability. Becau
s
e
the ope
ration
al amplifier i
s
very high m
agnificati
on, i
n
ord
e
r to
prevent high freque
ncy pa
ra
sitic
oscillation
s, this also ap
plied AC ne
gativ
e feedb
ack circuit, gene
rally the
output of the
operational a
m
plifier an
d the "-" input te
rminal,
conn
e
c
ted to a hun
dred of PF ca
pacito
r
s
can
be,
or the capa
ci
tor and
re
sist
or in seri
es i
n
Jie
s
ha
ngq
u
can b
e
, this
cap
a
cito
r is
called "elimin
a
t
e
parasitic osci
llation capaci
tor" or called "elimi
nate parasitic oscillation circuit."
Put the power
sup
p
ly resi
st
ors
and
cap
a
citors
conn
e
c
ted in seri
e
s
after the first (2) fe
et and (3
) is formed
betwe
en th
e l
egs elimin
ate
parasiti
c
o
s
ci
llation
circ
uit.
Section
(4
) fe
et for th
e d
e
a
d
zone
contro
l
side.
Com
parator A1
of the
" - " in
put, is
sent
by the o
scill
ator
OSC sa
wtooth vol
t
age, an
d its "
+
"
side i
s
the T
L494 '
s
first (4) feet, so th
e com
par
ator A1 output p
u
lse i
s
very
wide. Th
e ou
tput
5.
1K
R5
Q3
D3
1N4148
+I
N1
1
-IN
1
2
PW
M
3
D-T
i
m
e
4
CT
5
RT
6
GN
D
7
C1
8
E1
9
E2
10
C2
11
VCC
12
OUT CON
13
VR
EF
14
-I
N
2
15
+I
N
2
16
U3
TL
494
101
C10
104
C9
10
4
C11
100
uF
C20
+2
4
Q2
I
R
F
954
0
1m
H
L1
104
C5
D2
1N5822
330
0uF
C16
1M
R14
104
C8
33K
R16
Vout
100
uH
L2
104
C6
33
00uF
C17
R_L
1
0.
1
R13
2K
R18
20K
R20
2K
R15
V+
1k
R7
10
0
R12
+24V
10K
R23
100K
R19
10K
R11
10u
F
C18
10
R10
AD
2
AD4
10K
R17
+5V
2
3
6
4
7
1
8
5
AR
1
314
0
1K
R25
Res2
10uF
C21
DA
0_
O
u
t
D1
AD1
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
2302-4
046
The Re
se
ar
ch and D
e
si
ge
of the CNC
Con
s
tant Voltage Pow
e
r (S
hiwei Li
n)
4605
waveform A1
, the low-p
o
te
ntial part is
called the
"de
ad zo
ne", it is capa
ble of limiting the out
put
pulse width o
f
the widest [2]. A2 If the compa
r
at
or o
u
t
put pulse wi
dth than
the width of the pulse
output of A1
i
s
n
a
rro
w
er, t
hen th
e outp
u
t of the
O
R
gate
HM p
u
lse widt
h of the
input p
u
lse
width
is wi
de, and
A1 is the
sa
me as th
e wi
dth of the out
put pul
se, so
that it functio
n
s the
role
of the
pulse wi
dth li
mit. Chan
ge
the wavefo
rm sh
own in
Figure 2:
Ch
ange th
e
wa
veform
sho
w
n in
Figure 2.
4. The Desig
n
of the Sy
stem Soft
w
a
re
System soft
ware de
sig
n
inclu
d
e
s
the
use
of
sin
g
l
e
-chip clo
ck freque
ncy,
e
a
ch port
initialization
pro
c
ed
ure, modulu
s
, digita
l-anal
og
conv
ersi
on p
r
o
c
e
ss,
key scan
ner, L
CD d
r
i
v
er
with a
nalog
output a
u
tom
a
tically an
d
quickly
adj
ust the prog
ra
m as well a
s
di
gital/anal
og
interstate m
a
tchin
g
algo
rith
m and so o
n
[3].
4.1. The Reg
u
lation of O
u
tpu
t
Voltag
e
Figure 2. The
Chan
ge of TL494 O
u
tput Wave
Voltage adju
s
tment pro
c
e
s
s
is su
ch
th
at
we
set the
output
voltage, the
outpu
t voltag
e
increa
se
s fro
m
0V, the width adju
s
tme
n
t pro
c
e
ss,
the chi
p
after
the adju
s
tme
n
t of the voltage
contin
uou
sly
measured to
obtain th
e val
ue of
t
he
sa
mpled
voltag
e an
d in
crea
se the
DA
out
put,
so th
at the
se
con
d
pi
n
voltage ri
se
s TL4
94, TL
4
94 th
roug
h i
n
ternal
comp
arison, the
fi
nal
increa
se
in t
he d
u
ty cy
cl
e
of
the
power
switch
, the output voltage incre
a
se
s, contrary to the
t
A2
O
UT
0
(
b)
t
HM
O
UT
(
d)
t
HF
1
OU
T
(
f)
t
HF
2
OU
T
0
(
h)
t
Y1
O
UT
0
(
e)
t
Y2
O
UT
(
g)
t
A1
O
UT
(
c)
(
V)
U
0
A2
“-
”
V4
A1“
-
”
0
(
a)
t
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 23
02-4
046
TELKOM
NI
KA
Vol. 12, No. 6, June 20
14: 4603 – 4
608
4606
above adju
s
t
m
ent pro
c
e
ss, programmin
g
flowchart s
hown in Figure 3. In order t
o
detect whet
her
the system i
s
being outp
u
t voltage is re
gulated,
in th
e device a
d
d
ed an LED,
whe
n
the system
adjustment, LED lights
will
blink on
ce,
so you
can adjust the prog
ram has to be a better process
monitori
ng, if the sy
stem
stop
adjust
m
ent, LE
D
will stop flashing until commissioni
ng is
c
o
mpleted [4-5].
4.2. The Con
v
ersion of Outpu
t
Analo
g
AD co
de val
ues
coll
ecte
d
by the sy
ste
m
ho
w to
co
nvert an
alog
voltage an
d
curre
n
t
values, th
at i
s
, digital/a
nal
og mat
c
h
bet
wee
n
. In th
e
range
of all
o
wable
erro
r,
t
h
is study sele
ct
ed
the cal
c
ulatio
n spe
ed of lin
ear inte
rpol
ation [5].
Linea
r inte
rp
olation m
e
th
od of th
e d
a
ta pr
ocessin
g
is
pe
rform
e
d
by the
anal
og
sign
al
has
bee
n de
posite
d
an
d the am
ount of
digital si
gnal
mea
s
ureme
n
t seq
uen
ce
(x0, y0), (x1,
y1),
(x2, y2), ..., (
x
n-1, yn-1), to c
a
lc
ulate the requ
ired matc
h eac
h
reques
t
ed data. In this
des
ign,
that is alre
ad
y stored in th
e digital/anal
og bet
ween t
he co
rrespon
ding value
s
, whe
r
e the vol
t
age
value is corre
s
po
ndin
g
to the voltage A / D cod
e
and t
he D / A code
sho
w
n in Ta
ble 1.
Figure 3. The
Main Flow
Chart
Table 1. The
Value of A/D & the D/A and Output Voltage
Number
D/A
A/D
Voltage
1 0
18
0.09
2 500
253
1.45
3 1000
496
2.86
4 1500
738
4.26
5 2000
978
5.66
6 2500
1220
7.06
7 3000
1462
8.46
8 3500
1705
9.85
9 4000
1947
11.23
10 4500
2189
12.61
11 5000
2432
13.99
12 5500
2674
15.35
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
2302-4
046
The Re
se
ar
ch and D
e
si
ge
of the CNC
Con
s
tant Voltage Pow
e
r (S
hiwei Li
n)
4607
For a
n
y voltage AD valu
e
s
colle
cted x, 1, x is
in loo
k
-u
p table
ha
s the lo
catio
n
of the
seq
uen
ce of
measurement
s is xi
≤
x
≤
xi +
1
(
0
≤
i
≤
n-2), ove
r
th
e sam
e
interpolation, can
be
dra
w
n the AD code
corre
s
p
ondin
g
to t
he voltage y, calculate
d
as foll
ows:
1
1
()
ii
ii
ii
yy
yy
xx
xx
+
+
-
=+
-
-
(2)
For exam
ple
,
the sele
cted point
s a
nd the
interpolation d
a
ta are
cal
c
ul
ated by
interpol
ation
of the corre
s
p
ondin
g
voltag
e y is:
32
22
32
()
yy
yy
xx
xx
-
=+
-
-
(3)
4.3. Ke
y
Detection
Keyboard st
and-alon
e keyboard,
first detected i
n
the button
is p
r
esse
d, the ke
y
corre
s
p
ondin
g
to th
e
ro
w
line i
s
lo
w, th
e impl
ementa
t
ion
of a
1
0
m
s delay su
broutin
e, con
f
irm
that the line
cord i
s
still low, If
the descri
ption of the li
ne does ha
ve key
press.
When the key is
released, the row lines low to
high, the Executive
10ms del
ay li
ne i
s
still high detection li
ne,
indicating tha
t
key really lifted. After setting the
numb
e
r of keys, ta
king into a
c
count if the button
too mu
ch
will
not only affe
ct the run
n
ing
spe
ed, but al
so the
ha
rd
ware
de
sign m
o
re
com
p
lex
and
pron
e to erro
r, so that the
leftmost button with
the
e
x
it function. De
sign
set th
e four b
u
tton
s
,
each of the functio
n
key
s
are diffe
rent, su
ch a
s
adj
u
s
ting the
size
of the sam
p
l
ed voltage va
lue,
the outp
u
t vol
t
age valu
e of
the si
ze, th
e
calib
ration
D/
A, A/D co
de
value relation
ship
s. Keybo
a
rd
detectio
n
flow chart
sho
w
n
in Figure 4:
Figure 4. The
Flow Ch
art K
e
y Detectio
n
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 23
02-4
046
TELKOM
NI
KA
Vol. 12, No. 6, June 20
14: 4603 – 4
608
4608
Whe
n
the system is run
n
in
g, the LCD screen
di
spl
a
ys the initial sampling voltag
e value,
then if you click the S1
key
,
the LCD will
displa
y to se
t the output voltage value,
pre
ss S2 b
u
tton
if the value o
f
the output volt
age doe
s
not exceed t
he ran
ge will
be increa
se
d
by one, if by S3
key value
do
es n
o
t exce
e
d
the outp
u
t voltage ra
ng
e will b
e
re
d
u
ce
d by on
e
if the pre
s
s
S4
button
will
ret
u
rn to the initi
a
l screen that
is
di
splayed
on the LCD
sampled voltage values
[6]. Is
displ
a
yed on
the LCD voltage value
set
in the ca
se
, i
f
you click S1
, the LCD
display will switch
to adjust the
A/D value interface.
4.4. The Inte
rfac
e Progra
m
of LCD
Used
i
n
the
desi
gn
i
s
12
232F
L
CD,
it
s
o
p
e
r
ating
voltage rang
e
of +3V
~
+5
.5V,
7.5
Chin
ese ch
aracters
can be
displaye
d.
LCD p
r
o
c
e
ss
shown in Figu
re 5.
Figure 5. The
Interface Pro
g
ram of L
C
D
5. Conclusio
n
C80
51F4
10
as the devi
c
e to the system's main
control chi
p
, TL494 pul
se width
modulato
r
wi
th drive h
a
rd
ware runni
ng
softwa
r
e progra
mming, usin
g
liqui
d cry
s
tal
di
spla
ys
buttons a
d
ju
st the voltage 1223
2F ch
an
ging ci
rcum
stances, with
small size, lig
ht weight, sm
all
ripple
cha
r
a
c
t
e
risti
cs, to a
c
hieve a stabl
e output voltage.
Referen
ces
[1]
Lu Ha
n. Desi
g
n
and
Deve
lo
p
m
ent of Direct
Current
Stab
il
ized Vo
ltag
e S
ource
w
i
t
h
Di
g
i
tal Co
ntrol.
Shanx
i Electro
n
ic T
e
chn
o
lo
gy
.
2013; 4: 3-5.
[2]
Xi
ao-
don
g S
H
EN, Qian
LIU,
An-zh
ong
DE
NG, Shen
g-b
o
LI. Res
earch
on
Hig
h Prec
is
ion
Co
nstant
Current So
urc
e
Base
d on C
onstant D
egre
e
Sourc
e
.
Jou
r
nal of L
o
g
i
stical Eng
i
n
eeri
n
g Univ
ersity
.
201
3; 27: 78-8
0
.
[3]
Z
hang Z
h
a
n
S
ong, Ca
i Xua
n
three. S
w
itc
h
i
ng po
w
e
r su
p
p
l
y
th
eor
y a
n
d
desig
n. Beiji
n
g
: Electronic
Industr
y
Pr
ess. 2010.
[4]
Z
hao T
ao, Z
hang
Hai
y
a
n
. P
e
rformanc
e s
w
itchin
g DC
po
w
e
r su
ppl
y
de
sign.
Nu
cl
ea
r Te
ch
n
o
l
o
gy
.
200
4; 27: 25-3
0
.
[5]
Yamin L,
W
a
n
m
ing C.
Impl
e
m
e
n
tatio
n
of S
i
ngl
e Pr
ecisi
o
n
F
l
oati
ng P
o
int
Squ
a
re
Root
on F
P
GAs
.
IEEE S
y
mpos
i
u
m on FPGA for Custom Co
mputin
g Machi
nes. Nap
a
. 200
8: 226-2
32.
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