TELKOM
NIKA Indonesia
n
Journal of
Electrical En
gineering
Vol. 12, No. 11, Novembe
r
2014, pp. 76
2
2
~ 763
0
DOI: 10.115
9
1
/telkomni
ka.
v
12i11.66
73
7622
Re
cei
v
ed
Jul
y
30, 201
3; Revi
sed Septe
m
ber
14, 201
4; Acce
pted
Septem
ber 3
0
, 2014
Power Factor Correction using Valley-Fill SEPIC
Topology with Fuzzy Logic Control
R.Balam
u
r
u
gan, S.Harip
r
asa
th*, R.Ni
thy
a
Dep
a
rtment of Electrical
and
Electron
ics En
gin
eeri
ng,
K.S.Rangas
am
y Co
lle
ge of T
e
c
hno
log
y
, T
a
milna
du, Indi
a
Vell
alar C
o
ll
eg
e of
T
e
c
hnol
og
y, T
a
milnad
u, Indi
a
*Corres
p
o
ndi
n
g
author, e-ma
i
l
: drnrba
ls@gm
a
il.com
A
b
st
r
a
ct
This
paper deals
with a new singl
e
ended primary inductance c
onv
ert
e
r (
SEPIC) for power factor
correctio
n (PFC). The pr
opos
ed co
nverter
is
used
in
co
mb
i
natio
n w
i
th SE
PIC an
d a v
a
ll
ey fill c
i
rcuit. T
h
e
valley
fill c
i
rcuit
improv
es the
efficiency
of th
e SEPIC
by r
e
duci
ng th
e har
m
o
nics i
n
the
supp
ly
m
a
i
n
s. The
pow
er factor is
also e
n
h
anc
e
d
co
mp
ared to
the conv
entio
nal PF
C co
nve
r
ters. It uses the si
mp
le c
ont
ro
l
strategy for c
o
ntrolli
ng
the
po
w
e
r fa
ctor of t
he A
C
ma
ins.
It can b
e
pr
efe
rred to
low
p
o
w
e
r app
licati
o
n
s
,
since it has th
e mer
i
ts like le
ss input curren
t
ripples
an
d le
ss total harmo
nic distortio
n
(T
HD). T
o
observ
e
the perfor
m
a
n
c
e of the Vall
e
y
fill circuit, a mo
de
l bas
ed
on the SEPIC
topol
ogy h
a
s b
een d
e
si
gne
d
by
usin
g MULTISIM and MATLAB / SIMULINK envir
on
me
nt and i
m
pl
e
m
e
n
te
d w
i
th one cycle control (OC
C
)
and
F
u
zz
y
log
i
c contro
ller. T
h
e si
mulati
ons
r
e
sults
are
de
monstrated
i
n
or
der to
va
lid
ate
the effectiv
ene
ss
of the controll
e
r
s in pow
er factor improv
emen
t.
Ke
y
w
ords
:
Vall
ey-Fill SEP
IC topolo
g
y, one cycle co
ntrol, fu
z
z
y
lo
gic
control
l
er, pow
er factor correctio
n
and total
har
monic d
i
stortion
Copy
right
©
2014 In
stitu
t
e o
f
Ad
van
ced
En
g
i
n
eerin
g and
Scien
ce. All
rig
h
t
s reser
ve
d
.
1. Introduc
tion
Due to the
rece
nt advancement in
the
LED tech
nolo
g
y,
many topolo
g
ies
were
introdu
ce
d to
improve the
perfo
rma
n
ce
of the LE
D
drivers. To
e
n
su
re th
at th
e LED light
s
are
more effici
ent
than the con
v
entional light
ing system
, the Valley-Fill
circuit with S
EPIC topolog
y i
s
prop
osed a
s
a gree
ne
r alternative to ac
hieve po
wer f
a
ctor n
e
a
r
er t
o
unity.
The Europe
a
n
stan
dard IEC 610
00-3-2 (cl
a
ss
C) i
n
stru
ct
s
that the power fa
ctor a
n
d
total ha
rmoni
c di
sto
r
tion
should
be
mai
n
tained
for th
e lightin
g e
q
u
i
pment ex
cee
d
ing
above
2
5
W.
For in
ca
nde
scent la
mp
s, the po
we
r fa
ctor i
s
unity
be
cau
s
e it’
s
a p
u
rely a
re
sisti
v
e load the
n
they
are
inefficie
n
t
in te
rm
s of t
he a
m
ount
of
po
we
r
con
s
u
m
ed. Th
e
po
wer fa
ctor ca
n be
imp
r
ove
d
to
unity by the followin
g
two
method
s: 1)
Passive
po
wer fa
ctor
co
rrection; 2
)
Act
i
ve power fa
ctor
corre
c
tion.
For si
ngle ph
ase ap
plications, pa
ssive
power
filters
and active o
ne or two sta
ge PFC
rectifie
rs with
SMPS (swit
c
hed m
ode
po
wer supply
)
t
opolo
g
ies [1-2] are
the
typical
app
roa
c
h
e
s
to achieve hi
gher
power f
a
ctor
and to redu
ce tota
l h
a
rmo
n
ic di
sto
r
tion. In passi
ve powe
r
fact
or
corre
c
tion, th
e power fact
or ca
n be b
r
o
ught nea
r to
unity using
capa
citors or i
ndu
ctors as t
hey
requi
re
d. Thi
s
filter
nee
ds
a large val
ue
of indu
ctors
a
nd
capa
cito
rs whi
c
h
are bu
lky an
d p
r
ice
y
.
The a
c
tive p
o
we
r facto
r
correctio
n
met
hod i
s
used t
o
ch
ange th
e
nature
of inp
u
t curre
n
t fed
to
the load. The
main intentio
n is to make the load
ap
pe
ars to be p
u
rely resi
stive. For exampl
e, the
power fa
ctor
can
be imp
r
o
v
ed from 0.7
to 0.9 by
usi
n
g the SMPS topolo
g
ies. In
orde
r to a
c
hi
e
v
e
power fa
ctor up to 0.99,
the SMPS topolo
g
ies
are implem
ent
ed with
pa
ssive power fa
ctor
corre
c
tion
circuits.
Without
any po
we
r factor corr
e
c
tion ci
rcuits, th
e po
wer fact
or i
s
only a
b
out
0.75 to 0.85.
The sin
g
le
stage PF
C ci
rcuit
s
(Fi
gure
1) we
re e
m
ployed to dri
v
e multiple L
E
D
lamps a
nd al
so to eliminat
e the addition
al DC to DC stage.
The ci
rcuit choices a
r
e b
u
ck, boo
st, buc
k-boo
st, flyback and
single end
ed
prima
r
y
indu
ctan
ce
converte
r [2-3
] etc. The
s
e
topologi
es
a
r
e a
ppo
site f
o
r different p
o
we
r level
a
n
d
cu
stome
r
n
e
c
e
ssitie
s
. T
h
e si
ngle
en
d
ed p
r
ima
r
y in
ducta
nce
con
v
erter
ha
s th
e adva
n
tage
s of
less noi
se, less
swit
chin
g loss and it can be ope
rat
ed at highe
r freque
nci
e
s t
han that of the
flyback co
nverter.
T
o
tal numbe
r
of compon
ent
s i
s
si
milar fo
r both the S
EPIC and flyback
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
2302-4
046
Power Factor Correction using Valley-Fi
ll
SEPIC Topology with Fuzzy…
(R.Balam
urugan)
7623
conve
r
ters (n
umbe
r of po
wer compo
nent
s and
su
ppo
rtive comp
one
nts). Th
e mai
n
disa
dvanta
ge
of the flyback convert
e
r is
requi
re
d of snubb
er.
Co
ntinual inp
u
t current not only
redu
ce
s ri
ppl
es,
it also improv
es the
electromagneti
c
emi
ssi
ons
of the
system. So, this
SEPIC converter can
be
use
d
for hig
h
brightn
e
ss
LED lighting
appli
c
ation
s
4
without re
qui
ring excessiv
e compli
catio
n
,
comp
one
nt count and
co
st.
Figure 1. Sin
g
le Stage LED Driver Circuit
2. Valle
y
Fill SEPIC Topolog
y
Figure 2
shows the block
diagram
of the
Valley-Fill
SEPIC Topol
ogy, the total
harm
oni
c
distortio
n
is redu
ced a
nd p
o
we
r facto
r
is impr
oved
wh
en the co
nverter is ope
rate
d with co
nsta
nt
ON and OFF
time.
(a)
(b)
Figure 2. Valley-Fill SEPIC Topology
The in
put
sou
r
ce
i
s
the
AC
line a
nd th
en
some
type
of
conve
r
si
on
st
age m
u
st
be
carrie
d
out amo
ng th
e line
and
the
LEDs. So th
e diod
e
re
ctifier i
s
the
front
end
co
nverte
r for all the
L
E
D
drivers. Th
e i
nput 23
0V, 5
0
Hz AC volta
ge is ap
p
lied to
the
dio
de rectifier whi
c
h conve
r
ts
th
e AC
to DC voltag
e. The main
probl
em with
this diode re
ctifier is that
it is a nonlin
ear devi
c
e a
nd it
draws a nonli
near input current. The Val
l
ey-Fill [5
-7] SEPIC topology is used to
modify the wave
sha
pe of current dra
w
n by a load. It consist
s
of
passi
ve compo
nen
ts and two di
ode
s. This ci
rcuit
in addition
with SEPIC topology
improves the power f
a
ctor.
3. Control Technique for SEPIC Valle
y
Fil
l
Circuit
3.1. One C
y
cle Contr
o
l (O
CC)
Control ci
rcuit
for On
e Cy
cl
e Co
ntrol te
chniqu
e is
sh
o
w
n in
Figu
re
3. At the begi
nning
o
f
each switchi
ng pe
riod, a
con
s
tant fre
q
uen
cy cl
o
c
k turn
s O
N
the
transi
s
to
r [8-10]. The out
put
voltage i
s
inte
grated
an
d
co
mpared
with t
he
referen
c
e
value. If the i
n
tegrate
d
volt
age
attains th
e
referen
c
e value, the comp
arato
r
cha
n
g
e
s its stat
e. Whe
n
the integrato
r
is re
set to zero, the
transi
s
to
r is t
u
rne
d
OF
F. If the co
ntrol
referen
c
e
i
s
st
able, then th
e
averag
e of t
he dio
de volt
ag
e
and the outp
u
t
voltage is co
nstant.
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 23
02-4
046
TELKOM
NI
KA
Vol. 12, No. 11, Novem
ber 20
14: 76
22 – 763
0
7624
Figure 3. Con
t
rol Circuit -
One Cy
cle Control
The sl
ope
of the integratio
n is
di
re
ctly propo
rtion
a
l to
the input vol
t
age. The int
egrate
d
value is al
wa
ys compa
r
ed
with the
co
nstant co
ntro
l
referenc
e. If t
h
e input voltage is higher, t
hen
the slope of
the integration is
stee
pe
r; therefore, the integr
atio
n value attains the co
ntrol
referen
c
e
qui
cker. A
s
a
re
sult, the
duty
ratio i
s
i
n
versely pro
p
o
r
tion
al to the
inp
u
t
voltage. If the
control refe
re
nce i
s
varia
b
l
e
, then the di
ode voltage i
s
equ
al to the
chan
ging
co
ntrol refe
re
nce in
each cy
cle; t
herefo
r
e, the
output voltag
e equ
als
the
referen
c
e volt
age. Th
e inte
grated
value
of
the diode volt
age catch
e
s t
he co
ntrol referen
c
e imm
e
diately.
Figure 4. Sim
u
lation Circuit - Valle
y-Fill
SEPIC Topolo
g
y with OCC
The
simulation circuit for one cy
cle
cont
rol te
chnique with Valley-Fill circuit i
s
shown i
n
Figure 4. Simultaneo
usly
to turn ON t
he tran
si
st
or
and to trigg
e
r
the Integrator, the co
ntroller
use
s
con
s
tan
t
frequen
cy p
u
lse
s
. The
n
the integ
r
at
ed
output voltag
e is
comp
are
d
with a
co
ntrol
referen
c
e. Th
e instant wh
en the integrated output
voltage re
ach
e
s the contro
l refere
nce, the
transi
s
to
r is t
u
rne
d
OF
F a
nd the Integ
r
ator valu
e is
res
e
t to
z
e
ro. I
f
the c
o
ntrol
referenc
e is
even
,
then they obtained ave
r
ag
e of t
he outpu
t voltage is invariable.
3.2. Fuzzy
Controlled Val
l
e
y
fill SEPIC
Topolog
y
The
simul
a
tion ci
rcuit for fuzzy
l
ogi
c cont
roller with Val
l
ey-Fill
circuit
[11-12] is shown in
Figure 5. The per
for
m
anc
e
of fuzzy logic
c
o
ntr
o
ller
only depends
on the s
e
lec
t
ion of
member
ship func
tion var
i
ables
and inference of fu
z
z
y
r
u
les
.
A fuzzy logic
c
ont
r
o
ller
is
a pow
e
rful
tool in
coping
with
time va
rying th
e n
o
n
linearitie
s an
d un
ce
rtaintie
s [13
-
1
5
]. By usi
n
g
this, t
h
e
input cri
s
p val
ues a
r
e conv
erted into fuzzy vari
able
s
a
n
d they are m
appe
d
as lin
g
u
istic la
bel
s.
The Memb
ership Fu
nctio
n
(MF) of the input
and out
p
ut variable
s
of fuzzy are
gene
rally
defined on a
common u
n
i
v
erse of discourse. For
h
a
ving the be
st desig
n of FLC, the pro
per
sele
ction
of input an
d out
put scalin
g fa
ctors in
cl
udi
n
g
the tunin
g
of other
para
meters ne
ed
ed for
controlle
r, are
very importa
nt. This, in many ca
se
s
is
achi
eved thro
ugh trial a
nd
error to get b
e
st
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
2302-4
046
Power Factor Correction using Valley-Fi
ll
SEPIC Topology with Fu
zzy… (R.Balam
urugan)
7625
perfo
rman
ce.
For the
prop
ose
d
system,
trian
gula
r
in
put an
d o
u
tp
ut memb
ersh
ip fun
c
tion
s a
r
e
sele
cted
and
it is sh
own in
Fig.6. The F
L
C con
s
is
t
s
of
two inp
u
ts a
n
d
one
output.
The in
puts f
o
r
the FL
C
are
error voltage
e a
n
d
ch
an
ge in
e
rro
r v
o
ltage
∆
e. T
he o
u
tput va
riable
is u
a
nd it
controls the
o
peratio
n of
switch.
Five m
e
mbe
r
sh
ip fu
nction
s
are
chosen fo
r e
r
ror
(e
), chang
e i
n
error (
∆
e) an
d for output (u).
The M
e
mbe
r
ship
fun
c
tion
s a
r
e
define
d
within the
no
rmalize
d
rang
e an
d a
s
soci
ated
with
each lab
e
l:
NB (n
egative
big),
NS (n
egative sm
all
)
, ZO
(zero
)
,
PS (po
s
itive small
)
, an
d
PB
(po
s
itive big).
Figure 6. Sim
u
lation Circuit - Valle
y-Fill
SEPIC
Topology with FLC
Figure 6. Me
mbership Fun
c
tions
Table 1. Rule Matrix
∆
e
NB NS
Z
PS
PB
e O/P
NB NB
NB
NS
NS
Z
NS NB
NS
NS
Z
PS
Z NS
NS
Z
PS
PS
PS NS
Z
PS
PB
PB
PB Z
PS
PS
PB
PB
A kn
owle
dge
ba
se
co
ntai
ns th
e d
e
fini
tion of the
fuzzy sub
s
ets for th
e
con
v
erter
operation, th
eir trian
gula
r
membe
r
ship
function
s an
d
the whol
e ru
les of the inf
e
ren
c
e
syste
m
.
The fu
zzy
co
ntrol
wo
rk fo
r su
ch
rul
e
s in
siste
d
to it. Here
25
rule
s
are f
r
ame
d
fo
r controlling t
h
e
SEPIC c
onverter, thus
the
power fac
t
or is
improved and c
u
rrent
THD is
reduc
e
d.
The ce
ntroi
d
Defuzzification pro
c
e
s
s is
used conv
ert the infere
nce me
ch
ani
sm into
actual inp
u
ts
for the pro
c
e
ss. The
Rule
Viewer
(Fi
g
u
r
e 7) is u
s
ed
to displays the whol
e fuzzy
inferen
c
e p
r
o
c
e
ss a
c
cordin
g to the rule
matrix as giv
en in Table 1.
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 23
02-4
046
TELKOM
NI
KA
Vol. 12, No. 11, Novem
ber 20
14: 76
22 – 763
0
7626
Figure 7. Rule Viewer
Some of the basi
c
rul
e
s framed for the
above po
we
r factor
corre
c
ti
on are give
n belo
w
,
If (e is
NB) and (
∆
e is
NB) then (u i
s
NB)
If (e is
NB) and (
∆
e is
NS) then (u i
s
NB)
If (e is
NB) and (
∆
e is Z
)
then (u is
NB)
If (e is
NB) and (
∆
e is PS) then (u i
s
NS)
If (e is
NB) and (
∆
e is PB) then (u i
s
Z)
The Surfa
c
e
Viewe
r
is a G
U
I (graphi
cal
use
r
interfa
c
e
)
tool use
d
to get a different
three-
dimen
s
ion
a
l
view of the
d
a
ta an
d hel
p
s
to
ex
amine
the outp
u
t surface of th
e
system, fo
r t
w
o
input
system.
The
input
s o
f
the surfa
c
e
viewer
a
r
e error
voltage
e and ch
ang
e
i
n
erro
r
voltag
e
∆
e. The o
u
tp
ut variable
ob
tained from fu
zzy lo
gic
co
ntrolle
r for th
e i
nputs
given i
s
indicated a
s
u.
The overall mappin
g
ha
s b
een do
ne in single plot an
d
is sho
w
n in F
i
g
ure
8.
Figure 8. Surface Viewer
4. PWM Dimming Circuit
Figure 9. PWM Dimming
Circuit
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TELKOM
NIKA
ISSN:
2302-4
046
Power Factor Correction using Valley-Fi
ll
SEPIC Topology with Fuzzy…
(R.Balam
urugan)
7627
A PWM
dimm
ing
cont
rol i
s
employed
a
s
the
second
stage cu
rrent r
egulato
r
as shown in
Figure 9. Thi
s
ci
rcuit use
s
the LM 555 t
i
mer wh
ich g
enerates
a continuo
us p
u
l
s
e throug
h Pin 3
as a squa
re
wave.
The sta
b
le m
ode ha
s no
stable state. T
he out
put ch
ange
s its stat
e contin
ually betwe
en
high an
d lo
w
without any i
n
tervention
s
.
LM 555
time
r based dimmi
ng ci
rcuits a
r
e also used f
o
r
flashin
g
lamp
s and it is u
s
ed as a
clo
c
k pulse fo
r oth
e
r ci
rcuits al
so. This turn
s
the LED light
s
ON
and
OF
F. By varying
the
re
sisto
r
s
R
1
an
d
R
2
,
the turn O
N
an
d turn O
FF
speed
of the
L
E
Ds
can
be
adj
usted. The
lon
ger th
e
ON
perio
d, t
he
b
r
ightne
ss of
the LEDs wil
l
be m
o
re. T
he
potentiomete
r is varie
d
fro
m
5% - 95% t
o
atta
in different voltage le
vels. Wh
en th
e potentiom
e
ter
is adju
s
ted to
the minimum position (0%
)
, the
obtaine
d output voltage is 11.90
8 Volts as sh
o
w
n
in Figure 10(a). During thi
s
period, the
brightne
ss
of the
LED will be
more
. And the brightness of
the LED
will
be le
ss, if th
e pote
n
tiome
t
er i
s
a
d
just
e
d
to the
max
i
mum p
o
sitio
n
(100%).
T
h
e
obtaine
d outp
u
t voltage in this po
sition i
s
1.113 Volts a
nd it is sho
w
n
in the Figure
10(b
)
.
Figure 10. Dif
f
erent Voltag
e Levels
5. Simulation
R
e
su
lt
s
5.1. MULTISIM Simulation Resul
t
s for
One C
y
cle
Con
t
rol
Figure 11
sh
ows the Watt meter and
Disto
r
ti
on An
alyzer
rea
d
in
gs of the p
r
opo
sed
Valley-Fill SEPIC topology with one
cycl
e control
technique. While
driving the P
F
C topology by
impleme
n
ting
the O
C
C te
chniqu
e, the
p
o
we
r fa
ctor
is 0.969
an
d th
e total h
a
rm
o
n
ic
disto
r
tion
is
28.794 %.
Figure 11. Measure
d
Power Fa
ctor a
n
d
THD of O
C
C
5.2. MATL
AB simulation
w
i
th Fuzz
y
Logic Con
t
r
o
ller
Figure 12. Measure
d
Power Fa
ctor a
n
d
THD of FL
C
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ISSN: 23
02-4
046
TELKOM
NI
KA
Vol. 12, No. 11, Novem
ber 20
14: 76
22 – 763
0
7628
Figure 12 sh
ows the power facto
r
as 0
.
9905
and th
e total harmo
nic di
stortion
as 18.9
1
% of the proposed Valley-Fill SEPIC top
o
logy with fuzzy logic
controller.
Figure 13 shows the i
n
put
voltage and current
waveform of t
he Valley-Fill SEPIC
der
ived topology w
i
th fuzzy logic
c
o
ntr
o
ller
.
Figure 13. Input Voltage a
nd Cu
rrent Waveform
The
rectified
DC volta
ge
waveform of th
e sin
g
le
pha
se diod
e rectifi
e
r i
s
sho
w
n i
n
Figu
re
14. The m
a
g
n
itude of the
pulsated
DC
voltage is
23
0V. The duty
cycle
obtain
e
d
from the fu
zzy
logic
cont
roll
er is
sho
w
n i
n
Figure 15
whi
c
h is
sup
p
lied to the
MOSFET swi
t
ch (Q
) d
r
iving the
proposed Val
l
ey-Fill SEPIC
power factor
correcti
on
topology. Due to high
frequency operati
on,
MOSFET is p
r
eferred often
.
Figure 14. Rectified DC Voltage Waveform
F
i
g
u
r
e
1
5
.
Wa
ve
fo
r
m
o
f
th
e
D
u
ty C
y
c
l
e
Figure 16. DC Output Volt
age Waveform
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
2302-4
046
Power Factor Correction using Valley-Fi
ll
SEPIC Topology with Fu
zzy… (R.Balam
urugan)
7629
Figure 16
shows the DC output voltage wave
form
of the Valley-Fill SEPIC derived
topology with
fuzzy logi
c controlle
r. The
magnitu
d
e
o
f
the obtaine
d
dc voltag
e is 59.47V. Th
e
output current
waveform of
the
Valley
-
Fill SEPIC deri
ved
power factor correcti
on topol
ogy
wi
th
fuzzy logi
c co
ntrolle
r is sho
w
n in Figu
re
17. The obtai
ned outp
u
t DC cu
rrent is 0
.
5947A.
Figure 17. Ou
tput Current
Wavefo
rm
5.3. Compari
s
ion of Re
su
lts
The comp
ari
s
on
of power factor a
nd t
o
tal har
moni
c distortio
n
of
the pro
p
o
s
ed
system
with on
e cy
cl
e co
ntrol te
chniqu
e an
d fuzzy logi
c
co
ntrolle
r are
shown in Fi
gu
re 1
8
. By this, th
e
proposed topology is more efficient when the
Valley-Fill SEPIC PF
C topology is
controlled usi
n
g
f
u
zzy
logi
c c
o
nt
rolle
r.
Figure 18. Compari
s
on Chart of OCC a
nd FLC
with Valley Fill SEPIC Circuit
6. Conclusio
n
The
simulation of Valley-Fill SEPIC derived
power factor correction topol
ogy f
o
r LE
D
lighting ap
plication usi
ng o
ne cycl
e cont
rol techniq
ue
and fuzzy log
i
c co
ntroll
er h
a
s be
en
carri
ed
out for
reduci
ng the input
current T
HD
and for im
proving the po
wer factor. T
h
is
Valley fill circuit
contai
ns only
passive component
s
and with the combination
of SEPIC improves the power
factor. T
h
is
p
r
opo
se
d top
o
l
ogy is
small
in si
ze,
le
ss
co
st, with o
n
e
sta
ge of
po
wer conversi
on
,
simple
feed
b
a
ck control a
nd a
c
hieve
s
power fa
ctor
i
s
ne
arer to
u
n
ity. The OCC an
d FL
co
ntrol
techni
ques were em
ployed for cont
rolling the proposed topology. In
this control
setup, the fuzzy
logic
co
ntroll
er p
r
ovide
s
better p
o
wer factor (0
.9
9
05)
and
re
d
u
ce
d total h
a
rmo
n
ic
dist
ortion
comp
ared to OCC (PF=0.
969). Th
us, the MUL
T
ISIM and MATL
AB Simulation results vali
date
the effectiven
ess pro
p
o
s
ed
system.
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ISSN: 23
02-4
046
TELKOM
NI
KA
Vol. 12, No. 11, Novem
ber 20
14: 76
22 – 763
0
7630
Referen
ces
[1]
Z
Lai, KM Smedl
e
y
. A F
a
mil
y
of Co
ntin
uou
s Cond
uctio
n
Mode Po
w
e
r F
a
ctor Correcti
o
n Contro
lle
r
s
Based o
n
the
Genera
l
Pulse
w
i
d
th Mo
dul
ato
r
,
IEEE
Trans. Power Electron
., 1998; 13(3):
501
–5
10.
[2]
R Redl, Po
w
e
r
-
factor correction in si
ngl
e-p
h
a
se s
w
itch
ing-
mode p
o
w
e
r s
upp
lies. An ov
ervie
w
.
Int. J.
Electron.
, 19
94
; 77(5): 555
–58
2.
[3]
M Madiga
n, R Erickson, E Ismail, Int
egrated hi
gh qu
a
lit
y
re
ctifi
e
r regul
ators.
IEEE Trans. Ind.
Electron.,
19
99
; 46(4): 749
–75
8.
[4]
Hua
ng-Je
n Ch
i
u
, Yu-Kan
g L
o
,
Jun-T
i
ng Ch
en, Shi
h
-Jen
Che
ng, Ch
un
g
-
Yi Lin, Sh
an
n
-
Ch
yi Mo
u, A
High-Effici
enc
y Dimma
ble
LE
D Driver
for L
o
w
-
Po
w
e
r L
i
g
h
ting A
p
p
licati
ons.
IEEE Transactions o
n
Industria
l Elect
r
onics
. 20
10; 5
7
(2): 735-
74
3.
[5]
D
y
lan
Dah-
Ch
uan L
u
. Anal
ys
is of an AC-DC
Valle
y-F
i
l
l
Po
w
e
r F
a
ctor Cor
r
ector.
ECT
I
T
r
ansacti
ons o
n
Electrical E
ng., Electronics, a
nd Co
mmunic
a
tions.
200
7; 5(
2): 23-27.
[6]
Hon
gbo Ma, Ji
h-She
ng L
a
i, Quan
yu
a
n
F
eng,
W
ensong Y
u
, Con
g
Z
hen
g, Z
hen
g Z
hao. A Novel V
a
ll
e
y
-
Fill SEPIC-d
e
ri
ved Po
w
e
r Su
ppl
y
w
i
t
h
o
u
t El
ectrol
y
t
ic C
apa
citors for LED
Lig
h
ting A
p
p
lic
ation.
IE
EE
T
r
ansactio
n
s On Pow
e
r Electronics
. 20
12; 27
(6): 3057-
30
71
.
[7]
John
Chi
W
o
L
a
m, Pravee
n K
Jain. A M
odifi
ed Va
lle
y-F
i
ll E
l
ectron
ic Bal
l
as
t Havin
g
a
Cur
r
ent Sourc
e
Reso
nant Inv
e
rter W
i
th Impro
v
ed
Lin
e
-Curr
e
nt T
o
tal Harmo
nic D
i
stortio
n
(
T
HD), High Po
w
e
r F
a
ctor,
and L
o
w
L
a
mp
Crest F
a
ctor.
IEEE Transactions on Industrial Electronics
. 200
8; 55(3): 11
57-1
159.
[8]
Dieg
o
Go
nzal
ez L
a
mar, Ja
vier Se
basti
an
Z
unig
a
, Al
be
rto Rodr
ig
uez
Alons
o, Mig
u
e
l R
odri
g
u
e
z
Gonzal
ez, Marta Maria Her
nan
do Alvar
e
z
.
A Very
Sim
p
le Co
ntrol S
t
rateg
y
for Po
w
e
r F
a
ctor
Correctors Dr
i
v
ing H
i
g
h
-Brig
h
tness LE
Ds.
IEEE Transactions
on Power Electronics
, 200
9; 24(
8)
:
203
2-20
42.
[9
]
D
o
ng
sh
en
g Ma
, Ja
ne
t Wa
ng, Mi
n
k
y
u
So
ng
. Ad
ap
ti
ve
On
-C
h
i
p Po
w
e
r Sup
p
l
y
Wi
th
Ro
bu
st On
e
-
Cy
cl
e
Contro
l T
e
chnique.
IEEE Transactions on V
e
ry Large Sc
ale Integration
(
V
LSI) System
s
. 2008; 16(
9)
:
124
0-12
43.
[10]
Ke
yue
M Sme
d
le
y, S
l
ob
od
an
Cuk. On
e-C
y
c
l
e C
ontro
l of S
w
itc
h
in
g
Conv
e
r
ters.
IEEE Transactions o
n
Power Electronics
. 1995; 1
0
(6
): 625-63
3.
[11]
KV Hari
Prasa
d
, CH
Uma M
ahes
w
a
r
Rao,
A Sri H
a
ri. D
e
sig
n
a
nd S
i
mulati
on
of A
F
u
zz
y Lo
gi
c
Contro
ller for
Buck & Boost
Convert
e
rs.
Internati
o
n
a
l Jo
urna
l Adva
nce
d
T
e
chn
o
lo
gy
& Engi
neer
in
g
Research
. 20
1
2
; 2(3): 218-2
2
4
.
[12]
Kessal, L
Ra
h
m
ani, M Moste
f
ai. Po
w
e
r
F
a
ctor Co
rr
ection
B
a
sed
on F
u
zz
y Log
ic C
ontrol
l
e
r
w
i
th F
i
xe
d
S
w
itc
h
i
ng F
r
eq
uenc
y. 20
12; 2
(
118): 67-
72.
[13]
Hari S, Balam
u
rugan R. A va
lley
-
fill SEPIC-derived po
w
e
r
factor co
rrection topology
for
LED lighting
app
licati
ons
us
ing
on
e c
y
cl
e c
ontrol
techn
i
q
u
e
,
Internati
o
n
a
l
Co
nferenc
e
o
n
C
o
mputer
Co
mmu
n
icati
o
n
and Infor
m
atic
s (ICCCI).
2013: 1-4.
[14]
Z
hang J
i
ng-
yi.
High P
o
w
e
r
F
a
ctor Po
w
e
r
Desig
n
.
T
E
LK
OMNIKA Indo
nesi
an Jo
urn
a
l
of Electrica
l
Engi
neer
in
g.
2013; 11(
7): 397
3-39
80.
[15]
Min-
yan DI, F
u
zz
y
Co
ntrol An
al
ysis
w
i
th B
a
c
k
-EMF
in W
a
shin
g Machi
nes.
T
E
LKOMNIKA Indones
ia
n
Journ
a
l of Elec
trical Eng
i
ne
eri
ng.
201
4; 12(8)
: 5758-5
7
6
5
.
Evaluation Warning : The document was created with Spire.PDF for Python.