TELKOM
NIKA Indonesia
n
Journal of
Electrical En
gineering
Vol. 12, No. 10, Octobe
r 20
14, pp. 7196
~ 720
1
DOI: 10.115
9
1
/telkomni
ka.
v
12i8.564
4
7196
Re
cei
v
ed
Jan
uary 17, 201
4
;
Revi
sed
Ju
n
e
27, 2014; A
c
cepted
Jul
y
19, 2014
Resear
ch on Multichannel Test
Device of Missile Fuze
Guo
y
ong Zhen
1,2
Yanhu Shan*
1,2
, Yir
a
n Wei
1,2
1
Nation
al Ke
y l
abor
ator
y
for E
l
ectron
ic Meas
ureme
n
t T
e
chnolo
g
y
,
North Un
iversit
y
of Ch
ina, T
a
iyu
an 0
3
0
051
2
Ke
y
L
abor
ator
y of Instrument
ation Sci
enc
e & D
y
n
a
mic Me
asurem
ent of Ministr
y
of Edu
c
ation,
North Un
iversit
y
of Ch
ina, T
a
iyu
an 0
3
0
051
*Corres
p
o
ndi
n
g
author, e-ma
i
l
: shan
ya
nh
u@
126.com
A
b
st
r
a
ct
T
h
is pa
per i
n
troduc
es the d
e
sig
n
of multi
c
han
nel
acq
u
i
s
ition circ
uit b
a
sed
on F
P
GA w
h
ic
h
sampl
e
s a
n
d
records
the
D
opp
ler s
i
gn
als,
ig
nitio
n
si
g
nal
an
d
the
wo
rki
n
g co
nd
i
t
io
n o
f
fu
z
e
se
curi
ty
enforce
ment
a
genc
ies of mi
ssile
fu
z
e
in
real-ti
m
e
in
th
e test of
hig
h
spe
ed
dyn
a
m
ic
inters
ectio
n
.
F
u
rthermore, for the pr
obl
e
m
of incre
a
sin
g
nu
mb
er of
sa
mple c
han
ne
l w
h
ich ca
uses the
compl
e
xity of th
e
mu
ltipl
e
xer co
n
t
rol, a gen
eral
progr
a
m
mab
l
e
chan
nel
sw
itchi
ng metho
d
is p
r
opos
ed b
a
sed
on F
P
GA. In
th
e
meth
od, F
P
GA is the co
ntrol core, a
n
d
usin
g the
internal ROM resource
e
ffectively sim
p
lifies
t
he
complexity of c
hannel switch in
the
multichannel ac
quis
i
tion system
. Th
is
paper analy
z
e
s
the ac
quis
i
tion
system des
ig
n, and descr
ibes
the desig
n of hardw
are circ
u
i
t and an
alo
g
sw
itch address
codi
ng in d
e
tai
l
.
T
he test resu
l
t
show
s that the ac
qu
isitio
n
circuit
me
ets
the d
e
si
gn r
equ
ire
m
e
n
ts w
i
th hi
gh s
a
mp
l
i
ng
precisi
on a
nd a
pplic
atio
n val
u
e.
Ke
y
w
ords
:
mi
ssile fu
z
e
,
mult
icha
nne
l, FPGA, sw
itching method
Co
p
y
rig
h
t
©
2014 In
stitu
t
e o
f
Ad
van
ced
En
g
i
n
eerin
g and
Scien
ce. All
rig
h
t
s reser
ve
d
.
1. Introduc
tion
In the missil
e
dynamic int
e
rsectio
n
flight simu
lation
test, usually
test method
is usin
g the
grou
nd
ca
ble
tran
smitting i
n
formatio
n, the tap
e
recorder
and
tele
metry technol
ogy. For the f
e
w
test cha
nnel
s and lo
w speed flight simulation
test, the method of using t
he gro
und
cable
transmitting informatio
n can meet the
experime
n
t requi
rem
ent. Ho
wever, for the high sp
eed
flight experim
ent, due to th
e rel
e
a
s
ing
speed
and
distance
of cabl
e, and th
e rel
i
ability rea
s
o
n
s
su
ch a
s
di
stu
r
ban
ce
s, bro
k
en lin
e, it cannot
be
use
d
. The tape
reco
rde
r
is
be
ing pha
se
d o
u
t
grad
ually b
e
cause of th
e
complex o
p
e
r
a
t
ion an
d
t
h
e
mech
ani
cal s
y
s
t
e
m
r
e
li
ability [1, 2]. Due
to
the hig
h
co
st
and te
st d
ebu
gging
comple
xity the te
lem
e
try is u
s
ed
o
n
small ta
ctical mi
ssile
b
a
ttle
less. With the widely use
d
of storag
e test tech
n
o
logy
which h
a
s m
any advantag
e su
ch as hi
g
h
reliability, lo
w
co
st, multi
c
ha
nnel, l
a
rg
e capa
city
, e
a
sy o
p
e
r
atio
n an
d
so
on
, the
solid
st
ate
recorder is
the bes
t res
o
lution for the test of mis
s
ile fuz
e
[3-5].
With the in
creasi
ng pe
rformance of the
missil
e
,
the test sy
stem is more a
nd m
o
re
com
p
lex
and the n
u
m
ber of te
st signal i
s
al
so g
r
o
w
ing.
In the high
-sp
eed
dyna
mic interse
c
t
i
on
experim
ent, the Do
pple
r
sign
als, igniti
on sig
nal
a
n
d
the wo
rkin
g co
ndition
of fuze secu
rity
enforcem
ent agen
cie
s
are need
ed to re
cord in re
al-t
i
m
e. The more test cha
nne
ls are, the m
o
re
compl
e
x the stru
cture of the data fra
m
e is. The
cha
nnel switch is mainly relate
d to the ord
e
r of
input
cha
nnel
and
the
data
frame.
Whe
n
the
num
ber
of te
st si
gna
l is l
e
ss and
the st
ru
cture
of
data fra
m
e i
s
simple,
reg
u
lating the
switch
or
der
of multiplexe
r o
r
data
fra
m
e can
achi
eve
multicha
nnel
acq
u
isitio
n. Howeve
r, whe
n
the
numbe
r of channel i
s
many, the a
bove re
soluti
on
will undo
ubte
d
ly incre
a
se the difficulty and com
p
lexi
ty of
the syste
m
desig
n. Ch
annel switch of
multicha
nnel
acq
u
isitio
n sy
stem i
s
be
co
ming mo
re
co
mplex. Ho
w t
o
de
sign
of chann
el switch
ing
rea
s
on
ably h
a
s be
co
me th
e key tech
nol
ogy of t
he design of a
c
qui
sition sy
stem.
To solve the
s
e
probl
em
s, we
prop
ose
d
a
desi
gn of soli
d state re
co
rder for the te
st of missil
e
fuze. And for
the
requi
rem
ent
of multichann
el test,
a g
e
n
e
ral
pr
ogram
mable
multichann
el a
c
q
u
i
s
ition
method
is
also
pro
p
o
s
e
d
, whi
c
h
simp
lify the hard
w
are
de
sign fo
r the multicha
nnel a
c
q
u
isiti
on ci
rcuit. Wh
en
the flight sim
u
lation te
st is finished,
we re
co
ve
r th
e flight data
from the
re
corde
r
which
is
conve
n
ient fo
r analyzi
ng th
e cau
s
e of m
a
lfunctio
n
.
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
2302-4
046
Re
sea
r
ch on
Multicha
nnel
Test Devi
ce o
f
Missile Fu
ze
(Guo
yon
g
Zh
en)
7197
2.
The Struc
t
ur
e and Wor
k
ing Principle of Sy
stem
The blo
c
k di
agra
m
of acquisitio
n
and
stora
ge
sy
stem is sho
w
n
in Figure
1. The syste
m
take
s the
27
V pulse si
gn
al wh
ose d
u
ri
ng time i
s
1
0
0
ms
as the trigger si
gnal.
Whe
n
the
mixed
sign
als
go th
rough th
e inp
u
t
interface, these
sig
nal
s a
r
e firstly reg
u
l
a
ted by the
si
gnal regul
ation
module
an
d
are
then
tra
n
s
mitted to
an
alog
switch.
Then, th
e a
n
alog
sig
nal
s
are
tran
smitt
e
d
throug
h a
nal
og switch tha
t
are
seq
uent
ially cont
rolle
d by the lo
gi
c
control mo
dule a
nd
se
n
t
to
ADC. T
he
FPGA sto
r
e
s
th
e converte
d
data into
Fla
s
h mem
o
ry. T
he
re
corded
data i
s
u
p
loa
ded
via USB after finishi
ng the
test. The
sy
stem u
s
e
s
dry battery pa
ck a
s
th
e ind
e
pend
ent po
wer
sup
p
ly, whi
c
h
avoid
s
the
n
eed
of po
we
r
sup
p
ly by
mi
ssile
and
is co
nvenient fo
r i
n
terface d
e
si
gn
and in
stallatio
n
.
Figure 1. The
Block
Diag
ra
m of
Acquisiti
on and Stora
ge System
3.
The De
sign of Ac
quisitio
n
and Storag
e Module
After modul
ating by th
e o
p
e
ration
al a
m
p
lifier,
the m
o
d
u
lated
analo
g
sig
nal
s a
r
e
o
u
tputted to
analo
g
multip
lexer ADG
7
3
2
. And then FPGA cont
ro
l
the address
lines of ADG
732 to switch
in
an order, so
that the 80 analog
sign
als can be
orde
rly inputt
ed into the
analo
g
-to
-
digi
tal
conve
r
ter- T
H
S104
0. The
output di
gita
l sign
al
of A
D
-T
HS10
40 i
s
gath
e
red b
y
FPGA in 1
0
bit
data length. In the FPGA, the sampl
e
d
data w
ill be
framed a
s
the data pa
ck. The stru
ctu
r
e
diagram of acquisitio
n
pro
c
ess is sho
w
n
as the Figu
re
2.
Figure 2. The
Diagram of Acqui
sition Pro
c
e
s
s
3.1.
Signal Condi
tioning
In the p
r
o
c
e
s
s of
de
sign, i
n
orde
r to
gu
arante
e
the
i
n
tegrity an
d
accuracy
of
signal
s b
e
fore
they are
inp
u
tted to anal
o
g
switch, we
use
ope
ratio
n
a
l amplifie
r
with the cha
r
a
c
ter of
rail to
ra
il
to modulate the sign
al. This desi
gn imp
r
oves
the inp
u
t impedan
ce
of signal, an
d at the same
time also red
u
ce
s the
out
put impe
dan
ce
of mod
u
la
ted sig
nal. A
fter mod
u
lating, all the
hi
gh
amplitude
si
gnal
s a
r
e p
r
oce
s
sed
unif
o
rmly into
0
～
2V si
gnal
s that are co
nvenient fo
r
data
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 23
02-4
046
TELKOM
NI
KA
Vol. 12, No. 10, Octobe
r 2014: 719
6
– 7201
7198
sampl
e
. The
-10V
～
+1
0V and -30V
～
+30V interfa
c
e
circuit i
s
sh
own i
n
the
F
i
gure
3(a). T
h
e
0
～
+40V
、
0
～
+1
0V inte
rface
ci
rcuit a
s
sho
w
n
in t
he
Fig
u
re 3
(
b). Acco
rdin
g
to the
different
rang
e of input
, the value of
R1 an
d R2 i
s
different. In Figure 3
(
a
)
, the output VO1 is:
V
1
V
V
(1)
In the Figure
3(b
)
, the outp
u
t VO2 is:
V
1
V
(2)
Acco
rdi
ng to the Equation
(1) and Eq
uati
on (2
), the
sel
e
ction of R1 and R2 is sho
w
n in Tabl
e 1
.
(a)
(b)
Figure 3. (a)-10V~1
0V and
-30V~
30V interface ci
rcuit, (b) 0V
~40V
and 0V~10V i
n
terface ci
rcu
i
t
Table 1. The
Value of R1 a
nd R2
Input rang
e
R1(
Ω
) R
2
(
Ω
)
-10V
～
+10V
13K 150K
-30V
～
+30V
4.7K 150K
0
～
+40V
120K 6.2K
0
～
+10V
160K 39K
The op
eratio
nal amplifie
r i
s
susce
p
tible
to the
cap
a
cit
i
ve load in th
e uni
ty gain
configuration.
To avoid the
phen
omen
a
of oscilla
ting,
the re
sisto
r
RX of 100
Ω
ca
n be in
serte
d
in the output
o
f
operational a
m
plifier. The
block dia
g
ra
m is sh
own in
Figure 4.
+
-
10
0
Ω
MUX
OP
AMP
R
X
Figure 4. The
Block
Diag
ra
m of the Output of op amp
3.2. General
Programma
ble Chann
e
l S
w
i
t
ching M
e
thod
The sa
mple rate of each signal is different,
so wh
en
data packin
g
the hybrid frame i
s
use
d
with
p
r
ime-fra
m
e
an
d subfra
me.
Acco
rdi
ng th
e re
quireme
n
t
of frame fo
rmat, there i
s
no
regul
ar swit
ch
betwe
en ch
annel
s.
The convention
a
l
method i
s
re
g
u
lating the o
r
der of multipl
e
xer
cha
nnel
s to meet the re
quire
ment of
the s
equ
ent
ial cont
rol of
FPGA. However, wh
en the
numbe
r of si
gnal chann
el
is large
r
, the hard
w
a
r
e
desi
gn and t
he co
ntrol of
FPGA are more
compl
e
x. So
the conventio
nal m
e
thod
is fit for
th
e a
c
quisitio
n
syst
em
with a
fe
w
cha
nnel
s,
not
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
2302-4
046
Re
sea
r
ch on
Multicha
nnel
Test Devi
ce o
f
Missile Fu
ze
(Guo
yon
g
Zh
en)
7199
for the
sy
ste
m
with
a l
a
rg
e num
be
r of
cha
nnel
s. Th
erefo
r
e, fo
r th
e complex
ch
annel
switch, we
prop
osed a gene
ral prog
ramma
ble ch
annel
switch
i
ng
m
e
thod. We en
cod
e
all
the switch
addresse
s
according
to th
e fram
e form
at, and
writ
e
them into th
e internal
ROM of FPGA
in
advan
ce. Wh
en the a
c
q
u
i
s
ition
system
works,
the
addresse
s of
cha
nnel
s a
r
e rea
d
out from
ROM
which is name
d
add
r_rom in Fig
u
re 5
to control the grou
p of multiplexers.
Figure 5. The
Control of ROM in the FPGA
In the acq
u
isi
t
ion system,
each sixteen
-cha
nnel
multi
p
lexer
contai
ns fou
r
add
re
ss g
a
tes
(A3,
A2,
A1 and
A0
) and
one ena
ble signal (EN).
E
a
ch
en
able
si
gnal
of multi
p
lexer
uses
one
control lin
e a
l
one a
nd
all
the multiplex
e
rs sha
r
e th
e ad
dre
s
s lin
es. Fo
r th
e
eighty chann
els
acq
u
isitio
n sy
stem, five multiplexers
are
need
ed.
So, nine control lines
can
determine a chan
n
e
l
address, whi
c
h is sh
own in Table 2.
Table 2. The
Corre
s
p
ondin
g
Relatio
n
of the Multiplexer Address
9 bits of address
the enable signals
address gates
EN4
EN3 EN2
EN1 EN0
A3
A2
A1
A0
The
m
e
thod
reali
z
e
s
com
p
lete sep
a
ration
b
e
twe
en the
inp
u
t sig
nal cha
nnel
and the fram
e
format de
sig
n
. And the method is p
r
o
g
r
amma
ble,
which
can a
d
ju
st the add
re
ss co
de of ROM
with the
cha
n
ge of fram
e format. So, th
e method
ha
s gene
rality. In the frame fo
rmat, except t
h
e
cha
r
a
c
teri
stic signal, one signal is a
c
cording to one multiplexer a
ddre
s
s. The data frame fo
rmat
is 58×10. Th
e cha
r
a
c
teri
stic data is 50,
so the
addre
ss nu
mbe
r
is 530. The da
ta width of 9
bit
and the de
pth
of 1024 bit of the ROM in
FPGA
can m
eet the addre
ss
cont
rol re
q
u
irem
ent.
3.3. Storage
Module
The stora
ge module uses Flash
memo
ry
K9
WBG08
U
1M
(4GByte
)
a
s
data
storage, du
e
to the cha
r
a
c
teristics of small size, low powe
r
co
nsu
m
ption, larg
e
memory cap
a
city and so on.
The writing
a
nd re
adin
g
o
peratio
n of Fl
ash i
s
in
th
e
unit of pag
e
.
It is nece
ssary to write the
control word
and a
ddress of next pag
e again
after finishing
wri
t
ing one p
a
g
e
. Therefore,
to
guarantee
da
ta integrity in the alternati
ng time of
ad
jace
nt page,
the intern
al F
I
FO of FPGA is
use
d
as data
ca
che. The
sampled d
a
ta is written
into
FIFO first, and then stored
to Flash. In the
pro
c
e
s
s of
d
a
ta op
eration
,
the ave
r
ag
e
sp
eed
of
i
n
p
u
t of FIFO
i
s
low th
an
ou
tp
u
t. T
o
imp
r
ov
e
the writing
sp
eed of Fl
ash, the interl
eavi
ng two
-
pla
ne
prog
ram
m
ing
mode i
s
u
s
e
d
in the
writin
g
operation th
at the fastest writing spe
ed can
rea
c
h 30MByte/s. The waiting time of p
age
prog
ram
m
ing
is
red
u
ced to
the mini
mum
by the i
n
terle
a
ving p
a
ttern.
Also, to
man
age th
e invali
d
block of Fla
s
h co
nvenientl
y
, the addre
s
s of invalid
bl
ock is id
entified and
written into the RO
M of
FPGA. Whe
n
in the ope
rati
on of pa
ge p
r
ogra
mming,
r
eadin
g
or
era
s
ing, the
add
ress is
rea
d
o
u
t
to compa
r
e
with the current
addre
s
s to identify
whethe
r the cu
rrent block is invali
d or not.
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 23
02-4
046
TELKOM
NI
KA
Vol. 12, No. 10, Octobe
r 2014: 719
6
– 7201
7200
4.
The De
sign of Re
sista
n
c
e
to Ov
erload
The solid sta
t
e
re
corde
r
a
c
compli
she
s
the
acqui
sitio
n
and
sto
r
ag
e of si
gnal
s.
Duri
ng the
colli
sion of
missil
e
high
-spe
ed intersection, the re
si
st
an
ce t
o
ov
erloa
d
ca
p
a
cit
y
of
rec
o
rde
r
rea
c
he
s mo
re than 200
0g
. So the effective me
a
s
ure sho
u
ld be
taken to
stre
ngthen ove
r
l
oad
resi
stan
ce of
the re
corder.
After weldin
g, chip
itself is
su
spe
nde
d in
circuit boa
rd
s, and conn
e
c
t
the circuit bo
ard
s
only through the chi
p
pin. Chip
a
nd circuit bo
ard did
n
’t rea
lly form a whole.
Whe
n
the
re
corde
r
is
hit so h
a
rd,
be
cause the
q
u
a
lity of various com
pone
nts is different, the
overloa
d
is al
so differe
nt. This will be v
e
ry easy
to appea
r loo
s
e solder joi
n
ts, virtual wel
d
ing
or
pull
u
p
weldi
n
g
plate, etc. The circuit
i
s
packa
ged
wit
h
en
ca
psulati
ng m
a
terial
a
nd the
n
b
e
co
me
an integ
r
ated
stru
cture whi
c
h i
s
hel
p for
prote
c
ti
ng the
circuit. The
p
r
ocess i
s
call
ed emb
edm
e
n
t.
With a
spe
c
i
a
l re
sin
of
high
stren
g
th
a
nd hi
gh
to
ug
hne
ss the
ch
ips
and
the
circuit
boa
rd
a
r
e
encap
sulatin
g
into a
whol
e, whi
c
h
can
rest
rict
the m
o
vement
bet
wee
n
the chi
p
and circuit board.
In additio
n
, th
is h
a
s the
effect of
sta
b
le
comp
one
nts,
circuit
param
eters,
to e
n
su
re
no
dama
g
e
to
circuit und
er
high overl
oad
.
5.
Sy
stem Test and Res
u
lt
In the p
r
o
c
e
s
s of
syste
m
t
e
st, a
multich
annel
si
gnal
sou
r
ce i
s
u
s
e
d
to verify th
e fun
c
tion
of
the acq
u
isitio
n system. In the experi
m
en
t, the firs
t operation is e
r
a
s
i
ng after po
we
r-o
n. Whe
n
the
era
s
e o
peration is compl
e
te, +27V ste
p
signal i
s
loa
d
ing to sta
r
t sampli
ng an
d
recordi
ng. After
recording, th
e data i
s
rea
d
into
comp
u
t
er via the
USB interface, and th
en
an
alyze the
dat
a
grap
hically. The software
can
dra
w
u
p
the wave
of all the chan
nels. Me
an
while, it also
can
che
c
k the frame format whether
corre
c
t or not. T
he
partial chan
n
e
ls’ wavefo
rm is sho
w
n i
n
the
Fig.6. The frame form
at of all the dat
a of
each ch
annel i
s
corrct. Thro
ugh
acq
u
irin
g the
sine
ware, the a
c
q
u
isition
pre
c
i
s
ion which is e
x
pres
se
d by
ENOB can b
e
cal
c
ul
ated [
6
-9]. The E
N
OB
of the acqui
si
tion system i
s
better than 8
bit.
Figure 6. The
Partial Cha
n
nels’
Waveform
6. Conclu
sion
This
pape
r p
r
opo
se
d a g
eneral p
r
og
rammabl
e mu
ltichan
nel a
c
quisitio
n
met
hod for the
missil
e
fu
ze
test. For the
eighty
chan
nels an
alog
sign
als whi
c
h
co
nsi
s
ts Do
ppler si
gnal
and
ignition
signal
and the
wo
rking condi
tion
s of the
se
curity fuze enf
orceme
nt age
n
c
ie
s, the devi
c
e
is use
d
soli
d state re
co
rde
r
whi
c
h ca
n resi
st
the overload ca
pa
city of more than
2000g an
d be
employed
re
peatedly. Th
erefo
r
e, the
desi
gn
red
u
ces
experim
e
n
t co
st an
d
has engi
nee
ring
pra
c
tical valu
e. The device has
been
u
s
ed in t
he
hi
gh-spe
ed dy
namic i
n
terse
c
tion expe
rim
ent,
whi
c
h
re
co
rd
s the
si
gnal
s
corre
c
tly an
d
provid
es the
accu
rate
dat
a for t
he fu
ze
de
sign
an
d t
h
e
fault analysi
s
.
Referen
ces
[1]
LI Jing hai
，
S
UN Xi jin
g. A Fast Data Proce
ssing Meth
od i
n
Air Defense
Missile Pro
x
imi
t
y
Fuse T
e
st.
Journ
a
l of Nav
a
l Aero
na
utical
and Astron
auti
c
al Univ
ersity
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9-44
2.
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
2302-4
046
Re
sea
r
ch on
Multicha
nnel
Test Devi
ce o
f
Missile Fu
ze
(Guo
yon
g
Zh
en)
7201
[2]
Che
n
R
u
o
fei,
Bai H
ao. A
Mo
dul
arize
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Ge
ne
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ati
o
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e
sting S
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he
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i
o
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u
ze.
Guid
ance
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u
ze. 2010; 3
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3): 13-17.
[3]
W
e
i W
an, Yon
g
Ho
ng H
u
, Pe
ng W
u
. Multi
C
han
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Rec
o
rd
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ann
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i
al V
e
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cle Bas
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e
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09.
[4]
Abda
lla
h M, Elkee
l
an
y O, Alou
ani AT
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w
-
C
o
st Stand-A
l
on
e Mul
t
ichan
nel D
a
ta
Acquisiti
on
,
Monitori
ng, a
nd
Arch
ival
S
y
stem
w
i
th
On-C
hi
p Si
gna
l Pre
p
roc
e
ssin
g
. Instru
mentatio
n a
n
d
Measur
ement.
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011;
60( 8): 281
3-2
827.
[5]
Su Shuj
ing, L
e
i Jia
n
she
ng.
A Method of Multi-
cha
n
n
e
l
Data Acqu
isiti
on
w
i
th Ad
just
abl
e Sampl
i
n
g
Rate.
T
E
LKOMNIKA: Indones
i
an Jour
nal
of
Electrical E
ngi
ne
erin
g.
201
3; 11
(9): 5299-
53
07
.
[6]
Shiro
ng Yi
n, Yituan
He. Si
nuso
i
da
l Sig
n
a
l Gen
e
rator
for ADC T
e
sting in M
i
xed-
Sign
al SOC.
T
E
LKOMNIKA: Indones
ia
n Jo
urna
l of Electri
c
al Eng
i
ne
eri
n
g
. 2013;
11(7):
371
1-37
17.
[7]
Dani
el
Bel
e
g
a
, Dari
o Petri.
Accurac
y
ana
l
y
sis
of the
a
m
plitu
de
estim
a
tion
of a
sin
e
-
w
av
e b
y
t
h
e
ener
g
y
-bas
ed
method us
in
g the dir
e
ct and i
ndir
e
ct proced
ures.
Measur
e
m
e
n
t.
2012; 4
5
(
9): 2264-
22
7.
[8]
IEEE Std. 12
41-2
000, IEE
E
Standar
d f
o
r T
e
rminol
o
g
y
a
nd T
e
st Methods for
Anal
og-to-D
igit
al
Conv
erters, IEEE, NY, 2001.
[9]
Armin J
a
li
li, Sa
ye
d M
a
sou
d
S
a
yed
i
, J J
a
cob
W
i
kner, A
bol
g
hasem
Z
e
id
aa
bad
i N
e
zh
ad.
A no
nli
n
e
a
r
i
t
y
error cali
brati
o
n techni
qu
e for pipe
lin
ed AD
C
s
.
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n
a
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