TELKOM
NIKA
, Vol. 11, No. 2, Februa
ry 2013, pp. 754~760
ISSN: 2302-4
046
754
Re
cei
v
ed Au
gust 5, 201
2; Re
vised Decem
ber
29, 20
12; Accepted
Jan
uary 13, 2
013
A Monolithic 0.18
μ
m 4GHz CMOS Fre
quency
Synthesizer
Wu Xiushan*
, Huan Ch
an
ghong, Lv
W
e
i, Hu Ming, Li Qing
Colle
ge of El
e
c
trical & Mech
anic
a
l Eng
i
n
e
e
r
ing of Ch
ina Ji
lian
g
Un
iversit
y
, Hangzh
ou 3
1
001
8, Chi
n
a
*Corres
p
o
ndi
n
g
outhor, e-ma
i
l
:
w
u
xius
han
@
c
jlu.e
du.cn
A
b
st
r
a
ct
A 4 GH
z
P
L
L
(phase-
lock
ed
loop)-typ
e fre
que
ncy synthe
s
i
z
e
r
has b
e
e
n
impl
e
m
ent
ed
in th
e
standar
d 0.
18
μ
m
mixe
d-sig
n
a
l a
n
d
RF
1P
6M CMOS tec
hno
logy. It i
n
t
egrates
a V
C
O, a du
al-
m
o
d
u
lus
presca
ler, PF
D, a charge pu
mp, a contro
l l
ogic, vari
ous di
gital co
unters
and d
i
gita
l regi
sters onto a singl
e
chip. W
i
th th
e
hel
p of th
e l
i
ne
ar
mod
e
l
of the
loo
p
, the
des
i
gn
and
opti
m
i
z
ation
of the
lo
o
p
p
a
ra
meters
a
r
e
discuss
ed i
n
d
e
tail
ed. T
he
measur
ed r
e
sult
s show
that th
e lock
ed r
ang
e w
a
s 40
96-4
288 M
H
z
a
nd
t
h
e
phas
e no
ise co
uld re
ach -1
17
dBc/H
z
at 1MH
z
offset fr
om th
e carrier 4.1
54
GH
z
,
the out
pu
t pow
er is abou
t
-3 dB
m. T
h
e c
h
ip
are
a
is
0.6
75
mm×
0
.7
00
mm. T
h
e
DC
p
o
w
e
r cons
u
m
p
t
ion
of the c
o
r
e
p
a
rt is
abo
ut
2
4
mW
und
er 1.8
V supply.
Ke
y
w
ords
: freque
ncy synthe
s
i
z
e
r
; VCO; PFD; CP; phase n
o
ise
Copy
right
©
2013 Un
ive
r
sita
s Ah
mad
Dah
l
an
. All rig
h
t
s r
ese
rved
.
1. Introduc
tion
Frequency synthesis is a process ge
nerati
ng lots
of the same stable and precise
discrete f
r
eq
u
ency by reference si
gnal
source
wi
th on
e or m
o
re f
r
e
quen
cy sta
b
ility and very hi
gh
accuracy th
rough th
e fre
quen
cy do
m
a
in line
a
r
op
eration. It i
s
widely u
s
e
d
i
n
co
mmuni
ca
tion,
navigation, ra
dar and mea
s
uri
ng equip
m
ent.
Use
fre
quen
cy synth
e
si
s technol
o
g
y made
a
si
gnal
sou
r
ce
calle
d
frequ
en
cy synthesi
z
er,
which i
s
th
e key modul
es i
n
the resea
r
ch of an
alog
RF
transceive
r
system. There
are three co
mmon reali
z
a
t
ion app
roa
c
h
e
s: direct
f
r
e
q
uen
cy
sy
nt
he
sis,
phase lock loop type fre
quency syn
t
h
e
sis and di
gital
frequenc
y synthesis
. Among them,
th
e
pha
se lo
ck lo
op type frequ
ency synth
e
si
zer i
s
wid
e
ly
us
ed in RF
communic
a
tion s
y
s
t
em [1, 2].
2. Transceiv
e
r architectu
r
e and Freq
u
e
nc
y
Plan
The a
r
chitect
u
re a
nd fre
q
u
ency pla
n
of the RF
tran
sceiver play an
importa
nt rol
e
in the
compl
e
xity and pe
rform
a
nce
of the o
v
erall sy
st
em
. The sim
p
lified blo
c
k dia
g
ram
of a zero
-
se
con
d
-IF d
u
a
l-conve
r
si
on
tran
sceiver i
s
sho
w
n in
F
i
gure
1. The
use
of this
a
r
chite
c
tu
re, the
LO_IF i
s
ge
n
e
rated f
r
om t
he LO
_RF
u
s
ing a divid
e
-b
y-four
cou
n
te
r, eliminate
s
t
he ne
ed for t
w
o
synthe
sizers and imp
r
ove
s
the transmitt
er’s im
age rej
e
ction [3].
The frequ
en
cy synthe
sizer gen
erate
s
th
e qu
adrature
1 G
H
z an
d 4
GHz L
O
freq
uen
cie
s
use
d
for the
mixers in the
receiver and
transmi
t chai
ns. Fig
u
re 2
sho
w
s a
blo
c
k di
agram of
the
freque
ncy sy
nthesi
z
e
r
, wh
ich is m
ade u
p
of a phase freque
ncy det
ector
(PFD), a cha
r
ge
pu
mp
(CP), a lo
w p
a
ss filter (LP
F
), a VCO, and a down scaling ci
rcuit. The freq
uen
cy band at 4 GHz i
s
gene
rated
by the VCO, a
nd the q
uad
rature
1 G
H
z
LO si
gnal
s a
r
e o
b
tained
b
y
the frequ
en
cy
divider worki
ng at
divided
-by-4
in
the
down
scaling
ci
rcuit, then
K
=
4
.
In
this PLL s
y
s
t
em, the
down scalin
g
circuit con
s
i
s
ts of th
ree
parts:
a
syn
c
hron
ou
s fre
q
uen
cy divider workin
g in t
h
e
divide-by
-4 m
ode, a du
al-m
odulu
s
p
r
e
s
caler (DMP
), and a prog
ram
m
able & plu
s
swallo
w divid
e
r
made
up
of
cou
n
ter-M a
n
d
counte
r-A.
The
DMP
d
i
vides th
e ou
tput by
P
+1
until
counte
r-A
c
o
unts
up to
A
. At this point it switche
s
over and divi
des by
P
until counte
r-M
co
unts up to
M
.
In the p
r
op
osed fre
que
ncy
synthe
si
zer,
K
=4,
P
=8,
M
=32,
and
A can b
e
set b
e
twee
n
3
and 10 i
n
the
prog
ramm
ab
le & plus
swa
llow di
vide
r. Then the t
w
o
counte
r
s are
reset, and DMP
swit
che
s
b
a
ck to divide
-by
-(P
+1)
at the
same
time. T
he total divisi
on ratio of th
e do
wn
scali
ng
cir
c
uit
is:
()
NK
P
M
A
(1
)
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
2302-4
046
A Monolithic
0.18
μ
m
4GHz CM
OS Freq
uen
cy Synthe
sizer (Wu Xiu
s
ha
n)
755
The synthe
si
zer p
h
a
s
e lo
cks an on
-ch
i
p VC
O to a 4 MHz refe
rence frequ
en
cy. The
synthe
sized frequ
en
cy ca
n be varied
from 4.
144 t
o
4.256 GHz in a step of 16MHz, whi
c
h
corre
s
p
ond
s
to an RF ca
rrier
cente
r
freque
ncy ra
n
g
ing from 5.
18 to 5.32 G
H
z in a
step
o
f
20MHz. The
operation freque
ncy of
the pro
p
o
s
e
d
tran
sceiver in t his pa
per
covers t
h
e
5.15
～
5.35
G
H
z b
and.
Figure 1. Simplified RF Tra
n
sceiver
Arc
h
itec
ture
Figure 2. Block
Diag
ram o
f
PLL Freque
ncy
Synthesizer
3. Behav
i
oral Simulations
The p
r
op
ose
d
CPPLL typ
e
frequ
en
cy
synt
he
sizer
can be
model
ed a
s
a lin
ea
r sy
stem.
Figure 3 give
s the line
a
r
model of
CPPLL type
fre
quen
cy synth
e
si
zer. T
he
PFD an
d CP
are
combi
ned
as one blo
c
k, IP is t
he current of the ch
arge
pum
p a
nd
K
d
is the
gain of the bl
ock
(
I
p
/2
π
). The VCO is a
n
id
eal integrator with gain
K
V
, and the tra
n
sfer fu
nctio
n
of the LPF is
defined a
s
F
(s). In orde
r to reduce the chi
p
are
a
,
a passive t
h
ird
-
orde
r loop filter for the
freque
ncy sy
nthesi
z
e
r
is u
s
ed a
nd re
ali
z
ed by off-chi
p
comp
one
nts.
For the third
-
orde
r pa
ssive
loop filter, usually, C
3
<<C
1
, C
2
, the tr
ansfe
r functio
n
of the
filter is simplif
ied:
2
tot
a
l
1
3
1
1
()
(1
)
(
1
)
s
Fs
Cs
s
s
(2)
whe
r
e
tota
l
1
2
3
CC
C
C
,
2
1
2
1
2
1
C
C
C
C
R
,
2
2
2
C
R
,
3
3
3
C
R
.
The PLL op
e
n
-loo
p gain
H
0
(s
)
is
vp
2
o
2
to
t
a
l
1
3
1
()
2
π
(1
)
(
1
)
KI
s
Hs
N
Cs
s
s
(3)
The clo
s
e
d
-l
o
op tran
sfer fu
nction
H
(s
)
is
vp
2
ot
o
t
a
l
vp
2
v
p
43
2
o
13
1
3
to
ta
l
t
o
t
a
l
(1
)
()
2
π
()
1(
)
()
2
π
2
π
KI
s
NH
s
C
Hs
KI
KI
Hs
ss
s
s
NC
NC
(4)
For si
mplicity, we igno
re th
ese hi
gh term
s whi
c
h a
r
e smaller tha
n
lo
wer o
r
d
e
r terms. So
the simplified
se
con
d
-o
rd
er expressio
n
is
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 23
02-4
046
TELKOM
NIKA
Vol. 11, No. 2, Februa
ry 2013 : 754 – 760
756
vp
2
total
vp
2
v
p
2
to
ta
l
t
o
t
a
l
(1
)
2
π
()
2
π
2
π
KI
s
C
Hs
KI
KI
ss
NC
NC
(5)
Therefore, th
e dampin
g
factor an
d natu
r
al freq
uen
cy:
vp
2
tot
a
l
22
π
KI
NC
(6)
to
t
a
l
2
π
vp
n
KI
NC
(7)
For mo
st de
si
gn, the PLL locks in q
u
ickl
y and 0<
ζ
<1, hen
ce it is re
aso
nabl
e to state that
the lock-in ti
me is
L
n
2
π
T
(8)
The de
sign
of the LPF plays an im
p
o
rtant ro
l
e
to the stability of the loop
and the
perfo
rman
ce
of the lo
op trappin
g
an
d tracking.
Sui
T
able
paramet
ers of the
co
mpone
nts i
n
the
LPF not only redu
ce p
u
ll-in
and lock-i
n time, but also
i
m
prove the
stability of the l
oop. In orde
r
to
kee
p
the
sta
b
ility of the loop, the
pha
se m
a
rgi
n
(
φ
) is
usually l
a
rge
r
tha
n
4
5
°, the maxi
mum
pha
se ma
rgin
occurs a
r
o
u
nd the
cro
s
so
ver freq
uen
cy
, where the o
pen-l
oop
gain
is unity. The
n
the optimal lo
op ban
dwidt
h
(
f
n
) is equal t
o
the crossov
e
r freq
uen
cy for maximum
pha
se ma
rgin.
With the hel
p of the line
a
r mo
del, the simul
a
ti
on
of the loop
respon
se
a
nd the tra
n
si
ent
respon
se a
r
e
impleme
n
ted
in the ADS 2005. The opti
m
al loop pa
ra
meters are li
sted in Table 1
.
Table 1
．
Lo
o
p
Paramete
rs of The Freq
u
ency Synthesizer
K
v
(MHz
/V)
I
p
(mA)
f
re
f
(MHz
)
f
n
(k
Hz
)
φ
(°)
C
1
(p
F)
R
2
(k
Ω
)
C
2
(p
F)
R
3
(k
Ω
)
C
3
(p
F)
160 1
4
50
52
87
4.2
1450
2.8
38
Figure 3. Linear Mo
del for The CPLL T
y
pe
Freq
uen
cy Synthesi
z
er
Figure 4. Tra
n
sie
n
t Re
spo
n
se of VCO Control
Voltage
Based o
n
the
s
e Lo
op pa
ra
meters and (6), (7), the value of damp
i
ng factor a
n
d natural
freque
ncy
are 0.95
and
5
0
KHz, re
sp
e
c
tively. Base
d on
(8
), the
lock-i
n time
of the sy
ste
m
is
about 2
0
u
s
.
Figure 4
sh
o
w
s the tran
si
ent re
sp
on
se
of the VCO
control voltag
e in
clo
s
ed
lo
op
state
whe
n
th
e total
divisio
n
ratio of
the
down
sca
ling
ci
rcuit is
set
to 103
6. It ca
n be
seen
th
at
the cont
rol voltage of VCO cha
nge
d very small aft
e
r 20
μ
s, the PLL sho
u
ld
be in the locked
-
state. The ov
erall be
havio
r of the simul
a
tion
sh
ows
good a
g
re
em
ent with the desi
gn pri
n
ci
ple
and theo
retical analysi
s
.
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
2302-4
046
A Monolithic
0.18
μ
m
4GHz CM
OS Freq
uen
cy Synthe
sizer (Wu Xiu
s
ha
n)
757
4. Circuit de
sign of Freq
uenc
y
S
y
nthesizer
4.1. The desi
gn of VCO
Figure 5
sho
w
s
schem
atic views of th
e VCO.
Thi
s
circuit p
r
e
s
e
n
ted in thi
s
pape
r is
based o
n
the
negative tra
n
scon
du
ctan
ce L
C
oscillat
o
r [5, 6]. The
pro
p
o
s
ed V
C
O
con
s
i
s
ts
of a
LC-ta
n
k ci
rcuit and
a n
egative-con
d
u
ctan
ce
cro
s
s-cou
p
led
dif
f
erential
pair.
The
differe
ntial
transi
s
to
r p
a
irs g
ene
rate
th
e ne
gative re
sista
n
ces
to
compen
sate
th
e lo
sses of th
e L
C
-tan
k.
L
C
-
tank ci
rcuit
co
nsi
s
ts of
the
on-chip
differential
in
du
cto
r
, the
on
chi
p
MIM ca
pa
cito
rs an
d the
M
O
S
varacto
r
s. Th
e rel
a
tive si
zes
of Mn1
a
nd Mp
1
were
determined
by the DC v
a
lue of
LC-ta
n
k
whi
c
h wa
s se
t about half of voltage sup
p
ly s
ource. It
wa
s found th
at when Mn1
and Mn2 sh
are
the same (minimum) le
ngt
h, the size of Mp1 sh
ould b
e
three and f
our times a
s
l
a
rge a
s
Mn1
for
optimal pha
se-noi
se p
e
rfo
r
man
c
e [7]. PMOS varacto
r
s a
r
e used in inversi
on m
ode be
cau
s
e
of
the wide
cap
a
citor va
riatio
n that can b
e
obtained
with a low vari
ation of sou
r
ce to gate bi
as
voltage.
4.2. The desi
gn of the d
o
w
n
-
s
caled di
v
i
der
The first div
i
de-by
-4
circuit is the
m
o
st
critical a
nd
challe
ngi
ng
comp
are
to othe
r
building
blo
c
ks in the frequ
ency
synthe
si
zer. Fi
rs
t, the
divider o
pera
t
es at the hi
g
hest fre
que
ncy
and it mu
st st
ill function
s p
r
ope
rly un
der the proc
ess
and tem
perature va
riation.
Furthe
rmo
r
e,
it
must ge
nerate quad
ratu
re
outputs. At last, in our
p
r
o
posed a
r
chite
c
ture, the o
u
tput load of th
e
divide-by
-4
ci
rcuit
contain
s
not
only the
next st
ag
e
di
vider and
wi
ri
ng cap
a
cita
n
c
e but also
t
w
o
buffers fo
r u
p
and do
wn
mixers. Thi
s
mean
s the lo
ad ca
pa
citan
c
e will be ve
ry large, nea
rly
200fF in ou
r desi
gn.
Figure 5. Circuit Sche
mati
c of The VCO
Figure 6. Circuit Schemati
c
of The Latch
Voltage
The divid
e
-b
y-4 ci
rcuit co
nsi
s
ts
of two
di
vide-by-2 ca
scade
incl
uding
t
w
o D flip-flop
s
(DF
F
). An i
m
proved
D-latch is
used to
realize t
he
ma
ster/
s
lave
DF
F as sho
w
n i
n
Figu
re
6. It is
the source
-co
upled l
ogi
c (S
CL) with
tail current
sou
r
ce
.
Compl
e
men
t
ary
cro
s
s-co
upled pai
rs are
use
d
in
the
output p
a
rt
o
f
the latch. T
he lo
ad
of th
e outp
u
t pa
rt
is li
ghten
ed
to imp
r
ove t
h
e
operating
spe
ed. The
ope
rating spee
d o
f
the latch
i
s
prop
ortio
n
to the
ch
arge/di
scharge cu
rre
n
t,
and i
n
inve
rse propo
rtion
to si
gnal
swin
g amplitu
de.
We ca
n
in
cre
a
se
the refe
rence
voltag
e Vref
and tail cu
rre
n
t to improve the operating
spe
ed [8].
As
sho
w
n i
n
Figu
re
2, the d
ual-mod
ulus
(P/P+
1
) presc
a
ler is c
o
mbined
with two
prog
ram
m
abl
e cou
n
ters M and A, which are impl
emen
ted with stan
dard di
gital cells to reali
z
e
d
a
prog
ram
m
abl
e divide
ratio
of PM+A. T
h
e imple
m
ente
d
ci
rcuit of th
e DMP is
sho
w
n i
n
Fi
gure
7,
whi
c
h consi
s
t
s
of a divider-by-
4/5
synchron
ou
s co
u
n
ter, a divide
r-by-2 asyn
chron
o
u
s
co
u
n
ter
and divi
sion
model
cont
rol
(MC) ci
rcuit. Whe
n
divisi
o
n
model
co
ntrol input i
s
hig
h
, the pre
s
cal
e
r
divide ratio i
s
9, othe
rwi
s
e, the divid
e
ratio
i
s
8.
The divide
r-by-4/5
syn
c
hron
ou
s cou
n
ter
employs thre
e ma
ster-sl
a
ve SCF
D-flip
-flops a
nd two
OR
gate
s
. As sho
w
n in
Fi
gure
8, a n
o
vel
D-lat
c
h a
r
chit
ecture integrated with OR logic gat
e
s
is pre
s
e
n
ted i
n
this pape
r, DN a
nd DP are
the inp
u
ts
of t
he O
R
gate,
Vref is the
DC
refere
n
c
e v
o
ltage
pro
d
u
c
ed by th
e inte
rnal
bia
s
circuit.
The D-latch a
r
chite
c
tu
re int
egrate
d
with
OR logi
c gate
s
not only si
mplified the d
e
sig
n
step
s, but
also redu
ce
d
the para
s
itical par
am
eters of the singl
e logic gat
e t
o
assure the
high operating
spe
ed of the DMP.
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 23
02-4
046
TELKOM
NIKA
Vol. 11, No. 2, Februa
ry 2013 : 754 – 760
758
Figure 7. Block
Diag
ram o
f
The Dual
-
Modulu
s
Divi
der-by-8/9 Prescale
r
Figure 8. D-la
tch Architectu
re With O
R
In
put
4.3. The desi
gn of the PF
D and CP
Figure 9
sho
w
s the
sche
matic of th
e
pha
se/freq
ue
ncy d
e
tecto
r
. The PF
D
g
enerates
differential si
gnal
s by inverter and tra
n
sfer gate to
drive the CP [9]. This sequ
e
n
tial PFD ha
s a
monotoni
c p
h
a
se e
r
ror tran
sfer
(inde
pen
dent of t
he d
u
ty-cycle
). Th
e dead
-zon
e of the PFD can
be red
u
ced b
y
inserting inv
e
rters into the
res
e
t path to inc
r
eas
e
the res
e
t delay.
The ta
sk of
th
e cha
r
ge
pu
mp i
s
to
hol
d
prop
er
voltag
e level
to
con
t
ro
l the os
c
illator [10].
The charge p
u
mp, in gen
e
r
al, sh
ows no
nideal
cha
r
a
c
teristics
whe
n
implemente
d
in a circuit a
n
d
its practi
cal i
s
sue
s
ne
ed t
o
be
co
nsi
d
e
r
ed i
n
the
de
sign
of the P
LLs.
One
of the issu
es in
the
cha
r
ge
pum
p
desi
gn i
s
th
e cu
rrent mi
smat
ch. In this p
ape
r th
e effects
of the ph
ase offset
cau
s
e
d
by the cu
rre
nt mismatch a
r
e
co
nsid
er
e
d
an
d
a new
cha
r
ge pum
p ci
rcuit with nea
rl
y
perfe
ct curre
n
t matchi
ng i
s
p
r
opo
se
d.
Figure 10 i
s
t
he ci
rcuit dia
g
ram
of the d
i
fferential
cha
r
ge
pump b
a
sed
on the curren
t steerin
g techniqu
es
whi
c
h con
s
i
s
ts of
feed ba
ck
ci
rcuit a
nd ba
n
d
-
gap voltag
e
referen
c
e
circuit. Different
ial ch
arge p
u
mps p
r
ovid
e goo
d
reje
ction to com
m
on
mode noi
se o
r
interfe
r
en
ce
[11]. The feed back
ci
rcuit incre
a
ses th
e output dyn
a
mic-ra
nge a
n
d
cha
r
ge/di
sch
a
rge
symmet
r
y. Band-g
a
p
voltage refe
ren
c
e
circuit
improve
s
the
performan
ce
of
the cha
r
ge p
u
m
p [12].
Figure 9. Block di
agram of
The Dual
-
Modulu
s
Divi
der-by-8/9 Prescale
Figure10. Ci
rcuit Sche
mati
c of Cha
r
ge P
u
mp
5. Measurem
e
nt Results
For dem
on
stration, the pre
s
ente
d
CPLL
ty
pe frequen
cy synthesi
z
er
has b
een fab
r
icated
in SMIC’s
0.18µm CMOS
pro
c
e
ss. A
c
cording to th
e ISF theory
[13], the pha
se n
o
ise can
be
signifi
cantly reduced if
certain symmet
r
y propert
ies exist in the waveform of the oscillati
on
.
Thus,
the l
a
yout of the
VCO de
sig
n
m
u
st be
focused
on th
e full
sy
mmetry. The
PFD a
nd
do
wn
scaling
divide
r bel
ong to
d
y
namic l
ogic
circuit a
nd
a
r
e se
nsitive to
the pa
ra
sitic cap
a
cita
nce
o
f
the nod
e. Interconn
ectio
n
s
of tho
s
e
bui
lding bl
o
cks a
nd conn
ectio
n
s b
e
twe
en t
he FET
s
mu
st be
s
h
or
te
n
as
po
ss
ib
ly to
r
e
du
c
e
th
e
p
a
r
as
itic
c
apa
cita
nce. Buildin
g
blocks
of the PFD an
d d
o
wn
scaling
divid
e
r a
r
e
en
circled by
doubl
e gu
ard
-ri
ng
s to minimi
ze
su
bstrate n
o
ise
interfe
r
e
n
ce.
Furthe
rmo
r
e
they are de
signed in the
deep n-well
to This pap
er also puts forwa
r
d so
me
method
s, incl
uding de
sig
n
i
ng PFD and
down scaling
divider ci
rcuit in the deep n
-
well
sep
a
rati
ng
the an
alog
a
nd di
gital
su
pply, ch
oo
sin
g
ap
pro
p
ri
ate
filter
capa
cit
o
r a
nd
se
pa
rating the
an
a
l
o
g
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TEL
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and
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siz
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K
OM
NIKA
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M
Freq
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e
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p
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r
u
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lyz
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noi
se
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2
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cy at
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cy
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s
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vers
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idth
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bou
t
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n
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h
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cy
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nt
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re 13. Mea
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s
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re
ws, an
d t
B
.
M
icro
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e
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state. Fi
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kHz
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u
t
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e offset is
si
ze
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n
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wer
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m
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r
ed
Ph
as
e
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n
olith
i
c 0.18
μ
the inte
rfe
r
e
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e pads is
0
s
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ws a ph
o
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c
o
r
ap
h of The
e
si
zer
r
ed by
the
nt 8
610
0
A
o
q
ue
ncy at
4.
u
nde
r an
i
n
n
g ci
rcuit in
1
03
6. It ca
n
of the refe
r
e
e
15 sho
w
s
a
tion in th
e
l
o
refe
re
nc
e s
o
n
o
ise of t
h
e
d
B/d
e
c
a
de d
t
less than
s
larg
e than
s
n
ly caused b
m
ption of the
e
Noise of V
C
S
SN: 2302-4
0
μ
m 4
G
Hz
C
M
e
nc
e
be
tw
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te
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test
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o
scilloscope.
154G
Hz os
c
n
depe
nde
nt
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l
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e
d
lo
op
be see
n
tha
t
e
n
c
e sign
al.
T
s
a plot of
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o
cked state.
o
ur
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V
e
fre
quen
cy
ecre
asi
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everal M
H
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s
everal MH
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cor
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ci
rc
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C
O
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M
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ue
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u
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g
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t
D
31
86 sign
a
Figu
re
13
s
c
illation test
e
1.8V sup
p
l
y
state wh
en
t
the
freq
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n
T
his h
a
s
pr
o
t
he mea
s
ur
e
It can be
s
e
V
CO. Th
e p
h
synthe
sizer
ope, when t
h
The
ph
ase
z
(about 3
M
n
oise with
-2
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s
is ab
out 24
m
r
e 14. Wave
f
L
o
n
cy Synthe
s
g
circuit
an
d
u
re 11 s
h
o
w
B. The PC
B
w
ires
to the
t
ogra
ph of T
a
l gen
erat
or
s
ho
ws a
plo
t
e
d alone. Th
e
y
. Figure
14
the total di
n
c
y
of the
w
a
o
ved the fre
q
e
d pha
se
n
o
e
e
n
that the
p
h
ase noi
se
a
is
m
a
in
l
y
c
a
h
e offset i
s
l
a
no
is
e a
t
1
M
H
M
Hz
), the p
h
0
dB/decade
m
W un
der 1
f
orm of Dow
n
o
ck
ed State
s
izer (Wu Xi
u
di
gital circui
w
s a photo
o
B
is fixed on
mi
cro
s
t
r
i
p
s
he Test PC
B
, Agilent E
4
t
of the
me
a
e
pha
se noi
s
shows the
o
vision ratio
a
vef
o
r
m
is
e
q
ue
ncy synth
o
ise versus
p
h
a
se noi
se
a
t 10kHz of
f
a
u
s
ed by
th
e
a
rge than
th
e
H
z offs
et is
-
h
a
s
e noi
se
o
decrea
s
in
g
.
8
V supply.
n
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a
ler in
T
u
sha
n
)
759
t. The
o
f t
h
e
to the
at the
B
4
440A
a
sur
e
d
s
e at
1
o
utput
of the
q
ual
to
esi
z
er
of
fset
in l
o
w
f
set is
e
VC
O
e
loop
-
11
7.3
o
f the
sl
ope.
T
he
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TEL
K
760
6. C
o
SMI
C
frequ
desi
g
Ref
e
[1]
Y
J
[2]
J
W
R
[3]
V
C
[4]
M
E
[5]
H
a
[6]
D
s
3
[7]
Y
V
C
[8]
C
a
[9]
K
c
a
[10]
M
P
S
[11]
Y
4
[12]
F
s
[13]
H
1
K
OM
NIKA
V
Figure 15
.
o
nclusio
n
In this
p
a
C
0.18
μ
m te
c
en
c
y
p
l
an
o
f
g
n in this
pa
p
ren
ces
Y
ao-H
ong Li
u,
J
Solid-State
C
ae
w
o
ok Shi
n
,
W
ideb
and
Δ
∑
R
eg
ular Pa
pe
r
V
avel
idis K,
V
C
MO
S transc
e
M
.-S.H
w
a
ng,
E
lectronics Le
t
H
ani
l Le
e, Sa
e
a
pp
licati
ons.
I
E
D
on
gmin
Park
s
upp
l
y
. 20
06 I
3
23
6.
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oun
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o
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o
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-C
on
tr
o
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o
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C
hi B
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o
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a
n
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mi
c c
K
uo Hs
ing
C
h
c
harg
e
pum
p
a
a
nd System
s I
I
M
aciej Fra
n
ki
e
P
roceedings
o
S
ys
t
e
m
s
.
Gli
w
i
Y
. Chen, P.-I.
M
4
6(1
1
): 755-
7
5
F
ay
o
m
i
C
J B,
urve
y
.
A
nal
o
g
H
ajim
iri A, Le
e
99
8; 33(2): 1
7
V
ol. 11, No.
2
.
Measure
d
P
a
pe
r, a 4G
H
z
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hnol
ogy
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C
ircuit
s
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9;
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Hy
un
cho
l
S
h
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F
r
action
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N
rs
. 2010; 57(
7
)
V
assili
ou I,
G
e
i
v
er for 802.1
J.Kim, D.-K.
t
ter
s
. 2009; 4
5
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ed Mohamm
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EE Microwa
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on
g
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an
EEE Internati
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n, Yong-S
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lled
Oscill
at
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L
etter
s
. 2009;
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xue.
A
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rchitecture t
o
I
: Analog a
nd
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w
i
cz, Adam
G
o
f the 18th
I
ce. 2011; 1:
2
M
ak, Y. Z
hou
,
5
7.
Wirth G I, A
c
g
Integrated C
i
e
T
H. A gene
r
7
9-19
4.
2
, Februa
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P
ha
se Nois
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CP
PLL fre
h 1.8 V sup
p
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sc
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Li
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44(9):24
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in
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equ
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)
:157
3-15
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G
eorga
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,
1a/b/g w
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a
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. A subthr
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A
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Journa
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Yang,
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h
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o
a
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D
i
gital S
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o
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Self-tracking
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F
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n
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theor
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of
p
2013 : 754
–
e
of Frequ
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q
uen
cy syn
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ann
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s
an
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PLL-Bas
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n
d High-Pr
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ynthesiz
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etal. A dua
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IEEE
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o
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h
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r-optimi
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C
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on Circ
ui
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o
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Processin
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ased on th
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5.15–
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C
M
ts Letter
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0
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