TELKOM
NIKA
, Vol. 11, No. 9, September 20
13, pp.
5119
~51
2
5
ISSN: 2302-4
046
5119
Re
cei
v
ed
Jan
uary 18, 201
3
;
Revi
sed
Ju
n
e
4, 2013; Accepte
d
Ju
ne
17, 2013
Timed Behavioral Specification in Globally
Asynchronous Locally Synchronous systems
Yu Tonglan*
1
, Liu Jie
2
, Zhang Jua
n
3
, Wu Qujing
4
School of Co
mputer S
c
ien
c
e an
d Tech
n
o
logy, University of South Chin
a
Hen
g
Yang, HuNa
n, 4210
0
1
* e-mail:
Yton
glan
@16
3
.co
m
A
b
st
r
a
ct
In this pap
e
r
, we
pro
p
o
s
e a PolGAL
S l
angua
ge for
safety cri
t
ical
GALS
(Globall
y
Asyn
ch
ro
nou
s Lo
call
y Syn
c
hrono
us
)
system
s. The f
o
rm
al synta
x
and sem
antics
are
gi
ven a
n
d
its com
p
ilation a
nd im
pl
em
entation
are
define
d
. The l
ang
ua
ge i
s
ba
se
d
on tim
ed
CSP
(com
m
unicati
ng se
que
ntia
l pro
c
e
s
s) style re
nde
zvous b
e
twe
e
n
clock d
o
m
a
ins, aim
i
ng at
m
odelling the
tim
ed beha
vioral
of safety
critical
GA
LS system
s.
PolGALS is
use
d
to d
e
si
gn
tim
ed behavi
o
ral pattern to im
plem
ent
tim
i
ng require
m
ents, e.g. d
e
lay, tim
eout, deadline, timed
interrupt, etc. PolGALS provid
es a m
e
cha
n
ism
for im
plem
entation of tim
ed beha
vioral pattern
and pote
n
tial
for their fo
rm
al verifi
cat
i
on be
cau
s
e
it is base
d
on a PolG
ALS m
odel o
f
com
putation
and its form
al
sem
antics.
Key
w
ords
: P
o
lGALS lang
uage, Sem
a
n
t
ics, Synta
x
, Tim
ed beha
vi
oral, Glob
ally
Asyn
ch
ro
nou
s
Locally Synchron
ou
s syst
em
s
Copy
right
©
2013 Un
ive
r
sita
s Ah
mad
Dah
l
an
. All rig
h
t
s r
ese
rved
.
1. Introduc
tion
Safety critical
GALS syste
m
s
shoul
d ha
ve
highe
r reli
ability to ensure n
o
t to be
deploye
d
into applications
which ha
ve relatively rigid pe
rf
orm
ance req
u
ire
m
ents, su
ch
as traffic con
t
rol,
health
ca
re
a
nd a
u
tomotive safety syst
ems.
Fu
rthe
r, the
s
e
syst
ems mu
st be
strength
ene
d to
meet the re
que
st of stri
ngent fail-saf
e
relia
b
ility to avoid e
c
o
nomic,
huma
n
or
ecologi
cal
cata
strop
h
e
s
resulted in
by failure in th
o
s
e a
ppl
i
c
atio
ns. An imp
o
rt
ant f
eature of
these syste
m
s
is the ability to provid
e co
ntinual an
d timely re
spon
se to unp
redi
ctable ch
ang
e
s
of the state
of
the environm
ent [1][2]. Safety criti
c
al
GALS
syst
ems will not
be operated
in a controlled
environ
ment,
and
mu
st
be
rob
u
st to
unexp
e
cte
d
co
ndition
s and ada
ptabl
e
to su
bsy
s
tem
failures.
The
b
a
si
c pro
b
lem
of de
sig
n
ing safety critic
al GALS
system is the
unentirely p
r
e
d
ictabl
e
physi
cal worl
d. Time is a
n
importa
nt aspect of
sy
ste
m
spe
c
ification an
d
therefore spe
c
ification
langu
age
sup
port for time i
s
nee
ded. By deco
uplin
g the sp
ecifi
c
ati
on from impl
ementation
a
nd
usin
g formal
mathematical model
s of computat
io
n
for spe
c
ifica
t
ion,
GALS
systems can be
perfo
rmed
wi
th fast simul
a
tion and efficient sy
nthe
sis. The
com
p
lex
GALS systems can
be
modele
d
a
s
a hie
r
a
r
chical
co
mpo
s
ition
of the
sim
p
l
e
r m
odel
s
of co
mputatio
n
.
Some of
th
ese
simple
r mo
de
ls of computa
t
ion have finit
e
state, su
ch
as type
s of finite state ma
chin
es, d
a
taflow
model
s a
nd
synchrono
us/
r
eactive m
ode
ls. Th
us the
a
nalysi
s
of th
e
syste
m
can
be p
e
rfo
r
med
at
compil
e-time.
System dev
elop la
ngu
a
ges
are sui
t
able
for
co
mplex GAL
S
system
s,
gene
rally
con
s
id
ere
d
a
s
a set of co
mmuni
cating
pro
c
e
s
ses, which h
a
ve ha
rd re
al-time
con
s
trai
nts a
nd
comm
uni
cate
synch
r
on
ou
sly or asynchronou
sl
y. System develop l
angu
age
s ca
n be cla
ssifi
ed
into two se
parate type
s, formal and
inform
al. F
o
rmal la
ngu
age
s are ba
sed o
n
rig
o
rous
mathemati
c
al
foundation
s
,
such a
s
Est
e
rel, CR
P, SHIM and
CRSM [3][4][5],
whi
c
h a
r
e sui
t
able
for form
al ve
rification
and
com
p
ilation.
Informal la
n
guag
es
are
hard
e
r to
co
mpile an
d m
o
re
diffic
u
lt to be verified for lack
of formal s
e
manti
cs,
for exam
ple,
SystemC [6
]. However, t
h
e
System devel
op La
ngu
age
s, which
hid
e
s
detail
s
of time con
s
traint
s in th
e lan
g
uage, h
a
s fai
l
ed
becau
se n
o
widely u
s
e
d
l
angu
age
expresse
s timin
g
prop
ertie
s
. High
-level re
quire
ment
s
in
real-
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 23
02-4
046
TELKOM
NIKA
Vol. 11, No
. 9, September 201
3: 511
9 – 5125
5120
time system
s are often
stated in term
s
of deadlin
e, time out and timed interrupt.
The auth
o
rs'
opinio
n
is th
at the syste
m
-level
d
e
s
i
gn
in
g
la
ng
u
age
s
h
ou
ld
sp
ec
ify tim
e
con
s
trai
nt. A new
sp
ecifi
c
ation lan
gua
ge na
m
ed P
o
lGALS is propo
sed
whi
c
h provides hi
gher
reliability and
portability.
The paper is
org
anized as foll
ows: Section
2 gives motiv
a
tion PolGALS
prog
ram, hig
h
lighting the
main features of
the la
ngua
ge. Section 3 decrib
e
s the PolG
ALS
prog
ram
synt
ax. The fo
rm
al semanti
c
s
and M
o
C a
r
e
pre
s
ente
d
in
Section
4 a
n
d
the
com
p
ila
tion
pro
c
ed
ure is explaine
d i
n
Sectio
n 5.
Finally
, the
pape
r e
n
d
s
with
con
c
lu
sion
s a
nd fu
ture
r
e
sear
ch.
2. Motiv
a
tion and Rela
ted
Work
To figu
re
out
the
status of
the
curre
n
t time lan
gua
ge
s a
nd m
o
tivate the i
n
trod
u
c
tion
of
the ne
w lan
guag
e, the
comp
ari
s
o
n
of some
wel
l
-kn
o
wn ap
proache
s is
di
scusse
d in t
h
e
followin
g
. Many system l
e
vel langu
ag
es
sepa
ra
te
control an
d d
a
ta-d
riven co
mputation
s
a
nd
attempt to in
sert timin
g
fe
ature
s
into
system level
prog
ram
m
ing
langu
age
s.
Their
syntax
and
sema
ntics are more
suitab
le for desi
gni
ng digital ci
rcuits, but the timing de
script
ion of capa
cit
y
is
limited. Lee
summari
ze
d ti
ming featu
r
e
s
in p
r
og
ram
[7]. Much
ea
rli
e
r, Mo
dula
-
2
[8] gives
co
ntrol
over
sched
ul
e of co-routin
es,
which ma
ke
s it po
ss
ibl
e
f
o
r p
r
o
g
ra
m
m
er
s t
o
ex
e
r
c
i
se
som
e
c
o
a
r
se
control ove
r
t
i
ming. Th
e
synchro
nou
s
langu
age
s
h
a
ve no
explicit timing co
nstruct
s
, but th
eir
predi
ctabl
e a
nd repe
atabl
e app
ro
ac
h to co
ncurren
cy can yiel
d m
o
re
pre
d
icta
bl
e and
re
peat
able
timing than
m
o
st alte
rnativ
es [9], such a
s
Este
rel,
L
u
s
tre
and Si
gn
al, so th
at the
y
are limited
b
y
the unde
rlyin
g
platform. Ada ca
n not express ti
ming
con
s
traint
s. Real
-Time
Ja
va augment
s the
Java model
with a few ad-hoc f
eatures that reduce variability of
timing [10].
Real-tim
e Euclid
expre
s
ses p
r
oce
s
s peri
o
d
s
and a
b
sol
u
te start times [11]. Time C intro
duces exten
s
ion
s
to
spe
c
ify timing
requi
rem
ents based on
events, with
th
e
obje
c
tive of controllin
g cod
e
gen
eratio
n i
n
compil
ers to exploit instru
ction level pipe
lining
[12]. Ra
ther than ne
w langua
ge
s, an alternative i
s
to ann
otate
prog
ram
s
written in
con
v
entional la
n
guag
es.
Lee
gives taxo
nomy of tim
i
ng
prop
ertie
s
th
at must be e
x
pressibl
e in su
ch an
notati
ons [13]. Mu
nze
nbe
rge
r
g
i
ves ann
otations
for SDL to expre
ss
real
-tim
e con
s
trai
nts
[14].
That these langu
age
s se
parate
cont
rol and
data
-
driven comp
utations le
ad
s to low
adoptio
n rate
by Software
develop
er. New PolGALS
is de
sign
ed b
y
using a
syn
t
ax and de
sig
n
flow
simila
r
to gen
eral
p
u
rpo
s
e
p
r
og
ramming
lang
uage
s,
su
ch
as
Java
an
d
C++. Pol
G
A
L
S
extended Sy
stem
J [15] itself with
time
statement
s. PolGALS is
different from
SystemJ, which
can
sp
ecify
high-l
e
vel time req
u
iremen
ts for r
eal-ti
m
e su
ch
as
delay, dea
dline, time out, an
d
timed interru
p
t. Such tight integration o
f
cont
rol, dat
a-d
r
iven and
time operatio
ns re
du
ce
s the
sou
r
ce code
size and
provides a
mu
ch mo
re
p
o
w
erful
ab
stra
ction for
de
scribi
ng la
rge
and
compl
e
x mo
dels. PolGAL
S is desig
ne
d for a gen
eral pu
rp
ose
GALS and doe
s not target
towards
emb
edde
d sy
ste
m
s alo
ne, unl
ike ma
ny cu
rrent syste
m
-le
v
el langu
age
s. It is ca
pabl
e of
modelin
g mul
t
iple clo
ck
system
s, particularl
y tho
s
e can be mo
del
ed by a GAL
S
MoC, and
by
usin
g b
o
th p
u
re Syn
c
h
r
on
ous Rea
c
tive and
GALS
MOC. T
he
compilation
of
PolGALS ta
rgets
towards ge
ne
rating
efficien
t and p
o
rtabl
e co
de, in thi
s
case
Java
cod
e
, whi
c
h
can
be exe
c
u
t
ed
on different
computing
plat
forms.
With
Java as its
co
mpilation
re
sult, PolGALS is m
u
ch mo
re
portabl
e com
pare
d
to any
other curren
t system
lev
e
l langu
age.
The po
rtabil
i
ty of PolGALS
allows d
e
sig
ners to p
r
og
ram PolGALS
syst
em
s on
a de
skto
p
a
nd then
perf
o
rm
s autom
a
t
ed
deployme
nt on othe
r target arch
ite
c
ture
s, su
ch
as em
bed
de
d
system
s,
without ne
ed
for
recompil
ation.
3. PolGALS Langua
ge Sy
ntax
PolGALS not
only combi
n
es fe
ature
s
f
r
om Syste
m
J, timed CSP
[16] with th
e Java
prog
ram
m
ing
lang
uage,
bu
t also
combin
es th
e GALS
rea
c
tive mo
d
e
l of
comp
uta
t
ion of Syste
m
J
with timed CSP. Fig1 illustrates a
n
exa
m
ple of
PolG
ALS prog
ram
model with two cl
ock-dom
ain.
A PolGALS
prog
ram
con
s
ist
s
of a number of rea
c
tions, whi
c
h
follows the rules of
synchro
nou
s
rea
c
tive mod
e
l of comput
ation. Each
reactio
n
executes in lock-step with a logical
c
l
oc
k ca
lle
d "tic
k
"
in
th
e sa
me
c
l
ock
do
ma
in
.
Rea
c
t
i
ons exchan
g
e
an
d
synchronize by
usi
ng
CS
P
st
y
l
e re
nde
zv
ou
s bet
wee
n
clo
ck d
o
main
s.
Re
a
c
tion interact
s with its environm
ent thro
ugh
a set of input and output si
gnal
s and op
eration
s
on th
ese
signal
s. Every clock d
o
main
s sa
mp
les
inputs from t
he environm
ent, rea
c
ts to
these
in
puts instanta
neou
sly and p
r
o
d
u
ce
s the o
u
tputs
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
2302-4
046
Optim
i
zing Proce
s
s and
De
sign of Di
e wi
th CAE on the Car
(Su Ch
unjian
)
5121
back to
the
environme
n
t, thereby i
m
pleme
n
ti
ng
a
state
machi
ne. T
h
e syn
c
h
r
o
n
o
u
s,
asyn
chrono
u
s
, re
actio
n
s and
ope
ra
tions o
n
signal
s, clo
c
k-domain
s
an
d ch
ann
els and
statement
s are together
re
spo
n
si
ble for
t
he cont
rol-flo
w
of PolGAL
S program
s.
Figure 1. An example of PolGALS pro
g
ram model
PolGALS ke
rnel statem
ent
s co
nsi
s
t of sync
hro
nou
s,
asynchrono
us an
d time. Table 1
and II sho
w
the PolGALS
synchro
nou
s
and a
s
ynchro
nou
s ke
rn
el statements, which a
r
e
simil
a
r
with System
J [17]. Th
e
; operator m
a
ke
s t
w
o sy
nch
r
on
ou
s reactive
state
m
ents execu
t
e
seq
uentially. Abort and
su
spe
nd are b
a
se
d on sig
n
a
ls, while tra
p
is the sam
e
as Este
rel’
s
exceptio
n me
cha
n
ism.
Wo
rkin
g a
s
a wa
tchdo
g,
the a
bort statem
e
n
t preem
pts
a pro
g
ra
m if the
the watchdo
g’s si
gnal
status is
true
in any given
tick. The
r
e
are Seve
ral
kind
s of ab
ort
statement
s.
A wea
k
a
b
o
r
t stateme
n
t allows the
pro
g
ra
m to
finish a
si
ngle tick b
e
f
ore
pree
mpting. A strong ab
o
r
t immediatel
y terminat
es the program
when si
gnal
status is tru
e
.
These two
ki
nds
of abo
rt can
be furt
her
com
b
in
e
d
with an i
m
mediate
sign
al pre
d
icate. An
immediate ab
ort start
s
che
cki
ng the sig
nal from
the very first tick, while a non immediate ab
ort
alway
s
ch
ecks the si
gnal a
fter the first tick
has
pa
sse
d
. The susp
e
nd statem
ent
is simil
a
r to the
abort
statem
ent. The differen
c
e i
s
that the su
spe
nd
statement p
a
use
s
in the p
r
esen
ce of si
gnal
S instead of
preem
ption,
The trap st
atement is
a
control flo
w
base
d
pre
e
m
ption state
m
en
t
simila
r to th
ose fo
und i
n
mode
rn im
perative la
ng
uage
s li
ke
Java or
C++.
Whe
n
the
exit
statement i
s
execute
d
in t
he trap
body
, the pr
og
ra
m executio
n
terminate
s
i
mmediately.
The
while
statem
ent mean
s
a
n
infinite iteration st
ate
m
ent in PolGA
L
S pro
g
ra
m. The
synchro
nou
s
parall
e
l o
p
e
r
ator ||
run
s
t
w
o
or mo
re
rea
c
tion
s
co
ncu
r
rently. All re
action
s forked
by the
||
operator
sta
r
t and fini
sh
togethe
r. T
he
synch
r
o
n
ous statem
e
n
ts
con
s
ist of
the
jterm
(
p)
statement
s, whi
c
h are
u
s
ually use
d
f
o
r
d
a
ta-d
rive
n
computatio
ns. Data-driv
en comp
utation
provide
s
a m
u
ch m
o
re
po
werful
pro
g
ra
mming ab
straction b
e
cau
s
e it ca
n be f
r
eely mixed
with
reac
tive c
ont
rol flow.
As
sho
w
n
in
Table II ,the
asyn
chrono
u
s
stateme
n
ts re
pre
s
e
n
t th
e a
s
ynchro
no
us
MoC
impleme
n
ted
in PolGALS. Signals a
r
e b
a
si
c mean
s o
f
communi
cat
i
on whi
c
h h
a
v
e a status a
n
d
possibly a
va
lue in Pol
G
A
L
S pro
g
ram.
Signals can
be eithe
r
lo
cal or interfa
c
e qualifie
d
wi
th
either the i
n
put or the
o
u
tput. The first two
kernel
statement i
s
u
s
ed to d
e
cla
r
e
cha
n
n
e
ls,
inclu
d
ing the
output chan
nel to send
data ac
ro
ss
clo
c
k-do
main
s and the in
put chan
nel
to
receive data
from a
corre
s
po
ndin
g
inp
u
t port.
The
s
e output a
n
d
input po
rts
of cha
nnel
s
are
initialized
inte
rnally
at chan
nel d
e
cl
aratio
n. An
o
u
tput port
i
s
used b
y
the sen
d
statement
to
se
nd
data, while th
e input port is used by the receive
state
m
ent to recei
v
e data. The sen
d
and receive
statement
s a
r
e used to
sy
nch
r
oni
ze
an
d tran
sfer
dat
a over
ch
ann
els. Rend
ezv
ous i
n
PolGA
L
S
is cl
osely rel
a
ted to the
sched
uling o
f
cloc
k-dom
a
i
ns a
nd the
asyn
chrono
u
s
op
erato
r
(><).
PolGALS use
s
ren
d
e
z
vou
s
for synchro
n
i
z
ation b
e
twe
en se
ndin
g
a
nd re
ceiving
reactio
n
s.
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 23
02-4
046
TELKOM
NIKA
Vol. 11, No
. 9, September 201
3: 511
9 – 5125
5122
Table 1. Kern
el Statements and Thei
r De
scription
S
y
nchrono
us Ker
nel Statements
Description
;
pause
[output] [input] [t
ype] Signal S
emit S(exp
)
p1;p2
w
h
ile (
t
r
ue)
{
p
}
present (S)
{p1
}
else {p2}
[w
e
a
k] abort
([immediate] S) {p
}
[w
e
a
k] suspend (
[
immediate] S) {p
}
trap (
T
)
{p}
exit T
p1 || p2
Jterm(p)
j
t
ermp (p)=#s
j
t
ermp (p)=#c
dumm
y
stateme
n
t
dumm
y
stateme
n
t
signal declaration
signal emission
sequential statement
infinite loop
conditional statement
preempt watchdo
g
halt w
a
tchd
og
trap e
x
ception m
e
chanism
exit from t
r
ap
parallel statement
Java data-driven
obtaining a signal value
obtaining a chan
nel
Table 2. Asyn
chrono
us Ke
rnel St
atemen
ts and Th
eir
De
scription
Asy
n
ch
ronous K
e
rnel Statements
Description
Output [t
ype] cha
nnel C
Input [t
y
p
e] chan
nel C
p1><p2
send C ([e
x
p])
Receive C( )
sending channel declaration
receiving channel declaration
asynchronous pa
rallel
send data on cha
nnel
Receive data on
channel
The time
stat
ements are shown in tabl
e
3. T
he
wait[d] is rea
c
tion
p1 wait for e
x
actly d
time units
. The p1 timeout[d] p2 is
us
ed
to dec
lare
th
e
first ob
se
rva
b
le event
of reactio
n
p1
sh
all
occur
before
d time units e
l
apse,
sin
c
e t
he process st
arts. Othe
rw
ise, the re
acti
on p2 ta
kes
o
v
er
control after
exactly d tim
e
units elap
se. The
p
1
int
e
rrupt[d] p2
p
r
esent rea
c
tion p1 i
n
terru
p
ted
rea
c
tion p2 b
ehave
s
exactl
y as p1 until d time uni
ts e
l
apse, and th
en p2 takes o
v
er cont
rol. The
p1 dea
dline[d
]
const
r
ain
s
p
1
to terminate
before d time
units.
Table 3. Time
Kernel Statements an
d Th
eir De
scri
ptio
n Asynch
ro
no
us
Time kernel state
m
ents
Description
w
a
it[d]
p1 timeout[d] p2
p1 interrupt[
d
] p2
p1 deadline[d] p2
dela
y
timeout
interrupt
Deadline
4. PolGALS Langua
ge Semantics
Semantic rul
e
s
simila
r to
Esterel
and
SystemJ
are
use
d
for de
scribi
ng Pol
G
ALS time
statement
se
mantics. Giv
en p
an
d a
n
input
event
E, the b
e
h
a
vioral
se
ma
ntics e
s
senti
a
lly
descri
b
e
s
wh
at hap
pen
s i
n
a
singl
e rea
c
tion of the
m
odule
for th
e
given in
put e
v
ent. The thin
gs
that can ha
pp
en are emissi
on of
sign
als
and control flow from
one
set of point
s to anothe
r. Th
is
is ca
pture
d
by a mathematical relati
on, calle
d the transitio
n relation,which
is descri
b
e
d
as
following s
e
mantic
rule :
'
,
'
data
,
p
,
,
,
K
data
p
E
t
e
.
The rule re
prese
n
ts
th
e
a
n
tece
dent an
d
con
s
equ
ent
state
s
of
p, resp
ectively,
durin
g a
micro-step transitio
n. p a
nd p'
a
r
e th
e stateme
n
t before
and
a
fter the re
act
i
on. Term
da
ta
rep
r
e
s
ent
s th
e state val
ue
whi
c
h
rela
ted
with
p
befo
r
e tran
sition
a
nd data
'
represe
n
ts th
at after
transitio
n. Th
e variable va
lue can b
e
o
m
itted
if p can be executing pur
e cont
rol statem
ent
s
.
Term E p
r
e
s
ents in
put ev
ent whi
c
h i
s
the statu
s
se
t of all the si
gnal
s u
s
ed i
n
rea
c
tion
p,
but
decl
a
re
d
som
e
wh
ere
else. The a
r
ray in
dexing n
o
tation to refer to
sign
al
statuses i
s
utili
zed
in
the event
set
E. Term
e re
pre
s
ent
s the
sign
als em
itted d
u
rin
g
tra
n
sition
and
if
none
are emi
tted
then it ta
ke
s
the value
of
⊥
. Term
K repre
s
e
n
ts th
e termi
nation
co
de.
Whe
n
p i
s
cap
able
of
gene
rate a te
rminatio
n , K is an inte
ger
value. Thre
e
terms
ca
n do
it. Term ; is encode
d with
0,
pau
se
with 1,
and exit T with an intege
r greate
r
tha
n
or eq
ual to 2.
If a signal
d
epen
den
cy h
a
s
not yet been
resolve
d
. synch
r
on
ou
s p
a
rallel
rea
c
tion ca
n pro
d
u
ce a termin
ation co
de o
f
∞
.
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
2302-4
046
Optim
i
zing Proce
s
s and
De
sign of Di
e wi
th CAE on the Car
(Su Ch
unjian
)
5123
Beside
s the
a
bove m
ention
ed te
rms,
K
has a val
ue
o
f
⊥
i.e., un
kn
own,
whi
c
h
m
ean
s p
do
es
not
gene
rate a t
e
rmin
ation code after thi
s
tran
sition.
Term t de
not
es a tran
sitio
n
of t time units
elap
sing. In the followi
ng
rules,
we p
r
e
s
ent the
firing
one
s which
a
r
e a
s
soci
ated
with the time
d
statement.
(1) The wait[d] of s
e
mantic
rule as
:
(I) if
t
≤
d
then
'
],
[
data
],
[
ait
,
,
,
K
data
t
d
Wait
d
W
E
t
e
This expresses th
at the
p
r
oce
s
s m
a
y b
e
idle
for any
amount
of tim
e
when
it i
s
l
e
ss tha
n
or equ
al to d time units.
(II) if
t
≤
d
then
'
,
data
],
0
[
ait
,
,
,
K
data
skip
W
E
t
e
This exp
r
e
s
ses that the proce
s
s termin
ates imme
dia
t
ely after d become
s
0.
(2) The timeout[d] of s
e
mantic
rule as
:
(I) if e output by p1 then
'
,
'
1
data
],
[
timeout
p1
,
,
,
K
data
p
d
E
t
e
This exp
r
e
sses that if an
output event
e ca
n be
eng
aged
by p1, then p
1
timeo
u
t[d] p2
become
s
p1'.
(II) if t < d
then
'
,
2
]
[
timeout
'
1
data
,
2
]
[
timeout
p1
,
,
,
K
data
p
t
d
p
p
d
E
t
e
This
expre
sses th
at if p
1
may
idl
e
for less th
an
or equ
al to
d t
i
me u
n
its,
so
is th
e
composition.
(III) if
t=d then
'
,
2
data
,
2
]
0
[
timeout
p1
,
,
,
K
data
p
p
E
t
e
This exp
r
e
s
ses that wh
en
d become
s
0, p2 ta
ke
s ove
r
cont
rol by a silent tran
sitio
n
.
(3) T
he interrupt[d] of sem
antic rul
e
as:
(I) if t<d then
'
,
2
]
[
interrupt
1
data
,
2
]
d
[
interrput
p1
,
,
,
K
data
p
t
d
p
p
E
t
e
This exp
r
e
s
ses that if P engage
s in eve
n
t x
, P interrupt[d]Q beco
m
es P0 interrupt[d]Q.
(II) if t=d then
'
,
2
data
,
2
]
0
[
interrput
p1
,
,
,
K
data
p
p
E
t
e
This exp
r
e
s
ses that if P
may idle for less
than o
r
equal to d time units, so
is the
comp
ositio
n. Whe
n
d time units ela
p
se, Q take
s over
by a transitio
n.
(4) T
he dea
dl
ine[d] of sem
antic rul
e
as:
(I) if t
≤
d the
n
'
,
'
1
data
,
]
0
[
deadline
p1
,
,
,
K
data
p
Q
E
t
e
Intuitively, th
ese
rul
e
s ex
pre
s
s that p
deadli
ne[d] b
ehave
s
exa
c
tly as p
exce
pt that it
must termi
nat
e before d tim
e
units.
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 23
02-4
046
TELKOM
NIKA
Vol. 11, No
. 9, September 201
3: 511
9 – 5125
5124
5. Compile into Jav
a
The ba
sic
te
chn
o
logy of PolGALS co
mpiler
is
the
GRC co
mpil
er app
roa
c
h
use
d
to
compil
e SystemJ [17] an
d Esterl [18], which co
n
s
i
s
ts of the st
ructu
r
al info
rmation and t
h
e
operational.
The
stru
ctura
l
informatio
n i
s
p
r
e
s
er
ve
d
by the hie
r
archi
c
al
state g
r
aph
(HSG) ,
and
the operation
a
l is explicitly rep
r
e
s
ente
d
by the control
flow grap
h (CFG
).
The HS
G in
clude
s four
different types
of node
s
call
ed thre
ad n
o
des, p
a
rall
el
node
s,
comp
oun
d n
o
des
and
bou
ndary
nod
es.
It outlines th
e structu
r
e
of the syn
c
h
r
on
ous
re
actio
n
s in
terms of state
m
ents an
d thread
s of
control. Threa
d
no
des a
b
stract t
he se
que
ntial compo
s
ition
of
basi
c
in
struct
ion in
side
a
particula
r thread a
nd
p
a
rallel no
de
s repre
s
e
n
t con
c
urre
nt thre
a
d
s.
Mean
while, l
oop
s, ab
orts and
othe
r b
a
ck trac
king
statement
s a
r
e rep
r
e
s
ente
d
by comp
ou
nd
node
s and p
auses a
r
e re
pre
s
ente
d
by bound
ary n
ode
s. The n
u
mbe
r
of bra
n
ch
es exten
d
ing
from a thre
ad
node indi
cat
e
s the num
be
r
of possible
states of that thread.
The CF
G co
nsi
s
ts of syn
c
hrono
us
an
d asyn
ch
ron
ous n
ode
s
which a
r
e u
s
e
d
for the
cod
e
g
ene
ra
tion sta
ge.
There a
r
e
seven type
s
of syn
c
h
r
on
o
u
s
nod
es.
T
he a
c
tion
no
des
rep
r
e
s
ent sig
nal
emi
s
sion,
enter nod
es state
en
co
din
g
. On the
oth
e
r h
and, te
st
node
s
rep
r
e
s
en
t
sign
al tests a
nd switch no
des indi
cate
state
sel
e
ctio
n. The fork n
ode
s and joi
n
node
s defi
ne
con
c
u
r
ren
c
y. Terminate
n
ode
s mark the com
p
letio
n
cod
e
of a given threa
d
. The se
quen
tial
statement
s are en
co
ded
usin
g action
node
s, whi
c
h
are com
p
let
e
ly ignore
d
in the HSG. The
asyn
chrono
u
s
nod
es a
r
e t
w
o types. Th
e a-fork n
ode
s and
a-joi
n
node
s exp
r
ess asyn
ch
ro
no
us
c
o
nc
ur
re
nc
y r
e
s
p
e
c
tive
ly.
The AG
RC i
n
terme
d
iate
format is we
ll
suited fo
r system
J la
ngua
ge
s, i.e., GALS
prog
ram
s
. B
u
t it can
not
expre
s
s timed b
ehavi
o
r
cha
r
a
c
teri
stic. Th
e A
G
RC form
at is
insuffi
cient
,
t
here
b
y AGRC furthe
r e
n
h
ances
GALS
with timed b
e
havior
cou
p
li
ng. So we
a
d
d
new types n
o
des in orde
r to make the n
e
w co
mpile
r suitabl
e for compiling time
d MoC, whi
c
h is
calle
d TAG
RC. T
he ti
mer
nod
es rep
r
e
s
e
n
t
time co
nsu
m
ption. Th
e
re
sulted
T
i
med
Asynch
ro
nou
s GRa
ph Co
de (TAG
RC) format derive
d
dire
ctly from PolGALS sema
ntics is the
interme
d
iate
rep
r
e
s
entatio
n whi
c
h Pol
G
ALS is tran
slated into b
e
fore bei
ng tran
slated into
low
lev
e
l Jav
a
ba
ck
-en
d
co
de.
The
whol
e p
r
oce
s
s of
com
p
iling Pol
G
AL
S into Java code i
s
divid
e
d
into fou
r
p
h
a
se
s
as
s
h
ow
n
in
F
i
gu
r
e
2
.
(1) Ab
stra
ct
syntax tree
gene
ration:
synt
actic a
nalysi
s
and error che
c
k
inclu
d
e
s
syntacti
c erro
r and fro
n
t-en
d error a
r
e pe
rforme
d in this stag
e.
(2) F
o
rm
at transl
a
tion: Po
lGALS pro
g
ram is tra
n
sl
a
t
ed into the TAGRC form
at. The
stru
ctural tran
slation
rule
s
are follo
we
d to tran
sl
ate e
a
c
h
statement
into one
or m
u
ltiple no
des
of
TAGRC.
(3) B
a
ck-end
cod
e
G
ene
ration: The
ba
ckend
co
de
gene
ration
st
age i
s
carrie
d out o
n
the resulting
AGRC.
(4) T
he code
optimizatio
n: some
well
-kn
o
wn
al
gorith
m
s like
red
u
n
dan
cy elimina
t
ion and
informatio
n propag
ation are
used in thi
s
impleme
n
t sta
ge.
Figure 2. Co
mpiling PolG
ALS
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
2302-4
046
Optim
i
zing Proce
s
s and
De
sign of Di
e wi
th CAE on the Car
(Su Ch
unjian
)
5125
6. Conclusio
n
PolGALS la
n
guag
e b
a
sed
on
the
GAL
S
of comp
utation
com
b
in
es th
e a
s
yn
chron
o
u
s
feature
s
of System J with
timed behavior of
timed CSP and dat
a comp
utatio
n capa
bilities o
f
Java.
We
m
a
ke
a
detaile
d de
scri
ption
of Mo
C of
PolGALS la
n
guag
e, a
s
well a
s
the
ti
med
behavio
r
se
mantics
of the la
ngu
age,
whi
c
h
a
r
e
suited
for co
mpiler con
s
truction. P
o
lG
ALS
langu
age uti
lize
s
timer
for time co
nsumi
ng b
e
twee
n coupl
ed re
actio
n
s. The Time
d
Asynch
ro
nou
s Graph
Co
de (TAG
RC) format is then propo
se
d whi
c
h is
better suited
for
PolGALS lan
guag
e sin
c
e i
t
is base
d
on
a set of fo
rm
al sema
ntics,
and thus i
s
p
o
tentially easi
e
r
to be ve
rified
. The
TAG
R
C
com
p
iler provides better pe
rform
a
n
c
e
in o
u
r be
nch
m
ark te
sts a
nd
different exe
c
ution pl
atforms, whi
c
h in
turn pr
ovid
e
s
direct supp
ort for the a
c
tive and tim
e
d
behavio
r stat
ements
within
PolGALS languag
e.
Curre
n
tly, PolGALS timed beh
avior model of computatio
n is difficul
t
to be
verify
becau
se it ope
ns a
wide
variety o
f
verifi
cation
and
optimization te
chniq
u
e
s
availa
ble i
n
the
prog
ram
mo
deling
dom
ai
n. A Furth
e
r study
on ve
rification
tech
nique
s a
bout
timed b
eha
vior
model ne
ed
s to be ca
rrie
d
on in the future work.
Ackn
o
w
l
e
dg
ements
This work is partially sup
ported by th
e proje
c
ts fu
nded by Sci
ence and te
chn
o
logy
proje
c
t of
Hu
nan P
r
ovin
ce
(G
rant
No.
2
011GK3
192
),
Key proje
c
t
of Hu
nan
Pro
v
ince
scientifi
c
resea
r
ch of college
s and
Universitie
s
(G
rant No. 11A
105 ).
Referen
ces
[1]
Junsu
o
, QU. Des
i
gn
of
T
i
me S
y
nc
hro
n
izati
on M
e
th
od for
R
eal-
T
ime EPON.
TE
L
K
OM
N
I
KA
Indon
esi
an Jou
r
nal of Electric
al Eng
i
ne
eri
n
g
.
2013; 1
1
(7):
[2]
Qing-Qua
n
Liu
.
Coordin
a
ted
Motion Co
ntrol
of Autonomo
u
s and Semi
a
u
tonom
ous Mo
bile Ag
ents
.
T
E
LKOMNIKA Indon
esi
an Jou
r
nal of Electric
al Eng
i
ne
eri
ng.
2012; 1
0
(8):19
29-1
935.
[3] Berry
G.
T
he Esterel v5 la
ng
u
age pr
i
m
er ver
s
ion 5
_
9
. Ecol
e des Min
e
s de
Paris, CMA, INRIA. 2000.
[4] Ramesh
S.
Commu
n
icati
ng r
eactive state
machi
nes: desi
g
n, mod
e
l a
nd i
m
p
l
e
m
e
n
tatio
n
.
Proceedi
ngs
of the IF
AC Worksho
p
on d
i
stribute
d
comput
er
control s
y
ste
m
s. Pergam
on
Press. 1998; 9:
105-
110.
[5]
T
a
rdieu O, Edw
a
rds
SA.
Sch
edu
lin
g-in
de
pe
nde
nt thre
ads
and
exce
ptio
ns
in
SHIM.
Proc
eed
ings
of th
e
6th ACM and I
EEE internati
o
nal co
nfere
n
ce
on embe
dd
ed
soft
w
a
r
e
. Ne
w
Y
ork, NY. 2006
: 142–1
51.
[6]
Grötker T
,
Liao S, Marti
n
G,
et al.
Syst
e
m
desi
gn w
i
th
Sy
stemC.
Kluwer
Academ
ic
Publishers
, USA,
200
2.
[7]
Ed
w
a
r
d
A Lee.
Computi
ng n
e
eds time
.Co
m
mu
nic
a
tions of
the ACM
. 200
9
;
52(5): 70-79.
[8]
Wirth N, Gries
D.
Pro
g
r
amm
i
ng
i
n
Mo
du
l
a
-2
. Sprin
ger-Ver
la
g,
Ne
w
Y
o
rk. 1
983.
[9]
Benveniste A, Berry
G.
The synchro
nous a
p
p
roac
h to reac
tive an
d real-ti
m
e syste
m
s.
Procee
din
g
s of
the IEEE. 1991
; 79(9): 127
0-1
282.
[10]
Burns A, W
e
lli
ngs A.
Real-T
i
m
e Syste
m
s a
nd Progr
a
m
mi
ng La
ng
uag
es:
Ada 95, Re
al-
T
ime Jav
a
an
d
Real-Time POSIX.
Addison
W
e
sle
y
, 3
d
ed
i
t
ion. 200
1.
[1
1
]
Kl
i
n
ge
rma
n E, Stoy
e
n
k
o
AD
. R
e
al
-ti
m
e
Eu
cl
i
d
: A
l
a
ng
ua
ge
fo
r rel
i
a
b
l
e
re
a
l
-ti
m
e sy
stems.
Softw
are
Engi
neer
in
g, IEEE Transacti
ons.
198
6; 12(
9):941-
94
9.
[12]
Leun
g A, Pa
l
e
m KV, Pnu
e
li
A.
T
i
me
C: A
time c
onstra
i
nt
lan
g
u
age
for
ILP process
o
r
compil
atio
n
.
T
e
chnical Re
p
o
rt
T
R
1998-
76
4. Ne
w
York U
n
iversit
y
. 19
98.
[13]
Lee I, Davids
on S, W
o
lfe V.
Motivating ti
me as a first class entity
.
T
e
chnical Report MS-CIS-87-54.
Univers
i
t
y
of Penns
yl
van
i
a Au
g. 1987.
[14] Münze
nber
ger
R,
Dörfel
M, Hofmann R, et al
. A general tim
e
m
ode
l for the
specificati
on a
nd des
ig
n of
embe
dde
d rea
l
-time s
y
stems.
Microel
ectron
ic
s Journa
l
. 200
3; 34(11): 9
89-
100
0.
[15]
Malik A, Salcic
Z
,
Roop PS, et al. S
y
st
emJ:
A GALS Lang
uag
e for S
y
ste
m
Level D
e
si
g
n
,
Co
mput
e
r
Lan
gu
ages. Sy
stems a
nd Stru
ctures.
2010; 3
6
(4): 317-
34
4.
[16] Rosco
e
AW
.
Understa
ndi
ng c
oncurr
ent systems
. Spri
ng
erv
e
rla
g
Lon
do
n L
i
mited. 20
10.
[17]
Malik A.
Princi
pia L
i
ng
ua Sys
t
emJ
. PhD the
s
is,
T
he Univer
sit
y
of Auckl
an
d Ne
w
Z
e
a
l
an
d
.
2010.
[18] Potop-Butuc
a
r
u
D.
Optimisa
tions for faste
r
executi
on of
esterel pr
ogr
ams.
PhD
th
esi
s
, Eco
l
ed
es
Mines
de Paris.
2002.
Evaluation Warning : The document was created with Spire.PDF for Python.