TELKOM
NIKA Indonesia
n
Journal of
Electrical En
gineering
Vol.12, No.7, July 201
4, pp
. 5191 ~ 51
9
6
DOI: 10.115
9
1
/telkomni
ka.
v
12i7.520
9
5191
Re
cei
v
ed
No
vem
ber 2
6
, 2013; Re
vi
sed
March 19, 20
14; Accepted
April 3, 2014
Digital Image S
t
orage System Based on USB and NAND
Flash
Yongjun Cui
*
1
, Wei Liu
2
1
Nationa
l Ke
y
Lab
orator
y for Electron
ic Mea
s
ureme
n
t and
T
e
chnolog
y, N
o
rth Univ
ersit
y
of Chin
a,
T
a
iyua
n 03
005
1, Chin
a
2
Ke
y
La
borat
o
r
y
of Instrumen
t
ation Scie
nce
and D
y
n
a
mi
c Measur
ement of
Ministr
y
of E
ducati
on, North
Univers
i
t
y
of
Chin
a,
T
a
iyua
n 03
005
1, Chin
a
*Corres
p
o
n
id
n
g
author, e-ma
i
l
: Cui2
34@
16
3
.
com
1
, liu
w
e
i
0
6
65@
163.com
2
A
b
st
r
a
ct
Focusin
g
on th
e storage of lar
ge nu
mber of digi
tal i
m
ag
e informatio
n
, a system
is des
ign
e
d
w
h
ic
h
base
d
on
USB
bus
a
n
d
NAN
D
-type F
L
AS
H
usi
n
g
alter
nati
ng tw
o-pl
an
e
pag
e
progr
a
m
. T
he
ai
m of th
i
s
study is to s
hor
t the w
r
iting-re
adi
ng F
L
AS
H ti
me
an
d
i
m
prov
e the tra
n
s
m
is
sion
of data
in
order to
en
ha
n
c
e
the efficiency
o
f
the system. In hardw
are i
m
p
l
ementati
on, th
e pap
er intro
d
u
c
ed the int
e
rfa
c
e betw
een ev
ery
mo
du
le esp
e
ci
ally the USB
conn
ectio
n
. In softw
are,
detaile
d an
alysis
of the key techno
logy a
b
o
u
t th
e
altern
ating
tw
o-pla
ne
pag
e
pr
ogra
m
w
a
s s
h
o
w
n. By commis
s
ioni
ng, th
e sp
eed
of d
a
ta sto
r
ed i
n
th
e F
L
A
S
H
is 3
0
MB/s, ach
i
evin
g fast
dat
a stora
ge
an
d
accurate
fee
d
b
a
ck p
u
rpos
es,
mak
i
n
g
sur
e
th
at the
data
w
a
s
relia
bl
e.
Ke
y
w
ords
:
US
B, transmissi
o
n
, storage, F
L
ASH, alternati
n
g tw
o-plane
pa
ge pro
g
ra
m
Copy
right
©
2014 In
stitu
t
e o
f
Ad
van
ced
En
g
i
n
eerin
g and
Scien
ce. All
rig
h
t
s reser
ve
d
.
1. Introduc
tion
No
wad
a
ys m
easure
m
ent
and
contral tech
nolo
g
y ha
ve grately ch
ange
d ou
r so
ciety. In
many are
a
s
su
ch a
s
indu
stry, aero
s
p
a
c
e,
we m
e
a
s
ure
whethe
r the dev
ices can
wo
rk stabl
e
or
not accordin
g to the feedback data. In t
hese mea
s
urem
ents, co
untless data
wa
s got
so the
stora
ge
spee
d is critical to
effencien
c
y of t
he system
. In aerospa
ce, some e
qui
pments
need
to
colle
ct hug
e numbe
r of di
gital image in
formati
on, an
d the data tra
n
smi
ssi
on be
tween them
a
nd
grou
nd te
st ben
che
s
req
u
ire a
high t
r
an
sfer
rate
[1-3]. The a
c
curacy of d
a
t
a transmissi
o
n
influen
ce
s the pre
c
isi
on of
the system [4].
Re
cently, the data wa
s p
r
o
posed to be t
r
an
sm
itted in
high-sp
eed
a
nd long
-di
s
ta
nce. It’s
high time fo
r
us to find
ne
w way to ach
i
eve the
re
qui
reme
nts. At present, the p
h
ysical interf
ace
unabl
e to m
e
et the
requi
re
d data
tran
sf
er
rate. T
he
commonly
use
d
RS
-42
2
int
e
rface,
whic
h
the
maximum tra
n
smi
ssi
on
sp
eed of t
w
iste
d is
1Mb/
s in
per one
hu
n
d
red
mete
r [5
, 6]. Speed a
nd
distan
ce li
ke this can not m
eet
these tran
smissio
n
re
q
u
irem
ents.
In this p
ape
r, a ne
w
syst
em was
de
si
gned
to
mee
t
the high
-sp
eed, lon
g
-distance
transmissio
n and a
c
curate
stora
ge of the digital im
age informati
on. The
s
e re
quire
ment
s were
achi
eved u
s
i
ng USB interface, LVDS tech
nol
o
g
y and NAND-type
FLASH for alternatin
g two-
plane
pa
ge
p
r
og
ram.
USB
has many
fea
t
ures li
ke
fa
st
er sp
eed, hot
-swap
pabl
e, and
it ha
s
b
e
e
n
widely
used i
n
vario
u
s dev
ice
s
[7, 8].
L
V
DS technol
ogy provide
s
a solution
to f
a
st lo
ng-dista
n
ce
transmissio
n. For NAND-ty
pe FLASH K9
WBG0
8U1
M
, using the me
thod of altern
ating two-pla
ne
page
prog
ra
m, data
ca
n b
e
sto
r
ed
qui
ckly. USB
te
ch
nology com
b
i
ned with alternating
t
w
o-pl
ane
page
progra
m
achieve
s
t
he p
u
rp
os
e o
f
fast data t
r
a
n
smi
ssi
on,
storag
e a
nd
accurate fee
d
b
a
ck
[9, 10]. This method
pro
v
ides a
ne
w app
roa
c
h to
the tran
smi
ssi
on a
nd
st
orag
e of a
l
a
rge
numbe
r of image
s.
2. O
v
erall S
y
stem Design
The de
sig
n
is based on
USB technol
og
y and
alterna
t
ing two-plan
e pag
e program. The
system u
s
e
s
a modular
desi
gn app
ro
ach, that’s
t
o
say variou
s com
pon
ent
s are di
stin
ct in
comp
ositio
n
but functio
nal
ly compl
e
me
nt. The g
r
eat
bre
a
kth
r
ou
g
h
s in
the d
e
sign a
r
e a
c
cu
rate
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 23
02-4
046
TELKOM
NI
KA
Vol. 12, No. 7, July 201
4: 5191 – 51
96
5192
and fa
st dat
a storage
a
nd high
-spe
ed tran
smi
ssion. They a
r
e the bottle
necks trou
bl
e
d
acq
u
isitio
n system techn
o
logy devel
o
p
ment. Da
ta
acqui
sition and storage
system
i
n
cl
u
des
FPGA maste
r
interfa
c
e m
odule, USB
comm
uni
ca
ti
on
interfa
c
e and
timing control
d
e
si
gn
of
read
-write op
eration, logi
c
desi
gn of one
pair of parall
e
l FLASH.
Figure 1
sh
ows digital i
m
age a
c
q
u
isition
and
sto
r
age
syste
m
work flo
w
. Specific
operational
p
r
ocedu
re
s: a
video or
a compl
e
te pi
cture is
divide
d into a con
t
inuou
s pictu
r
e
frame
s
. USB
chip
FT2
45
RL m
a
kes the pi
ctur
e transmitted
to
the a
c
qui
sit
i
on an
d
storage
system.
Und
e
r the
cont
rol
of FPGA, the do
wnlo
a
d
data are sto
r
ed in two pa
rallel FLASH
chip
K9WBG0
8U1
M
medium.
Whe
n
the im
age n
eed
s to
be
se
nt, the three g
r
o
ups
of data sto
r
e
d
in
the FLASH
woul
d be fa
st read
out. T
h
rou
gh the
MAX9247, 1
6
-bit p
a
rall
el
data would
b
e
into
seri
al data an
d be se
nt as
the LVDS mo
dule to
the im
age sto
r
e an
d tran
sfer de
vice. One g
r
o
up
of the three
woul
d be
st
o
r
ed i
n
the
im
age
stor
e a
n
d
tran
sfe
r
d
e
v
ice .Anothe
r way
wo
uld
be
transmitted to downst
r
ea
m equipm
ent
s in PCM
co
de for them t
o
be obtai
ne
d. The third
way
woul
d be re
a
d
-ba
c
k to the host compute
r
simila
rly in PCM co
de.
Figure 1. Digi
tal Image Acq
u
isition a
nd Storage Syste
m
Work Flo
w
3. Hard
w
a
re
Compon
ents
of the Sy
stem
Digital im
age
acqui
sition a
nd
stora
ge
sy
stem in
term
s of ha
rd
wa
re
mainly by the
po
we
r
module, USB
interface m
o
dule, FPGA c
ontrol mo
dule
and FLASH
memory mo
d
u
les.
FPGA is the
digital image
acqui
sition a
nd
sto
r
ag
e control
core, controllin
g the
image
data re
ceptio
n, conversio
n
,
storage an
d
transmi
ssi
on
. Digital image data acq
u
i
s
ition interfa
c
e
use
s
the P
C
M form, whil
e
memory a
n
d
logic
cont
ro
l
units ad
opt T
T
L level. PCM interfa
c
e ci
rcuit
is structu
r
e
d
by PCM interface
chip S
N
65HV
D
10,
co
mpleting TT
L
→
422 and 422
→
TT
L
le
ve
l
conve
r
ter. DS92LV18 chi
p
s
comp
ose
a
c
quisitio
n
and stora
ge syste
m
feedba
ck
i
n
terfaces whi
c
h
with both inte
rnal inte
grate
d
deseri
a
lize
r
and seri
ali
z
e
r
[11]. In this desi
gn, DS9
2
L
V18 works
as
a de
se
rializer. When
the a
c
qui
sition
an
d sto
r
ag
e sy
stem receive
s
the
se
rial d
i
fferential
sig
nal,
the DS92
LV1
8
woul
d ma
ke them into
a 16-
bit para
llel data and
then se
nd to FPGA. Wh
en
FPGA receives the data, it would u
p
loa
d
to the PC for analysi
s
.
Comm
uni
cati
on
b
e
twe
en control boa
rd and
P
C
relys
on USB com
m
unication
i
n
terface;
It has many feature
s
, su
ch
as high d
a
ta transfe
r,
ca
n be hot-swapp
able, flexible appli
c
ation, e
t
c.
[12]. In the
di
gital imag
e
a
c
qui
sition
an
d sto
r
a
ge
system de
sig
n
,
FT245
RL
wa
s b
e
ing
choo
sen
as
USB
com
m
unication
chip. It had
be
en inte
grate
d
fi
rmw
a
re
lib
r
a
ry
, s
o
elimi
n
ates th
e n
e
e
d
for
addition
al co
mplex pro
g
ra
mming. USB interface ci
rcu
i
t conne
ction
diagram was
sho
w
n in Fi
g
u
re
2. In the figure, ACM-2
010
-900
-2P is th
e comm
on
-m
ode ind
u
cta
n
c
e an
d R2
4 is a ferrite be
ad.
Adding th
ese
two
sm
all m
odule
s
i
n
USB interfa
c
e
ci
rcuit, th
ey re
duce the
mut
ual inte
rferen
ce
betwe
en the
FPGA and th
e USB device. In the pro
c
ess of the PCB layout, to ensu
r
e that t
h
e
data line
s
D0
~
D7 a
r
e e
q
ual in le
ngth
and a
s
sho
r
t
as p
o
ssibl
e
in
ord
e
r to
achi
eve the pu
rp
ose
of wea
k
eni
ng
external ele
c
tromag
netic i
n
terferen
ce.
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
2302-4
046
Digital Im
age Storage Syst
em
Based on
USB and NA
ND Fla
s
h
(Yo
ngjun
Cui)
5193
Figure 2. USB Interface Ci
rcuit Conn
ecti
on Dia
g
ra
m
4. Ke
y
Logic
Design
Logi
c co
ntrol
main achieve
m
ents: USB read an
d writ
e function
s; u
s
ing alte
rnati
ng two-
plane pa
ge p
r
og
ram for th
e next pass
of the image data stora
g
e
, read and
era
s
e fun
c
tio
n
s;
putting forwa
r
d the imag
e
data sto
r
ed
in
the image
st
ore a
nd tran
sfer device to t
he main
co
ntro
l
comp
uter.
4.1. USB Re
ad-
w
ri
te Log
ic Design
Cha
nnel A in
FT245
RL ch
ip can b
e
set
to synchron
ous FIFO m
o
de. In this op
erating
mode,
data i
s
written
or read
out o
n
th
e ri
sing
e
dge
of the
CLKO
UT.
Rea
d
ing
and
writing
can
not be ope
rat
ed simulta
n
e
ously.
Whe
n
rea
d
in
g the
FT2
45
RL,
RXF
# h
a
s th
e
highe
st prio
rity. Wh
en the
FIFO
data to
be
read
out, RX
F # is lo
w, at the same ti
me, the
outp
u
t enabl
e
sig
nal OE #
is l
o
w, then, th
e
rea
d
enabl
e
sign
al
RD #
chan
g
e
s to
lo
w. In t
h
is
ope
rating
mode,
only b
o
th the
RXF
# an
d
RD #
a
r
e
low, the data will be read out. The data coming fr
om the FIFO woul
d be output to the A-channel
8-bit data p
o
r
t at the RD
# falling edg
e. Then t
he
RD # i
s
pulle
d high, achie
v
ing a byte read
operation. Du
ring a
write o
peratio
n, TXE # priority
i
s
in the hig
h
e
st level. So determi
ning t
h
e
level TXE # is the mo
st
importa
nt. If low, write
operation
ca
n not be p
e
r
forme
d
; in the
oppo
sition, writing ca
n be
perfo
rmed. When TXE # is
low, the writ
e enable
sign
al WR i
s
set
to
high
and
writing d
a
ta. The
n
the
WR lo
w, data
will
b
e
sent to th
e
FIFO, co
mple
ting a
byte write
operation. US
B internal FIF
O
read
and write timing sh
own in Fig
u
re
3.
Figure 3. USB Internal FIFO Rea
d
and
Write Timi
ng
4.2. Altern
ati
ng T
w
o
-
plan
e Page Prog
ram Logic Design
K9WBG0
8U1
M
is a NA
ND-type FLAS
H memo
ry
chip and the
data width i
s
8. But th
e
data
n
eed
to read, write
a
nd stora
ge a
c
hieve
to
1
6
-bit. To fulfill this
req
u
ireme
n
t, gene
rally
the
data wa
s div
i
ding into two 8-bit data
and then
st
o
r
e them in a
K9WBG08
U
1M twice. This
method i
s
fe
asibl
e
, but it spe
n
d
s
exe
c
ute two
st
ore
d
pro
c
e
d
u
r
e i
n
sto
r
ing a
1
6
-bit data,
which
greatly re
stri
cts the stor
ag
e rate. That
mean
s it can’
t reach
the tech
nical req
u
i
reme
nts of fast
stora
ge. In
thi
s
d
e
si
gn, F
L
ASH K9
WBG
08U1M-1 a
n
d
K9WB
G08
U
1M-2
were u
s
ed in
pa
rall
el
to
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 23
02-4
046
TELKOM
NI
KA
Vol. 12, No. 7, July 201
4: 5191 – 51
96
5194
achi
eve the
8-bit me
mory
cha
nge
d int
o
16
bits
wi
d
e
pu
rpo
s
e. S
pecifi
c
op
eration is putting
the
tw
o
c
h
ip
s
e
lec
t
p
i
n C
E
,
co
mma
nd
e
nab
le
p
i
n CL
E, a
d
d
r
e
s
s
e
nab
le
p
i
n AL
E, r
e
ad
an
d
w
r
ite
enabl
e pin
s
WE, RE se
ri
es, an
d ea
ch chip
R/B pin re
sp
ectiv
e
ly. Thus, th
e two chip
s
can
simultan
eou
sl
y write
com
m
and
or a
d
d
r
ess,
co
m
p
a
r
ing with ordi
nary
m
e
thod,
sto
r
ag
e spe
ed
doubli
ng. Ind
epen
dent of R/B pin is th
e cont
rol
ba
sis of altern
ating two
-
plan
e
page p
r
og
ra
m.
FLASH pin p
a
rallel
con
n
e
c
tion dia
g
ra
m
sho
w
n in Fig
u
re 4.
Figure 4. Paralleled FLAS
H Pin Con
n
e
c
tion
Diag
ram
Figure 5. Internal Stru
cture
K9WBG0
8U1
chi
p
i
s
divid
ed into
81
92
Block a
nd
e
a
ch
Block
co
mpri
se
s a
total of 6
4
Page, numb
e
r
ed fro
m
0 to 63. Every 2048 Blo
ck
m
a
ke
s up a Pl
ane. Du
ring t
he Block nu
mber
rang
ed from
0 to 409
5, th
e even n
u
mb
ered
Block
compo
s
e Pla
n
e0, odd
Nu
m
ber Blo
c
k co
nsi
s
t
Plane1. Duri
n
g
Block 409
6 ~
8
191, with
t
he
former
divi
sion, it i
s
divi
ded into
Plan
e2 a
nd Pla
n
e
3
.
Figure 5 sh
o
w
s the inte
rn
al stru
cture.
K9WBG0
8U1
internal d
a
ta
stora
ge i
s
a o
ne Page
ca
rri
ed out. Such a page
pro
g
ram ca
n
be divid
ed i
n
to comma
nd,
address and
data lo
adin
g
pro
c
e
s
s an
d
automatic p
r
o
g
rammi
ng
of
the
impleme
n
tation proce
s
s.
Loadin
g
proce
s
s mea
n
s
co
ntrollin
g
by the external
clo
ck,
the
comm
and,
a
ddre
s
s, data
and
othe
r i
n
formatio
n
wri
tten into th
e internal
re
gisters. Auto
matic
prog
ram
m
ing
pro
c
e
ss i
s
the chip a
c
co
rd
ing to the loa
ded informati
on putting th
e data sto
r
ed
to
the corre
s
po
nding
po
sitio
n
. So the
proce
s
s of
dat
a sto
r
ag
e i
s
finishe
d
. The
time it take
s i
s
prog
ram
m
ed time,
usu
a
lly betwe
en
the
200u
s ~
7
0
0
u
s.
Acco
rdin
g to the
chi
p
inform
ation,
the
spe
ed of rea
d
and write to the FLASH chip is
4
0
M
B
/s. The time requi
red to read or
write
one
data is:
T
WR
=
M
40
1
× 4K =102.4
μ
s
(
1
)
The g
ene
ral
page
pro
g
ra
m is a
se
que
nce. Fi
rstly, l
oad o
ne u
n
it’s comma
nd,
address
and d
a
ta, then autom
atic prog
ram
m
in
g. Followi
ng
th
is spee
d calcul
ation, th
e write
sp
ee
d of
FLASH is
:
V=
s
4
.
102
s
200
4096
μ
μ
byte
=
13.54MB/
s
(
2)
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
2302-4
046
Digital Im
age Storage Syst
em
Based on
USB and NA
ND Fla
s
h
(Yo
ngjun
Cui)
5195
This
spe
ed
can not me
et the req
u
ire
m
ent
of
the missi
on state
m
ent.
The choice
of
alternating t
w
o-plane page pr
ogram
will
enable the programmi
ng time greatly reduced.
Alternating t
w
o-pla
ne
page
pro
g
ra
m op
e
r
ation i
s
a
s
fo
llows: First, write
into K9
WBG08U1M-1 i
n
the Block0
Plane0 P
age
0, followed
by written
K
9
WBG
08U1
M
-1 Pla
ne1
Block1 Pa
ge
0, as
sho
w
n in Fi
g
u
re5
red
box
. When returned to the Pl
ane0 K9
WB
G08
U
1M
-1, it is alre
ady g
one
25n
s ×
409
6
× 7
= 71
6.8
u
s, g
r
eate
r
than tP
ROG (tPROG
stand
s for th
e pro
g
rammi
ng ti
me)
maximum 70
0ns. So it will
not affect Plane0 to m
a
ke the second
operation. S
u
ch
reu
s
e
of time
can
sho
r
ten the time of the loading p
r
o
c
e
ss
which h
a
s greatly impr
oved the
storag
e sp
eed.
FLASH write pro
c
e
ss i
s
sh
own in Fig
u
re
6.
Figure 6. FLASH Write Pro
c
e
s
s
In memory ch
ip parall
e
l op
eration m
ode,
when p
o
wered on digital i
m
age a
c
qui
si
tion and
stora
ge syste
m
immedi
atel
y
make
s bad
blocks
mo
nito
r. As l
ong
a
s
there i
s
an i
n
valid blo
ck,
the
entire
block will be deemed to
be invalid bl
ock. Such inv
a
lid block address integrated
manag
eme
n
t, gre
a
tly facilit
ates th
e
stre
amlined
alternating t
w
o-pl
ane
page
p
r
o
g
ram
op
erati
on,
redu
cin
g
the compl
e
xity of
the cont
ro
l lo
gic an
d enh
a
n
ce the
stora
ge sp
eed.
4.3. Issued a
nd Upload
th
e Image Data Process Fl
o
w
Image data i
s
sue
d
process: make
s the i
s
sued
pi
ctu
r
e
or video into
a contin
uou
s frame
format. The
frame
imag
e
is e
n
coded
a
dding
self
-si
g
ns
and f
r
am
e si
gn
s, and
then
sen
d
t
he
image data to
the next.
Image data read-ba
ck p
r
o
c
e
ss: t
he ho
st com
puter
use
s
USB in
terface to m
a
ke th
e
colle
cted o
r
image data
re
ad ba
ck tra
n
smitted to the
PC. PC recei
v
es image d
a
t
a and cal
c
ul
ates
the error rate
, then showi
ng in the form of
animation, the frame image play
back. Finally, the
results of dat
a analysi
s
wo
uld gen
erate f
iles an
d save
in the spe
c
ifie
d dire
ctory.
5. Results a
nd Discu
ssi
on
Whe
n
ea
ch
module i
ndivi
dually teste
d
su
cces
sfully, each mo
dule
is conn
ecte
d, maki
ng
the entire sy
stem functiona
l test. Experimental re
sult
s sh
ow that d
a
ta store
d
in the FLASH at the
spe
ed of
30
MB/s. It is be
tter than the
maximum tra
n
smi
ssi
on
sp
eed of t
w
iste
d is
1Mb/s in
per
one h
und
red
meter
by the co
mmonly
RS-4
22 inte
rface. Throu
gh
some ch
ange
s,
the h
o
st
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 23
02-4
046
TELKOM
NI
KA
Vol. 12, No. 7, July 201
4: 5191 – 51
96
5196
comp
uter g
e
ts the issue
d
data from the
image st
o
r
e
and tran
sfe
r
device. PC a
nalysi
s
software
can
com
p
a
r
e
the rea
d
ba
ck
data a
nd
sen
d
ing
ra
w
data, and
we
can
re
store
the image to
be
displ
a
yed. T
e
sting
pha
se
, issu
ed a g
ood
cyclic
al
picture, and
displ
a
yed th
e re
ceived
d
a
ta
th
r
o
u
g
h
th
e
PC
s
o
ftw
ar
e
.
D
a
ta co
mp
ar
is
on
s
h
ow
ed th
a
t
er
r
o
r
r
a
te
is 0
.
Th
e
de
c
r
yp
ted
da
ta
is
read ba
ck by
the
host co
mputer.
Th
e data
is sho
w
n
in graphi
cs
in Figure 7. It is more ea
sil
y
to
observe the e
x
perime
n
tal result
s.
Figure 7. Dat
a
Shown in G
r
aphi
cs
6. Conclusio
n
To a
c
hieve a
large
num
b
e
r of digital i
m
age
si
gn
al
acq
u
isitio
n a
nd sto
r
ag
e, a de
sign
based o
n
USB and alte
rn
ating two
-
pl
a
ne pa
ge
pro
g
ram i
s
pro
p
ose
d
. The
sy
stem a
c
hi
eve
s
a
fast sto
r
ag
e,
high-sp
eed
transmi
ssion
a
nd a
c
cura
te f
eedb
ack in
th
e u
s
e of th
e t
w
o te
ch
nologi
es.
Actual test re
sults h
a
ve fully proved that
the prop
osed
desi
gn corre
c
tness and reli
ability.
Referen
ces
[1]
Bai Xia
n
min, Z
han
g Yatin
g
,
Zhan Ji
anh
ua,
L
i
u W
e
n
y
i,
Ha
n Huil
ia
n.
T
he high-sp
eed d
a
ta
acquisiti
o
n
s
y
stem bas
ed
on LVDS in
terface and
t
w
o
-
pl
an
e flas
h-op
eratin
g
w
a
y
.
IEEE 2nd International
Confer
ence
on
Softw
are Engineer
ing a
nd Se
rvice Scie
nce
. 201
1: 516-
519.
[2]
Z
hang
Hui
x
in,
Guo Z
hen
g,
Ye
Yong. D
e
sig
n
of hi
g
h
-spe
ed r
e
mote ima
ge
d
a
ta storag
e me
mor
y
base
d
on LVDS.
Adv
ance
d
Materia
l
s Rease
a
rch
. 2
013; 60
5-6
07: 198
9-19
93.
[3]
W
e
i Z
u
ku
an,
Kim H
ong
ye
o
n
, Kim Y
o
u
n
g
k
y
u
n, Kim, J
a
eho
ng. A
n
efficient c
onte
n
t
base
d
im
ag
e
retrieval scheme.
T
E
LKOMNIKA Indo
nes
i
an J
ourn
a
l
of
Electrical
En
gi
neer
ing.
2
013;
11(
11): 6
9
8
6
-
699
1.
[4]
Bisht Amit Si
ng
h, Rath
od S
o
m
s
ing,
Vara
dar
aj
an V,
Kumar
S. Yog
eesh.
F
P
GA base
d
h
a
rd
w
a
re des
ig
n
of hi
gh
spe
e
d
co
mpact T
/
R u
n
it c
ontrol
l
er.
Proc
ee
din
g
s of t
he I
n
ternati
ona
l
Co
nferenc
e
o
n
Electroma
gneti
c
Interference
and
C
o
mpati
b
i
l
i
t
y
. 20
08: 57
3-
577.
[5]
W
ang H
o
n
g
li
a
ng, W
a
n
g
H
a
ir
ui,
Din
g H
a
ifei.
Desi
gn
of d
a
ta ac
quis
i
tion
a
nd stor
age
s
y
s
t
em for di
gita
l
and a
n
a
l
og si
g
nal b
a
se
d on F
P
GA.
Advanced Materials Research.
20
13;
605-
607: 9
55-9
59.
[6]
Dietz Jim,
Hu
bbar
d R
i
char
d.
T
he secret
s of
successfu
l
communic
a
tio
n
s
usi
ng LVDS.
EDN.
20
05;
50(2
1
): 89-9
2
.
[7]
Xu
Ji
an, W
a
n
g
Z
h
i
gon
g,
Niu
Xia
o
kan
g
. D
e
sig
n
of
hi
gh
spee
d L
V
DS t
r
ansce
iver ICs
.
Jo
u
r
na
l
of
Semico
nductor
s
.
2010; 31(
7): 11-1
4
.
[8]
Pravosso
ud
ovi
t
ch S, Godar
d B.
NAND
flash testi
ng:
A prel
i
m
in
ary
study o
n
ac
tual d
e
fects.
Procee
din
g
s - Internati
o
n
a
l T
e
st Conferenc
e. 200
9.
[9]
T
s
eng, Hung-
W
e
i, Grupp, La
ura M,
S
w
a
n
s
o
n Steven
.
Un
d
e
rpow
eri
ng NA
ND flash: Profit
s and p
e
rils.
Procee
din
g
s - Desig
n
Autom
a
tion C
onfer
en
ce.
2013.
[10]
H
y
de Jo
hn. Intercon
nectin
g
U
SB devices.
El
ectronics W
o
rl
d.
2011; 1
17(1
906): 44-
45.
[11] Szeco
w
k
a
,
Przem
y
s
l
a
w
M
Py
rz
y
n
sk
i, Kamil J.
USB recei
v
er/transmitter
for F
P
GA imp
l
ementati
on.
Internatio
na
l
Confer
ence
o
n
Sig
nals
an
d Elec
tro
n
ic
S
y
stems, ICS
ES 201
2 - T
he C
onfer
enc
e
Procee
din
g
s. 2
012.
[12]
Shuj
ing
Su, Ji
a
n
she
ng
Le
i. A
me
thod
of mu
lti-cha
nne
l d
a
ta
acqu
isit
io
n
w
i
t
h
a
d
justa
b
l
e
s
a
mpli
ng
rate
.
T
E
LKOMNIKA Indon
esi
an Jou
r
nal of Electric
al Eng
i
ne
eri
ng.
2013; 1
1
(9): 5
299-
530
7.
Evaluation Warning : The document was created with Spire.PDF for Python.