TELKOM
NIKA Indonesia
n
Journal of
Electrical En
gineering
Vol.12, No.4, April 201
4, pp. 2565 ~ 2
5
7
3
DOI: http://dx.doi.org/10.11591/telkomni
ka.v12i4.4791
2565
Re
cei
v
ed Se
ptem
ber 7, 2013; Re
vi
sed
Octob
e
r 17, 2
013; Accepte
d
No
vem
ber
19, 2013
Low Leakage C
i
rcuits Design with Optimized Gate-
length Biasing
Xiaohui Fan
a
, Yangbo Wu
*
b
, Haiy
an Ni, Jianping Hu
F
a
cult
y
of Information Sci
enc
e and T
e
chno
l
o
g
y
, Nin
gb
o Universit
y
, Ni
ng
bo, Chi
n
a
*Corres
p
o
ndi
n
g
author, e-ma
i
l
: eas
y
f
an
xh
@
126.com
a
, w
u
yang
bo@
nb
u.e
du.cn
b
A
b
st
r
a
ct
W
i
th the tec
h
n
o
lo
gy pr
ocess
scalin
g, l
eak
ag
e p
o
w
e
r diss
ip
ation
is
bec
omi
ng
a gr
ow
ing
n
u
mber
of
perce
ntag
e i
n
total p
o
w
e
r d
i
ssipati
on. T
h
i
s
study
pr
ese
n
ts a n
e
w
me
thod i
n
th
e g
a
te-le
ngth
bi
a
s
ing
techni
qu
e to
a
c
hiev
e a
cost-e
ffective gate-
le
ngth w
i
th
a
mo
st ben
efit betw
een
le
aka
ge r
e
ductio
n
a
nd
de
lay
i
n
crea
si
ng
. Wi
th
th
e o
p
t
imi
z
e
d
ga
te
-l
en
g
t
h
,
typ
i
ca
l com
b
i
n
a
t
i
o
na
l
a
n
d
seq
u
e
n
t
i
a
l ci
rcui
ts a
r
e
re
al
i
z
ed
and
simulat
ed
usin
g HSPICE w
i
t
h
the BSIM
4
.6
.4 pre
d
icti
ve
mo
de
ls at
a 4
5
n
m
CO
MS
pr
ocess. T
he r
e
sults
show
that lea
k
age curr
ents
of typi
cal co
mb
in
ation
a
l cir
c
uits reduc
e
mor
e
an
d de
l
a
y incre
a
se l
e
ss.
Moreov
er, leak
age curr
ents o
f
mirror ad
der
and trans
mis
s
ion g
a
te ad
d
e
r decre
ase 1
3
.9% an
d 8.9
0
%,
respectiv
e
ly; a
nd le
aka
ge p
o
w
er of 4-bit bin
a
ry count
ers u
s
ing C
2
MOS D
F
lip-F
lop
and
T
r
ansmissio
n
-
G
ate
D
Fl
i
p
-Fl
o
p
redu
ce
38
.3
6%
an
d
20
.0
5%
, wi
th
th
e
fre
que
nc
y of 5M, resp
e
c
tively. T
heref
ore, the
opti
m
i
z
e
d
gate-l
engt
h bia
s
ing tech
ni
que
is an attractive
appr
oach i
n
lo
w
pow
er circuits desig
n.
Ke
y
w
ords
:
lo
w
leakage, g
a
te-le
ngth bi
asi
n
g, cost-e
ffective gate-l
e
n
g
th, HSPICE simul
a
tion
Copy
right
©
2014 In
stitu
t
e o
f
Ad
van
ced
En
g
i
n
eerin
g and
Scien
ce. All
rig
h
t
s reser
ve
d
.
1. Introduc
tion
With the
eve
r
increa
sin
g
d
e
mand
an
d p
opula
r
ity of p
o
rtable
ele
c
tronics, d
e
si
gn
ers a
r
e
striving
for
small
silico
n
a
r
ea,
highe
r
speed,
high
re
liability and
l
o
w
po
wer di
ssipatio
n [1].
The
power di
ssip
ation of ci
rcui
ts affects th
e
battery
life of portabl
e ele
c
t
r
oni
cs. T
here
are th
ree m
a
in
power di
ssip
ations i
n
ci
rcuits: dynami
c
power
di
ssi
pation, short
-
circuit po
we
r dissipatio
n
and
leakage p
o
wer dissip
ation
[2].
Re
cently, CMOS techn
o
l
ogy develop
s into
micro
-
n
anomete
r
re
gime, leakag
e power
dissipatio
n a
c
count
s for
an in
crea
sin
g
ly larg
er
po
rtion of total
po
wer di
ssi
pation in
CMOS
circuits.
It is
reporte
d that
the p
o
rtion
of
leak
age
po
wer h
a
s in
crea
sed
from
18
% at 130
nm
to
54% at the 65 nm node [3]
.
Lea
kag
e
re
d
u
ction m
e
tho
d
s in
clu
de
standby
techn
i
que
s an
d runtime te
chn
i
que
s.
Standby lea
k
age
red
u
ctio
n techniqu
es de
cre
a
se
th
e lea
k
ag
e
when th
e ci
rcuits a
r
e
not
in
operation,
wh
ile ru
ntime te
chni
que
s d
e
crea
se th
e le
a
k
ag
e when
th
e ci
rcuits
are
in active
mod
e
.
Several stan
dby
lea
k
ag
e redu
ction
te
chniqu
es
have
being
pro
p
o
s
ed,
su
ch a
s
dual th
resho
l
d
CMOS, va
ria
b
le th
re
shold
CMOS, in
put
vector cont
rol
,
and
sta
c
kin
g
tra
n
si
stor te
chni
que,
po
wer
gating te
ch
n
i
que, et
c [4
]. The
runti
m
e le
ak
age
re
du
ction t
e
ch
niqu
es i
n
clu
de
multi-
V
th
manufa
c
turi
n
g
pro
c
e
ss a
n
d
gate-le
ngth
biasi
ng [3, 5, 6].
These
meth
ods have a
d
vantage
s
a
nd
di
sadva
n
tage
s, su
ch
as, multi
-
V
th
me
th
od
redu
ce
s the l
eakage p
o
we
r effectively, but additi
on
al
step
s and
m
a
sks
rai
s
e its pro
c
e
ss
co
st
.
Gate-le
ngth
b
i
asin
g techniq
ue redu
ce
s th
e lea
k
ag
e
without extra
ma
sk and
extra
pro
c
e
ss,
and
it
is re
port
ed th
at small bi
ases in g
a
te-l
en
gth of
tran
sist
ors
ca
n afford signifi
cant l
eakage
savin
g
s
with
small
pe
rforma
nce im
pact [3]. A
m
e
thod
of gate
-
length
bia
s
in
g was p
r
op
o
s
ed
in [3],
an
d
redu
ce
d le
akage
by 24%
-38% for mo
st com
m
only
u
s
ed
cells,
whi
l
e in
curring
d
e
lay pe
naltie
s
of
fewer than 10%.
In this wo
rk,
we
propo
se
a
ne
w m
e
thod
to o
p
timize
the g
a
te-le
ngt
h. We
g
e
t a
relatively
co
st-effe
ctive gate-le
ngth
with
a mo
st b
enefit betwe
e
n
leakage
re
ductio
n
and
delay incre
a
sing,
that is max
i
mizing th
e
leakage
re
ductio
n
with
minimal d
e
lay pen
alty. Then, severa
l
combi
nation
a
l
logic ci
rcuits a
nd
seq
u
e
n
tial ci
rc
uits
are
used to
verify the co
st-effe
ctive g
a
te-
length. Moreover, as
the battery life of
port
able elec
tronics
is
mainly determined by average
power, we ta
ke the averag
ing to meas
ure the re
sults i
n
this pap
er.
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 23
02-4
046
TELKOM
NI
KA
Vol. 12, No. 4, April 2014: 2565 – 2
573
2566
This p
ape
r is orga
nized a
s
follo
ws. In
Section 2, le
aka
ge
curren
t of MOS de
vices
i
s
descri
bed, an
d the gate-le
ngth bia
s
ing t
e
ch
niqu
e is
reviewe
d
. In Section 3, we prop
ose a co
st-
effective gate
-
length
optimi
z
ation m
e
tho
d
.
Basic com
b
ination
a
l
an
d
seq
uential circuits with
the
optimize
d
g
a
t
e-length
are
impleme
n
te
d and
sim
u
la
ted in Se
ctio
n 4 a
nd 5,
resp
ectively. The
con
c
lu
sio
n
is
dedi
cated in
Section 6.
2. Rev
i
e
w
o
f
Gate
-leng
t
h
Biasing Te
c
hnique
2.1. The Lea
kage o
f
MOS
Dev
i
ces
In nanom
eter regime, a
sig
n
ificant po
rtio
n of
total power di
ssi
pation
in high pe
rfo
r
man
c
e
digital circuit
s
is due to lea
k
ag
e cu
rrents [4, 7, 8].
The l
e
a
k
age
curre
n
t in
M
O
S devi
c
e
s
i
s
m
a
inly d
ue
to (1
)
sub
-
thresh
old
co
ndu
ction,
(2
)
gate dire
ct tunneli
ng cu
rrent, (3) jun
c
t
i
on tunne
lin
g
leaka
ge, (4
) gate indu
ce
d drain le
aka
ge
(GIDL), (5
) h
o
t carrier inj
e
ction current, (6) p
u
n
c
h-th
rough
curre
n
t, etc [7].
Figure 1. Major Lea
ka
ge of
MOS Device
Among the
m
, the majo
r l
eakage
cu
rre
n
ts a
r
e: sub
-
threshold
lea
k
ag
e current,
gate
leakage
cu
rre
n
t and
reve
rse-bia
s
j
u
n
c
tion ban
d-to
-ba
nd tunn
eling l
eakage
cu
rre
n
t as
sh
own i
n
Figure 1
[9]. With the
tech
nology
scalin
g, su
b-th
re
sh
old le
akage
current h
a
s be
comin
g
the
m
a
in
sou
r
ce of lea
k
ag
e po
wer d
i
ssi
pation.
2.2. Gate
-len
gth Bia
s
ing Techniqu
e
There are m
any leaka
g
e
powe
r
red
u
c
tion tec
hniq
ues, such a
s
tran
sisto
r
stackin
g
techni
que, d
ual-th
r
e
s
hold
techniqu
e, etc. It is
fou
nd that, as the gate-l
engt
h increa
se
s, the
leakage po
wer dissip
ation
will decline e
x
ponentially and the delay
only increa
se linearly [3, 10].
The fact provides a p
o
ssib
ility for the gate-lengt
h bi
asing tech
nique
: an appro
p
ri
ate increa
se
of
gate-le
ngth
can
significant
ly redu
ce
lea
k
ag
e p
o
we
r
dissipatio
n while pe
rforma
nce
of the
ci
rcuit
will not l
o
se too much.
Moreov
er, the technique
doe
sn’t increase the
extra process
cost
becau
se it ne
edn’t extra m
a
sk and extra
process.
In nanom
ete
r
CM
OS dev
ice, a
s
gate
-
length b
e
co
mes
sho
r
te
r,
V
th
sho
w
s
a gre
a
t
e
r
depe
nden
ce
on g
a
te-le
ngt
h [11], d
ue t
o
the
short
-
chann
el effe
ct (SCE
)
and
drain
ind
u
ce
d
barrier lo
we
ri
ng (DIBL
)
.
V
th
change
d
u
e
to SCE and DIBL is mod
e
l
ed (1
).
(,
)
-
(
)
[
2
(
-
)
]
th
t
h
e
f
f
b
i
s
ds
VS
C
E
D
I
B
L
L
V
V
(1)
Whe
r
e
V
bi
,
is kno
w
n a
s
the built-in voltage of the sou
r
ce/d
rai
n
junctions,
V
ds
is the sou
r
ce/
d
r
a
in
voltage
，
Ф
s
is the surfa
c
e
potential. The sho
r
t chan
nel effect co
efficient
θ
th
(
L
eff
) in (1) ha
s a
stron
g
dep
en
den
ce on the
cha
nnel len
g
t
h
given by:
0.
5
()
=
cos
h
(
)
-
1
ef
f
ef
f
t
L
Ll
(2)
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
2302-4
046
Low L
e
a
k
ag
e
Circuits Desi
gn with Optim
i
zed G
a
te-le
n
g
th Biasing
(Xiaohui Fa
n)
2567
l
t
is
the c
h
arac
teris
t
ic
length of devic
es
.
And the impa
ct of threshol
d voltage in sub-th
re
shol
d leakage [12] i
s
expre
s
sed
as (3
).
We can see that decrea
s
e
of
threshold voltage will result in sub-th
re
shol
d lea
k
ag
e raise
expone
ntially.
2
-
-
(
-
1
)
exp(
)
[
1
-
exp(
-
)
]
gs
t
h
ds
on
su
b
e
f
f
ox
T
ef
f
T
T
VV
V
W
IC
m
v
L
mv
v
(3)
W/L
eff
is the
width-to
-le
ngt
h ratio
of th
e tran
si
stor,
eff
*
C
ox
is the pro
c
e
s
s tra
n
s-co
ndu
ctan
ce
para
m
eter,
T
vk
T
q
is the equival
ent temperat
ure voltage,
m is the threshold rate coef
ficient,
V
gs
is the gate/sou
r
ce voltage, and
V
th
pre
s
ent
s the thre
shol
d voltage of MOS device.
Acco
rdi
ng to
(1), (2
) an
d (3), with
gat
e-le
ngth i
n
crea
sing, th
e thre
shold
voltage
increa
se
s, so
that the le
a
k
ag
e
current
de
cre
a
se
s
expone
ntially. The
r
efore, i
t
is po
ssible
to
slightly increa
se the gate
-
le
ngth to take
a
d
vantage of the expon
enti
a
l leakage re
ductio
n
.
Figure 2 sho
w
s the vari
ation of
leaka
ge with gate
-
length
(
L
Gate
) at a 45nm
CMO
S
pro
c
e
ss.
Th
e
nominal le
ngt
h is 50n
m, an
d the wi
dth of
PMOS and NMOS tra
n
si
stors is 1
000
nm.
The su
pply voltage of the tran
sisto
r
s is
1.0V.
Figure 2. Lea
kag
e
Variatio
n with Gate
-length
It can be
not
ed that lea
k
a
ge de
crea
se
s expo
nent
ial
l
y with slig
htly incre
a
se of
gate-
length. The l
eakage
cu
rre
nt of NM
OS redu
ce
s by 52
% and 66% a
t
L
Gate
=55nm and
L
Gate
=
60n
m
comp
ared
wi
th that of no
minal len
g
th
NMOS,
respectively. Th
e lea
k
ag
e current of PM
OS
redu
ce
s by 7
2
% and 8
7
%, respe
c
tively. In additi
on, t
he in
cre
a
se i
n
gate-l
ength
decrea
s
e
s
t
he
leakage effe
ctively; and th
e longe
r gate
-
lengt
h, the sl
owe
r
in lea
k
a
ge de
cre
a
se.
3. The Gate-l
ength O
p
tim
i
zation for Efficienc
y
Leakage Reduc
tion
In this se
ctio
n, we propo
se a co
st-effe
ct
ive gate-le
n
g
th optimizati
on method
b
a
se
d on
HSPICE sim
u
lation by usi
ng a 12-stag
es inverte
r
ri
ng oscillato
r at a 45nm CMOS pro
c
e
s
s. The
inverter ri
ng
o
scill
ator is pre
s
ente
d
in
Fig
u
re
3. T
he
rat
i
o of PM
OS
o
v
er
NMOS i
n
the inve
rters i
s
40
λ
/20
λ
, where
λ
=25n
m a
t
45nm pro
c
e
ss. Th
e variat
ion of delay a
nd lea
k
ag
e with gate-len
g
th
are sho
w
n in
Figure 4 and
Figure 5.
Figure 3. 12-stage
s Invert
er Rin
g
Oscill
ator
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 23
02-4
046
TELKOM
NI
KA
Vol. 12, No. 4, April 2014: 2565 – 2
573
2568
Figure 4. Vari
ations of Le
a
k
ag
e Cu
rrent and
Delay
Figure 5. Vari
ation Rate of
Lea
kag
e
Cu
rrent
and Delay
Figure 4 sh
ows that as t
he gate-le
ngth increa
ses, the lea
k
age current decli
ne
s
expone
ntially, and
the
dela
y
only in
crea
se
s lin
early.
Therefore,
we in
cre
a
se th
e gate
-
len
g
th
to
get the maximum ben
efit betwe
en lea
k
age an
d dela
y
.
Here dynami
c
programmi
ng algorithm
is
utilized to determine the value of
L
Gate
for
transi
s
to
rs. T
he ben
efit
Ga
t
e
()
c
fL
is defined a
s
fol
l
ows:
Ga
t
e
0
0
()
-
cl
l
d
d
f
LI
I
T
T
(4)
Whe
r
e
0
l
I
and
0
d
T
are the l
eakage
cu
rrent and
del
ay of nomin
al
L
Gate
ring oscillator,
r
e
spec
tively.
Figure 6. Benefit with Gate-length Va
riat
ion
The
re
sult in
d
i
cate
s that
th
e maximu
m b
enefit is the
max
Ga
t
e
()
c
fL
, and
the
co
st-effe
ctive
gate-le
ngth i
s
53nm. It p
r
o
v
ides
one
of
the be
st tra
d
eoffs b
e
twe
e
n
lea
k
ag
e p
o
wer di
ssi
pati
o
n
and pe
rform
a
nce in lo
w po
wer a
ppli
c
atio
ns.
4. The Comb
inational Cir
c
uits Design
w
i
th
the Op
timized Gate-length
In this sectio
n, the ba
sic
combi
nation
a
l
ci
rcuits with
gate-le
ngth
biasi
ng te
chn
i
que a
r
e
pre
s
ente
d
. All the circuits a
r
e sim
u
lated
with HS
IPCE at 45nm pro
c
ess. The nom
inal gate-l
eng
th
is 50nm, an
d the optimize
d
gate-len
g
th is 53nm. Th
e sup
p
ly voltage of the circui
ts is 1.0V.
4.1. The Basi
c Gate
s
w
i
th
Gate
-leng
t
h Biasing Te
c
hnique
The ba
sic
ga
tes su
ch a
s
i
n
verter, NA
ND, NO
R and
XOR are im
portant ele
m
ents in
digital ci
rcuits. Here we test the basi
c
l
o
gic g
a
tes
wit
h
gate
-
length
biasi
ng. Th
e
width of
NM
OS
and PM
OS i
n
NA
ND,
NO
R a
nd X
O
R i
s
sho
w
n
in
F
i
gure
7,
wh
ere
λ
=25n
m at
45n
m p
r
o
c
e
ss.
The lea
k
ag
e and del
ay of 2NAND, 2NO
R
, and 2X
O
R
are sh
own in
Table 1 and
Table 2.
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a
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a
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(Xiaohui Fa
n)
2569
Figure 7. Basic Gate
s
Table 1. Lea
kage Current o
f
Basic Gate
Circuits
Input
Leakage curre
nt(
n
A)
2NAND
2NOR
2XOR
L=50nm
L=53nm
L=50nm
L=53nm
L=50nm
L=53nm
00
12.3
12
16.4 12.8 76.5 61.9
01
25.9 18.5 6.21 2.66 86.8 73.2
10
16.7 13.1 2.98
1.5
76.3 61.7
11
12.3 5.19 0.30 0.22 66.1 51.5
Average
16.8 12.2 6.47
4.3 76.43
62.08
∆
I
%
-27.4
-33.6
-18.8
Table 2. Del
a
y Chara
c
te
ristics of Basi
c
Gate Ci
rcuit
s
2NAND
2NOR
2XOR
L=50nm
L=53nm
L=50nm
L=53nm
L=50nm
L=53nm
T
d
(ps)
13.2 14.7 15.2
17.15
32.8 34.3
∆
T
d
%
11.36
12.83
4.57
The re
sults show
that
th
e basi
c
gate
s
with
gat
e
-
lengt
h bia
s
in
g h
a
ve lo
we
r le
aka
ge. As is
sho
w
n th
at the lea
k
ag
e currents
of ba
sic
gate
s
: 2NAND, 2
N
O
R
, and 2XO
R
decrea
s
e
27.
4%,
33.6% and
1
8
.8%, respe
c
tively. Howev
e
r, as t
he gat
e-len
g
th in
cre
a
se
s, the lo
a
d
ca
pa
citan
c
e of
basi
c
gate
s
in
cre
a
ses, an
d delay, respe
c
ti
vely, increases by 11.36%
, 12.83% and
4.57%.
4.2. Full Adder
w
i
th Ga
te
-length Bia
s
ing Techniqu
e.
The add
er is
an importa
nt logical unit in digital system
s. The po
wer and spe
ed o
f
adder
will g
r
eatly a
ffect the pe
rf
orma
nce of
digital
sy
ste
m
[13]. Figu
re 8
sho
w
s two typical a
dder
circuits: mi
rro
r adde
r an
d tran
smi
ssi
on
gate add
er.
The si
ze of tran
sisto
r
s is
also in
clu
ded
in
Figure 8,
wh
e
r
e
λ
=2
5nm a
t
45nm
proce
ss. Two
a
dde
rs
have
sym
m
etric st
ru
ctu
r
e
and
the
sa
me
numbe
r of tra
n
si
stors. The
simulatio
n
re
sults a
r
e liste
d in Table 3 a
nd Table 4.
Figure 8. Two
Different Mo
dels of Adde
r Circuit
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Vol. 12, No. 4, April 2014: 2565 – 2
573
2570
Table 3. Lea
kage Current o
f
the Two Adders
Input
Leakage curre
nt(
n
A)
Mirror ad
der
Transmission gate adder
L=50nm
L=53nm
L=50nm
L=53nm
000 204
188
737.4
680.69
001 199
150
784.93
701.6
010 241
196
749.98
696.1
011 239
193
790.92
709.51
100 235
196
821.75
740.37
101 214
197
760.89
707.03
110 215
201
786.56
703.25
111 223
203
731.89
677.06
Average
221.25
190.5
770.54
701.06
∆
I
%
-13.90
-8.90
Table 4. Del
a
y Chara
c
te
ristics of the Two Adders
Mirror ad
der
Transmission gate adder
L=50nm
L=53nm
L=50nm
L=53nm
T
d
(ps)
42.88
48.5
55.67
59.52
∆
T
d
%
13.12
6.92
It is clea
r fro
m
Table
3 a
nd Tabl
e 4 t
hat lea
k
ag
e
curre
n
t of the gate-l
ength
biasi
n
g
adde
rs h
a
s
decrea
s
e
d
b
y
13.90% and 8.90%, re
sp
ectively, than the no
minal gate-l
e
ngth
adde
rs.
Othe
rwi
s
e, d
e
lay
of the g
a
te-le
ngth bi
asi
ng
adde
rs, i
n
cre
a
se
d by
13.1
2
% and
6.92
%,
r
e
spec
tively.
5. The Sequ
ential Circui
ts Design
w
i
t
h
the Op
timized G
a
te
-len
gth
In seq
uential
circuits de
sig
n
, Flip-Fl
o
p
s
are th
e mo
st
importa
nt buil
d
ing bl
ocks [14, 15].
Powe
r an
d p
e
rform
a
n
c
e
a
nalysi
s
of Fli
p
-Flo
ps
have
alway
s
b
een
criti
c
al d
ue t
o
its a
ppli
c
ati
ons
in data
path
[2]. In this S
e
ction,
D
Flip-Flo
p
a
nd a
4-bit
bina
ry cou
n
ter with the
gate
-
len
g
t
h
biasi
ng te
ch
ni
que
are di
scu
s
sed. T
he
ci
rcuits a
r
e
sim
u
lated usi
ng HSIPCE with the
fre
que
ncy
of
5M at 45nm
pro
c
e
ss te
ch
nology. The
nominal le
ngt
h is 50n
m, and the optimi
z
ation le
ngth
is
53nm.Th
e
su
pply voltage of the circuits is 1.0V.
Analysis
of combi
nation
a
l
logic
circui
t
and seque
ntial logic
ci
rcuit a
r
e
different
,
esp
e
ci
ally in powe
r
an
d
time metrics
analysi
s
. The
powe
r
metri
c
used h
e
re
is the avera
g
e
leakage p
o
wer con
s
ume
d
over a
con
s
t
ant time inte
rval for variou
s inp
u
t states and tra
n
sitio
n
s
[16, 17].The
timing metri
c
s con
s
ide
r
ed
inclu
d
e
s
the
clo
c
k-to-out
put propag
ation del
ay, set
u
p
time and hold
time [16].
5.1. D Flip-Flops De
sign w
i
th Ga
te-le
ngth Bia
s
ing
Technique
This
part
we
analysi
s
th
e
leakage
po
wer an
d tim
e
metri
c
of t
he D Flip
-Fl
op. Two
stru
ctures of
D Fli
p
-Fl
o
p
are
de
scrib
ed in
Figu
re
9, and
the
width
of transi
s
tors i
s
also
pre
s
ente
d
, where
λ
=2
5n
m at 45nm proce
s
s.
Figure 9. Two
Different Structures M
ode
l of D Flip-Flo
p
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Low L
e
a
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ag
e
Circuits Desi
gn with Optim
i
zed G
a
te-le
n
g
th Biasing
(Xiaohui Fa
n)
2571
The l
e
a
k
ag
e
power is sho
w
n i
n
T
able
5. The
timing
pa
ramete
rs
are
sho
w
n i
n
Tabl
e 6.
Due to the ho
ld time remai
n
0 in the desi
gn, the para
m
eter isn’t listed in Table 6.
Table 5. Lea
kage Power of
D Flip-Flo
p
Output
Leakage Po
w
e
r(
pW)
C
2
MO
S-
FF T
G
-
F
F
L=50nm
L=53nm
L=50nm
L=53nm
0 0.33
0.22
0.150
0.132
1 0.09
0.08
0.085
0.076
Average
0.21
0.15
0.118
0.104
∆
Leak-Power
%
-28.57
-11.49
Table 6. Time
Characte
ri
stics of D Fli
p
-F
lop
Clock-to-out time
(ps)
Setup time(ps)
L=50nm
L=53nm
L=50nm
L=53nm
C
2
MOS
-
F
F
66.496
85.881
50.566
53.318
∆
T
d
%
29.15
5.86
TG-FF
41.811
48.755
35.517
36.517
∆
T
d
%
16.61
1.66
It can
be
o
b
se
rved
that
lea
k
ag
e p
o
w
er of
th
e
gate-le
ngth
biasi
ng Fli
p
-Flops h
a
s
decli
ned. Th
e avera
ge le
aka
ge p
o
wer of C
2
MOS-FF and
TG
-FF with o
p
timized
gate
-
l
engt
h
decrea
s
e
s
2
8
.57% and
11.49%, re
spectively. Th
e
clo
c
k-to-ou
t
time of th
e two struct
ure
s
increa
se
s 2
9
.15% an
d 16.
61%, re
spe
c
t
i
vely. The
se
tup time of t
he two st
ru
cture
s
in
crea
ses
5.86% and 1.
66%, respe
c
tively.
5.2. A 4-bit
Binar
y
Counte
r
w
i
th Gate-l
ength
Biasin
g
This
pa
rt we
de
sign
a
4-bit bina
ry co
unter
usi
ng D
Flip
-Flo
ps descri
bed
in 5.1.
The
stru
cture of a 4-bit bina
ry count
er i
s
presented in Figu
re 10.
Figure 10. A 4-bit Binary Counter
In Figure
10, combi
nation
a
l
gates a
s
for NAND gate
and AND gat
e impleme
n
te
d in this
desi
gn are using the gate-l
ength bia
s
ing
techniqu
e.
The size of the gates is sam
e
as in se
ctio
n
4.1. The
sim
u
lation i
s
carried
out
with
the freq
uen
cy of 5M at 4
5nm p
r
o
c
e
s
s tech
nology.
Th
e
active lea
k
ag
e power an
d clo
c
k-to-out d
e
lay are p
r
e
s
ented in Tabl
e 7 and Tabl
e
8, resp
ective
ly.
The average
leaka
ge po
wer
of 4-bit
binary
count
er u
s
ing
C
2
M
O
S and Tran
smissio
n
Gate D
Flip
-Flops
de
crea
se 38.36% a
nd
2
0
.05%,
res
p
ec
tively.
At the s
a
me
time, the c
l
ock
-
to-
out delay increase 24.43%
and 14.3
4
%, respe
c
tively.
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Vol. 12, No. 4, April 2014: 2565 – 2
573
2572
Table 7. Active leakage p
o
w
er of the 4
-
b
i
t binary cou
n
t
ers
Output
Active leakage p
o
wer(fW
)
C
2
MOS
-
counter
TG-counter
L=50nm
L=53nm
L=50nm
L=53nm
0000
254.9
167.9
169.76
134.71
0001
330.3
189.1
193
154.64
0010
309.8
181.4
164.8
129.8
0011
342.2
195.3
208.7
166.8
0100
251
169.8
169.5
134.5
0101
329.6
191.8
198.7
159.5
0110
306.3
191.4
166.6
130.9
0111
362.3
207.7
231.1
184.5
1000
253
170.2
172.1
137.4
1001
327
190.5
195.3
157.5
1010
309
185.5
167.9
133.7
1011
340
197.9
211.9
170.8
1100
253
175.8
174.6
140.2
1101
331
198.9
204.5
165.6
1110
313
203.5
177.5
141.7
1111
264
189
246.6
198
Average
304.775
187.856
190.773
152.516
∆
Power
%
-38.36
-20.05
Table 8. Clo
c
k-to
-out Dela
y of the 4-bit Binary Co
unt
ers
C
2
MOS
-
counter
TG-counter
L=50nm
L=53nm
L=50nm
L=53nm
T
d
(ps)
137.477
171.058
45.047
51.507
∆
T
d
%
24.43
14.34
Also, the total powe
r
an
d p
o
we
r-delay produ
ct
(or P
D
P) of the 4-bit
binary count
ers
are
pre
s
ente
d
in Table 9 an
d Table 10.
Table 9. Power Di
ssi
pation
of the 4-bit Binary Co
unte
r
s
C
2
MOS
-
counter
TG-counter
L=50nm
L=53nm
L=50nm
L=53nm
Power(pW
)
9.9563
7.1217
4.01556
3.4107
∆
power
%
-28.47
-15.06
Table 10. PDP of the 4-bit Binary Co
unt
ers
C
2
MOS
-
counter
TG-counter
L=50nm
L=53nm
L=50nm
L=53nm
PDP*10
9
(fJ
)
1368.762
1218.224
180.889
175.675
∆
PDP
%
-10.99
-2.88
The simul
a
tio
n
results sh
o
w
that the tota
l powe
r
dissipation of the counte
r
s de
cre
a
se
s
28.47% a
nd
15.06%, resp
ectively. The
PDP de
cr
ea
ses
10.99%
a
nd 2.8
8
%, re
spe
c
tively. T
he
PDP can b
e
con
s
id
ere
d
a
s
a quality measure fo
r a swit
chin
g dev
ice [13]. The
decrea
s
e in
PDP
mean
s the
p
e
rform
a
n
c
e i
n
crea
sing.
Th
erefo
r
e, th
e
o
p
timized
gate
-
length
bia
s
in
g is an
effecti
v
e
method to im
prove the pe
rforman
c
e of circuit
s
.
6. Conclusio
n
The g
a
te-l
en
gth bia
s
ing
te
chni
que
ha
s
discu
s
sed
by many
re
sea
r
che
r
s. A
ne
w method
to optimize the gate-l
eng
th is implem
ented in
this work. With
the optimized gate-l
eng
th
(L=53n
m), typical
com
b
in
ational an
d seq
uentia
l
ci
rcuit
s
are de
veloped a
n
d
simulate
d. The
HSPICE sim
u
lation re
sult
s sh
ow
that the leakage of
combin
ation
a
l logic ci
rcuits and sequ
en
tial
cir
c
uit
s
de
clin
ed wit
h
t
i
me
met
r
ic
s in
cr
e
a
sin
g
. Lea
ka
ge of ba
sic lo
gic gate
s
, 2
N
AND, 2
N
O
R
and
2XOR, d
e
cre
a
se
27.4%, 3
3
.6% and
18.
8%, re
spe
c
ti
vely. Mean
whi
l
e, delay of t
hem in
crea
se
s
11.36%, 12.83% and 4.
57%, resp
ectively. Two
stru
ctures of
adder, mirror add
er an
d
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
2302-4
046
Low L
e
a
k
ag
e
Circuits Desi
gn with Optim
i
zed G
a
te-le
n
g
th Biasing
(Xiaohui Fa
n)
2573
transmissio
n
gate ad
der decrea
s
e
1
3
.9% and 8.
9%. Along
with that del
ay of the ad
ders
increa
se
s 13.
12% and 6.9
2
%, resp
ectiv
e
ly.
In addition, sequ
ential
circuits like C
2
MOS D Fli
p
-
Flop and T
r
ansfe
r-Gate
D Flip-Fl
o
p
redu
ce the
leakag
e p
o
we
r 28.57
% and 11.49%,
respe
c
tively.
At the same
time, the clock-to
-
out time of them raises 2
9
.15
%
and 16.6
1
%,
respe
c
tively. A 4-bit bina
ry counte
r
with
different
stru
cture
s
d
e
cli
n
e the total po
wer
dissipati
on
28.47% and
15.06%, amo
ng them the leakage p
o
we
r dissipatio
n decrea
s
e 3
8
.36% and 20.
05%
,
respec
tively.
Otherwise, the c
l
o
ck-to-o
u
t
time of the 4-bit bi
nary cou
n
ters rai
s
es 24.43% a
n
d
14.34%, re
sp
ectively. The
results in
dica
te that it
is ef
fective for th
e stan
dby po
wer dissip
ation
redu
ction
of
ele
c
tro
n
ic equipm
ent with
the
o
p
timized
gate
-
l
ength. M
o
re
over, the
PDP i
s
decrea
s
e
d
when the sequ
ential circuit
s
work while
freque
ncy is 5
M
. It is also obvious for
sa
ving
power di
ssi
pa
tion while the
electroni
c eq
uipment is
wo
rkin
g in low-freque
ncy.
Ackn
o
w
l
e
dg
ements
Proje
c
t is suppo
rted
by Natio
nal
Natural S
c
ie
nce
Fou
nda
tion of
Chi
na (No
.
6127
1137
), Scientific
Re
se
arch Fun
d
of Zhejian
g
Pro
v
incial Edu
c
a
t
ion Dep
a
rtm
ent (No.Y2
01
32
9962
), and Ni
ngbo
Natural Scien
c
e Fo
un
dation (No. 2
011A61
010
2).
Referen
ces
[1]
Kavita Me
hta,
Neh
a
Arora, B
P
Sin
gh.
L
o
w
Pow
e
r Efficien
t D Flip Flo
p
Circuit.
Proc
ee
din
g
s of the
Internatio
na
l Symp
osi
u
m on
Devices MEM
S
, Inte
llige
n
t Systems & Com
m
unic
a
tion. 2
0
1
1
; 16-1
9
.
[2]
Ch Da
ya
S ag
ar
,
T
Krishna Moorth
y
.
Desi
g
n
of a Lo
w
Po
w
e
r F
lip-F
l
op
Using MT
CMOS
T
e
chniq
ue.
Internatio
na
l Journ
a
l of Co
mputer
Ap
pl
icati
ons & Informati
on T
e
ch
nol
ogy
.
2012; 1(1): 1
9
-
21.
[3]
Pune
et Gupta, Puneert Sharma. Gate
-Length Bi
asin
g
for Runtime-Leak
age C
o
ntrol
.
IEEE
T
r
ansactio
n
s o
n
Co
mp
uter
-Ai
ded D
e
sig
n
of Integrate
d
Circ
u
its and Syste
m
s.
20
06; 25(
8
)
: 1475-1
4
8
5
.
[4]
Pune
et Gupta,
Andre
w
B Ka
h
ng,
Pu
neet S
h
arma, De
nnis
S
y
lv
ester
.
Sel
e
ctive Gate-L
en
gth Bias
in
g for
Cost-Effective
Runti
m
e Le
akag
e Co
ntrol
.
Proceed
in
gs
of the Des
i
gn
Automati
o
n
Co
nferenc
e
(DAC’0
4). 200
4; 7(1
1
): 327-
3
30.
[5]
Amit
Agar
w
a
l, Saib
al Mukh
op
adh
ya
y
,
Ar
ijit
R
a
y
c
ho
w
d
h
u
r
y
,
Kauch
i
k Ro
y
,
Chris H.Kim.
Leaka
ge Pow
e
r
Analys
is and R
educti
on for na
nosca
le Circ
u
it
s
. IEEE Computer Societ
y
.
2
006; 26(
2): 68-
80.
[6]
A
Agar
w
a
l, S Mukhopa
dh
ya
y
,
CH Kim,
A
Ra
y
c
h
o
w
d
h
u
r
y
, K Ro
y
.
L
eaka
ge Pow
e
r
Analysis a
n
d
Red
u
ction: M
o
dels, Esti
mati
o
n
an
d T
o
ols.
IEE Procee
di
n
g
s on
Comp
ut
ers an
d Di
gita
l
T
e
chniq
ues.
200
5; 152(
3): 353-3
68.
[7]
Liqi
on
g W
e
i, Z
han
pin
g
C
hen,
Mark Joh
n
son
,
Kaushik
Ro
y
.
Desig
n
a
nd O
p
timi
z
a
ti
on of
Low
V
o
lta
g
e
High P
e
rfor
ma
nce Du
al T
h
res
hol
d CMOS Cir
cuits.
Procee
di
ngs of the D
e
si
gn
Automati
on
Confer
enc
e
(DAC’9
8). 199
8; 489-4
94.
[8]
Gang
Y
a
n
g
, Jin Liu.
An
Al
g
o
rithm for Qu
antitat
ive
l
y
C
a
l
c
ulati
ng I/Q Gain an
d Phas
e Mismatch.
T
E
LKOMNIKA
Indon
esi
an Jou
r
nal of Electric
al Eng
i
ne
eri
ng.
2012; 1
0
(4): 8
12-8
17.
[9]
Nara
n Sirisant
ana, Li
qio
ng
W
e
i, Kaushik
Ro
y
.
Hi
gh-P
e
rformanc
e Low
-Pow
er CMOS
Circuits Usi
n
g
Multipl
e
C
h
a
n
n
e
l L
e
n
g
th a
nd
Multipl
e
Oxid
e
Thickness
. Pro
c
eed
ing
of the
Internatio
na
l C
onfere
n
ce
o
n
Comp
uter Desi
gn (ICCD’
00).
200
0; 227-
232.
[10]
Amit
Agar
w
a
l,
Chris H Ki
m, Saibal M
u
kho
p
a
d
h
y
a
y
,
Kauchik R
o
y
.
Le
akag
e i
n
Nan
o
-Scal
e
T
e
chn
o
lo
gies:
Mechan
is
ms, Impact an
d
Desig
n
Co
n
s
ider
ations
. P
r
ocee
din
g
s of
the Desig
n
Automatio
n
Co
nferenc
e, (DAC’04). 2
004; 6-
1
1
.
[11]
Xi X,
Du
nga M,
He
J, et a
l
. BSIM4.6.4 MOSF
ET
model user
’
s
ma
n
ual.
A
v
ai
lab
l
e
in http://
w
w
w
-
devic
e.eecs.b
e
r
kele
y
.
ed
u/~
b
sim3/bsim4.
h
tml
.
[12]
Nare
ndra SG, Chandr
akas
a
n
A. Leaka
ge in nan
ometer
CMOS technol
ogi
es. Ne
w
Y
o
rk: Springer
.
200
6.
[13]
Jan M Ra
ba
e
y
,
Anant
ha C
han
drakas
am, Borivoj
e
Nik
olic. Di
gital In
tegrated
Circu
its:
A
Desig
n
Perspectiv
e
, Pearso
n Educ
ati
on, Inc,
Prentice-Hal
l
, Secon
d
Edition. 20
03.
[14]
M Janaki Ra
ni,
S Malarkann.
Leak
ag
e Po
w
e
r Reducti
o
n
an
d
Anal
ysis of CM
OS Seque
ntial Circ
u
its.
Internatio
na
l Journ
a
l of VLSI desi
gn
& Co
mmu
n
ic
ation Sys
t
ems (VLSICS
’
12).
201
2; 3(1)
: 13-23.
[15]
D Harikr
ishn
a, NV Srikant
h.
Dyn
a
mic Sta
b
il
ity En
ha
nceme
n
t
of Po
w
e
r S
y
stems Usin
g Ne
ural-N
et
w
o
r
k
Contro
lle
d Sta
t
ic-Compe
nsat
or
.
T
E
LKOMNIKA
Indo
nes
ian
Journ
a
l of El
ectrical En
gi
ne
erin
g
. 201
2;
10(1): 9-1
6
.
[16]
R Rama
nar
a
y
a
nan, N V
ija
ykr
i
shna
n, MJ Ir
w
i
n.
Char
acteri
z
i
ng Dyn
a
m
ic
an
d Le
akag
e Po
w
e
r Behavi
o
r
in Flip-Flo
ps
. Procee
din
g
of the 15th
Ann
ual I
EEE In
ternatio
nal ASIC/SOC
Confer
ence. 2
002.
[17] Deja
n
Mark
ovi
ć
, Borivoj
e
Nik
oli
ć
, R
obert W
.
Broderse
n.
A
nalysis
an
d D
e
sig
n
of L
o
w
-
Energy F
l
ip-
F
l
ops.
Procee
din
g
of the Internatio
na
l S
y
mp
osi
u
m o
n
Lo
w
Po
w
e
r Electronics
and Des
i
g
n
(ISLPED’0
1). 2001; 52-
55.
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