TELKOM
NIKA
, Vol.11, No
.11, Novemb
er 201
3, pp. 6706
~6
713
e-ISSN: 2087
-278X
6706
Re
cei
v
ed Ma
y 20, 201
3; Revi
sed
Jun
e
23, 2013; Accepted July 2
6
,
2013
Design of a New Intelligent Controller with Switch
Management
Guang
f
u Wa
ng
Sichu
an El
ectromech
anic
a
l In
stitute of Vocation a
nd T
e
chn
o
lo
g
y
, Pa
nzh
i
h
ua, Sichu
an, C
h
in
a, 617
000
e-mail: w
a
ng
gu
angfu
1
2
6
@1
2
6
.com
A
b
st
r
a
ct
T
h
is pap
er ha
s a study on a
new
intell
ige
n
t
Pr
ogra
m
mab
l
e Log
ic Co
ntro
ller b
a
sed
on i
ndustri
a
l
Ethernet
(IPLCbIE). It propos
es a complete
soluti
on f
o
r the target
segment: MMM, WWW, F&B, Medium
Hydro p
o
w
e
r. T
he scopes
of the soluti
on d
i
scusse
d in
thi
s
paper
are th
e process
and
field p
a
rt of th
e
IPLCbIE arc
h
i
t
ecture. F
o
r t
he
proc
ess p
a
rt the sc
op
e
of o
u
r
desi
g
n i
n
clu
des
th
e co
ntroll
ers,
the
eng
ine
e
ri
ng s
o
ftw
are tools (U
nity Pro)
an
d t
he
interfac
es
w
i
th the ot
her
equ
ip
me
nt
of t
h
is l
e
ve
l, typic
a
ll
y
other co
ntroll
er
s or tools
lik
e a
sset mana
ge
ment, SCAD
A
or
OPC server. S
a
fety an
d HSB
Y
control
l
ers
are
also part of our design. For the
field part, the scope of our progr
am
inc
l
udes the remote I/Os and the
interfaces with the other e
quipm
ent of this level, typically
dist
ribut
ed I/Os & devices. In this paper, we
m
a
ke
a study
on the des
ign of the
controller. It includes th
e syst
em arc
h
itectur
e
of IPLCbIE, t
he
applic
ation
of
netw
o
rk mod
u
l
e
. And
it focus
e
s on
the
disc
ussio
n
of
d
e
si
gn for th
e ker
nel
mod
u
le
of
the PLC-
netw
o
rk
mo
du
le NOC.
Our des
ign
a
l
so i
n
clu
des t
he i
n
terfac
es
w
i
th the op
era
t
ion &
mana
g
e
ment to
ols.
T
h
e
hardw
are d
e
si
gn is esp
e
ci
ally
introduc
ed i
n
detai
l in
my pa
per.
Ke
y
w
ords
:
PL
C, industri
a
l et
hern
e
t, sw
itch
ma
na
ge
me
nt
Copy
right
©
2013 Un
ive
r
sita
s Ah
mad
Dah
l
an
. All rig
h
t
s r
ese
rved
.
1. Introduc
tion
No
wad
a
ys,
more
and m
o
re n
e
two
r
k
appli
c
ation
s
,
su
ch a
s
d
a
ta dist
ribution
,
distant
edu
cation
an
d dist
ributed
databa
se,
wo
rk
on the Eth
e
rnet
com
m
u
n
icatio
n mod
e
. For th
e future
merg
e of ne
tworks, th
e
comp
uter
ne
twork n
eed
s the ca
pabili
ty to suppo
rt the traditio
nal
indu
strial me
ssage b
r
oa
dcast bu
sine
ss. So how
to suppo
rt the field bus
comm
unication ba
se
d
on Ethe
rnet i
n
the i
ndu
stri
al net
wo
rk is
the net
re
se
a
r
ch
er’
s
im
po
rtant di
re
ction.
Ethernet i
s
th
e
most
com
m
o
n
Intran
et an
d a
c
cess
net
work. P
r
eviou
s
Ethe
rnet i
s
a net
work
sh
ared
by all
ho
sts.
It can’t supp
o
r
t the grou
p communi
catio
n
[1-3].
The Intelligen
t PLC Control
l
er ba
sed o
n
Industri
a
l Ethernet (IPL
CbI
E
) is a ne
w p
r
odu
ct
desi
gn for th
e differe
nt module
whi
c
h
mates
with
in
dustri
a
l PL
C
platform
s respectively. Th
ese
desi
g
n
s
sha
r
e a
comm
on
hardware
a
r
chite
c
ture
wh
ich
will
sup
p
o
rt both
the
Modbu
s P
r
ot
ocol
and the Control and Inform
ation Proto
c
ol
(CIP) a
s
sp
e
c
ified by the ODVA [4].
The
goal
of t
he IPL
C
bIE i
s
to
provide
a
co
mplete
sol
u
tion fo
r the
target
segme
n
t: MMM,
WWW, F&B, Medium Hy
dro po
we
r. IPLCBIE C
ont
rol Platform
prog
ram a
d
d
r
ess the Pro
c
e
ss
Control and t
he Di
screte Control b
r
icks of this offer.
It is a co
ntro
l colution
ali
gned
with th
e end u
s
e
r
strategy, delivering val
ue t
o
our
5
targeted
verti
c
al
s, taki
ng
care of
our i
n
stalle
d
ba
se
. It provide
s
a mid/lon
g
t
e
rm
sol
u
tion
to
sub
s
titute Premium & middle ran
ge pla
tforms. Du
e
to
IN
T
E
L
mic
r
o
-
pr
oc
es
so
r
o
b
s
o
l
es
ce
nc
e, i
t
rationali
z
e
s
t
he e
nd
use
r
rang
e p
o
rt
folio, and
ta
ke
s a
d
vanta
ge of
re
ne
wal to
redu
ce
developm
ent & maintenan
ce co
sts.
The scope of
the solution
we will di
scuss i
s
the process and fiel
d part of the IPLCbIE
architectu
re.
Our
de
sign
a
l
so i
n
clu
d
e
s
t
he inte
rfaces with th
e op
e
r
ation &
man
ageme
n
t tool
s.
For th
e p
r
o
c
e
s
s pa
rt the
scope
of ou
r p
r
ogra
m
in
clu
d
e
s th
e
control
l
ers,
the e
ngi
neeri
ng
software
tools (Unity Pro) an
d the
interface
s
with the
oth
e
r equi
pment
of this level, typically other
controlle
rs
o
r
tool
s like
asset ma
nag
ement, SCA
D
A o
r
OP
C se
rver. Saf
e
ty and
HS
BY
controlle
rs a
r
e al
so
pa
rt of
ou
r d
e
si
gn.
For
t
he field part, the sco
pe of our pro
g
ram in
clud
e
s
the
remote I/O
s a
nd the inte
rfa
c
e
s
with th
e
other
equip
m
ent of this l
e
vel, typically di
stribute
d
I/Os &
devices. In this paper,
we
will make
a
study on the design of
IPLCbIE. It includes the
system
architectu
re
o
f
IPLCbIE, th
e ap
plication
of netwo
rk m
odule. An
d it
focu
se
s o
n
di
scussio
n
of t
h
e
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
e-ISSN:
2087
-278X
De
sign of a New Intellige
n
t Controlle
r wit
h
Switch Ma
n
agem
ent (Gu
angfu Wang
)
6707
desi
gn of the
most imp
o
rta
n
t module
–ne
twork mo
dule
NO
C. The
h
a
rd
wa
re d
e
si
gn is i
n
trod
uced
in detail in my paper.
2. IPLCbIE Sy
stem Architecutr
e
The IPL
C
bIE system
a
r
ch
itecture
is sh
ow
n
in Fi
gure 1. Th
e n
e
w d
e
sig
n
in
cl
ude
s a
seri
es of
com
pone
nts of PLC controll
er:
M5xx new CPU module
s
- A new ran
g
e
of CPUs
wi
ll suppo
rt the new feature
s
of the
s
o
lution.
The CRP function will be integrated in
CPU M5x
x
. The CID/CIM service
will also
available with
CPU M5xx, but only for local ra
ck [5-8].
Network mo
dule
s
-
The
new soluti
on in
clud
es 3 ne
w n
e
twork m
odul
e
s
: CT
RL
Facto
r
yca
s
t NO
C for Co
ntrol man
age
s the inte
rfa
c
e with the
control network
and p
r
ov
ides
routing
capa
bilities
betwe
en the
control net
work
a
nd two oth
e
r inde
pen
dent
su
b-netwo
rks. 1
Facto
r
yca
s
t
Gene
ric NO
C a
nd
1 n
o
n
-
Fa
ctory
c
a
s
t
Gene
ric NO
C fo
r
Distri
b
u
ted I/Os ma
nage
stand
ard Eth
e
rnet devi
c
e
s
and also pro
v
ide
Unity co
nne
ctivity to
CPU via Ethe
rnet.
X80 I/O Drop
s ada
pters – This solution
inclu
d
e
s
a ne
w dro
p
’s a
d
a
p
tors: a ne
w
module
BME CRA
all
o
ws the
conn
ection
on
the
device
& I/Os Ethern
e
t net
work
of a
dro
p
in
cludin
g
o
ne
or two racks of X80 modul
es. Thi
s
CRA is
com
patible
with Ethernet
Backpl
ane [9
].
M5xx ne
w E
DRS
mod
u
le
-
Thi
s
soluti
on in
clu
d
e
s
all the
equi
p
m
ent a
nd
acce
ssorie
s
need
ed to
b
u
ild the vali
d
a
ted top
o
logi
es
of the
Co
ntrol n
e
two
r
k and th
e
De
vice I/O net
work.
EDRS is
sho
r
t for Integrat
ed Du
al Rin
g
Switch. A ne
w mod
u
le BME EDRS all
o
ws: To su
pp
ort
both DIO
& RIO on the
sa
me phy
sical n
e
twork [1
0];
Con
n
e
c
t a
su
b-ri
ng of IO
d
e
vice
s, in a
Daisy
Chai
n Loop, t
o
the RIO Ma
in Ring; Com
patible with E
t
hernet rack.
Unity Pro V8.0 - A new release of Unity pr
o will provide all the necessary specifi
c
softwa
r
e tool
s to De
sig
n
, Config
ure,
Commissio
n,
Operate an
d maintain the
Controlle
r, its I/Os
and the man
a
ged devi
c
e
s
.
Figure 1. IPLCbIE System Archite
c
ture
3. Applicatio
n of Ne
t
w
o
r
k
Module
The NOC
co
ntrol he
ad m
odule i
s
main
ly resp
on
sible
for providi
ng
netwo
rk t
r
an
spare
n
cy
betwe
en dev
ice
s
located
on a devi
c
e
netwo
rk
(i
n
c
ludi
ng remo
te I/O and/or distrib
u
ted I
/
O
device
s
), an
extended d
i
stribute
d
I/O network
, a
nd a cont
rol
network, while pre
s
e
r
ving
determi
nism f
o
r rem
o
te I/O device
s
on the device net
work.
In ou
r n
e
w n
e
twork mod
u
l
e
, it ope
rate
s in a
redu
nd
ant net
work that u
s
e
s
the
RSTP
proto
c
ol. It configures IP para
m
eters
a
nd d
e
vice
co
nfiguratio
n fil
e
s fo
r I/O d
e
v
ices. It
sup
p
o
rts
Hot Stand
by function
ality. It operate
s
with
other
EIO
head mod
u
l
e
s (CRP,
NO
C) or ope
rat
e
s
without
bein
g
interlin
ke
d
wi
th these h
ead
modul
es
on
the lo
cal
ra
ck. Figu
re
2 i
s
t
he
con
n
e
c
tio
n
s
example b
e
twee
n device
s
. This
exam
ple sh
ows
th
e maximum
cabl
e length
s
betwee
n
re
mote
I/O and distri
buted I/O device
s
and a
co
ntrol network
in an EIO inst
allation [11].
Evaluation Warning : The document was created with Spire.PDF for Python.
e-ISSN: 2
087-278X
TELKOM
NIKA
Vol. 11, No
. 11, Novemb
er 201
3: 670
6 – 6713
6708
In the Figu
re
2, 1 is
CRP remote I/O
head
modul
e
,
2 is
NO
C
distrib
u
ted I/
O hea
d
module
interli
n
ke
d
with the
CRP m
o
d
u
le, 3 i
s
NO
C
control h
e
ad mo
dule
in
terlinked
with
the
NO
C mod
u
le
on the lo
ca
l ra
ck. 4 i
s
distrib
u
t
ed I/
O su
b-ring.
5 is d
ual-rin
g switch
(DRS)
config
ure
d
fo
r copp
er-to-fi
ber and
fibe
r-to-cop
per
transitio
n o
n
t
he mai
n
ring
(conn
ectin
g
the
distrib
u
ted I/O su
b-ring a
n
d
the dist
ribut
ed I/O clou
d to the main
ring). 6 i
s
dist
ri
buted I/O clo
ud,
7 is rem
o
te I/O dro
p
on th
e main rin
g
. 8 is rem
o
te I/O drop
s on
the remote I/
O sub
-ri
ng. 9
is
DRS
on the
main ri
ng
(conne
cting th
e rem
o
te I/O
sub
-ri
ng to
the main
rin
g
). 10 i
s
co
n
t
rol
netwo
rk
(con
necte
d by the 140 NO
C 78
1 00 modul
e).
11 is main ri
ng.
Figure 2. Con
nectio
n
s of Network Mo
dul
es
4. Hard
w
a
re
Design
The de
sign u
s
e
s
the same
platform as u
s
ed by the Casp
er EtherNet module
s
wi
th a few
cha
nge
s. Me
mory si
ze ha
s bee
n increa
sed to
32
MB Flash
and 32
MB SDRAM
and the ad
dition
of a Ma
rvell
88E616
5 mul
t
i-port Ethe
rNet Swit
ch.
The m
odul
es ha
s fou
r
1
0
/
100 p
o
rts.
T
he
pro
c
e
s
sor an
d mem
o
ry
archite
c
ture
a
r
e
sche
mati
call
y identical
with ea
ch
havin
g its o
w
n
uni
que
backpl
ane int
e
rface [12].
As sho
w
n in
Figure 3, an
MPC87
0
13
2
M
hz
pro
c
e
ssor ma
nipul
ates d
a
ta bet
ween the
backpl
ane, lo
cal mem
o
ry
and EtherNet
Switch. On
power up
co
de sto
r
ed in
Flash i
s
mirrored
and exe
c
ute
d
from SDRAM providing
a faster ex
e
c
ution time. Ethernet traff
i
c is exchan
ged
betwe
en the
870 internal
MAC and ext
e
rnal Ethe
rNet Switch with
integrated P
H
Y’s.
Figure 3. NO
C Overvie
w
Figure
4. Ethernet Interfa
c
e De
sign
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
e-ISSN:
2087
-278X
De
sign of a New Intellige
n
t Controlle
r wit
h
Switch Ma
n
agem
ent (Gu
angfu Wang
)
6709
The Ethernet
desig
n is th
e most imp
o
r
tant part of
netwo
rk m
o
d
u
le NO
C [13
]. The
desi
gn is
sho
w
n in Figu
re
4.
4.1. MPC870
Process
or
Compl
e
te d
e
f
inition of thi
s
sub
-
sy
stem
, comp
one
nt or fu
nctio
n
(De
s
ig
ned
fu
nction
s,
Interface de
scriptio
n, Op
erating mo
de
with se
que
nce
diagram
s, So
ftware
so
urce
co
de l
o
catio
n
,
Mat
e
rial cha
r
act
e
ri
st
ic
s,
B
O
M,
….
)
The p
r
o
c
e
s
so
r is a
32bit
Freescal
e
MP
C870 i
n
tegrate
d
commu
nica
tions co
ntroll
er with
the co
re
ope
rating at 13
2M
Hz
and th
e e
x
ternal
bu
s
o
peratin
g in
2:1 mod
e
or 66
MHz. Em
bed
ded
is 8KB of I-Cach
e an
d D-Ca
che, three
memo
ry
con
t
rollers (GPM
C/UPMA/UP
M
B), two 1
0
/100
FEC
cont
roll
ers (Fa
s
t Eth
e
rnet
Controll
er),
one
SM
C (no Hand
shake) Seri
al Controlle
r, JT
AG
controlle
r, BDM (Ba
c
kgro
u
nd Debu
gge
r) an
d mult
ipl
e
pro
g
ra
mmab
l
e gen
eral pu
rpo
s
e I/O.
Co
re
power supply
is 1.8V with 3.3V I/O.
1
)
C
l
ock
G
e
ne
r
a
tio
n
Compl
e
te d
e
f
inition of thi
s
sub
-
sy
stem
, comp
one
nt or fu
nctio
n
(De
s
ig
ned
fu
nction
s,
Interface de
scriptio
n, Op
erating mo
de
with se
que
nce
diagram
s, So
ftware
so
urce
co
de l
o
catio
n
,
Mat
e
rial cha
r
act
e
ri
st
ic
s,
B
O
M,
….
).
On po
wer u
p
the MODCLK
[1:2] pins are
sample
d [1:0] using pull
-
u
p
/pull-d
o
wn resi
stors
whi
c
h
config
u
r
es the inte
rn
al PLL in
1:1
mode u
s
in
g t
he extern
al o
scill
ator frequ
ency of 5
0
Mh
z.
Core
and
bu
s frequ
en
cy remain
at 5
0
M
hz until
th
e
BootRom
re
config
ure
s
th
e PLL
for 13
2Mhz
core with the
bus o
perating
in 2:1 mode or 66M
hz.
2) Memory (F
lash & SDRAM)
BootRom an
d Executive cod
e
is store
d
in
16bit wide (32MB
)
Flash u
s
ing S
pan
sion
Mirro
rBit Fla
s
h. On po
we
r
up the
cod
e
image in
Fla
s
h is u
n
comp
ressed i
n
to 32
bit wide
(32M
B)
SDRAM p
r
ovi
d
ing faste
r
ex
ecutio
n times. Options
h
a
ve been
provid
ed to su
ppo
rt large
r
mem
o
ry
den
sities.
3) Memo
ry Controlle
r & Wait States
Thre
e me
mo
ry controll
ers
GPMC, UP
MA,
UPMB are
used
to
acce
ss mem
o
ry an
d
perip
he
rals.
The GPMC i
s
used for Fl
ash, UPMA
i
s
used for SDRAM an
d UPMB is use
d
to
acce
ss the b
a
ckpla
ne GP
X ASIC on the PETC an
d MNO
C
. See sectio
n on
UPM control
l
er.
Initially Flash
or CS0 i
s
co
nfigure
d
for 3
0
wait
state
s
.
Wait state “TA”
flag (T
erminate Cy
cle
)
is
determi
ned b
y
setting the “ORx” regi
ster “SETA” bit.
4) UPM Me
m
o
ry Cont
rolle
r
The
870 UP
M (User Programmable
Memory Ma
chine A&B) is
an internal 64x32 bit
wide
memory a
r
ra
y who
s
e bit
s
are di
re
ctly mappe
d to
CS,
BS[0:3] and GPL[0:5] out
put pin
s
u
s
ed
to
multiplex the control inputs on SDRAM or GPX3
. Freescale provides an
MP
Cinit utility
(MPC860
UPM Pro
g
ra
mming To
ol)
that grap
hical
l
y displays th
e UPM a
r
ray values a
nd
waveforms
with
edit capability
.
Source file i
s
a
“.mgp” tex
t
file, output
i
s
a
“.s” text file. To generat
e
the output fi
l
e
sele
ct “cod
e
gene
ration
” “orde
r
e
d
”. At the en
d of
thi
s
“.
s” file i
s
a
UPMA/B table that FW
can
paste into the
BootRom co
de.
5) Ethern
e
t 6165 Switch
Compl
e
te d
e
f
inition of thi
s
sub
-
sy
stem
, comp
one
nt or fu
nctio
n
(De
s
ig
ned
fu
nction
s,
Interface de
scriptio
n, Op
erating mo
de
with se
que
nce
diagram
s, So
ftware
so
urce
co
de l
o
catio
n
,
Mat
e
rial cha
r
act
e
ri
st
ic
s,
B
O
M,
….
)
Figure 5
is th
e de
sig
n
of
switch
interfa
c
e.
A Ma
rvell
88E616
5 m
u
l
t
i-port
Giga
bit Switch
with five inte
grated Eth
e
rNet triple
sp
e
ed
(1
0/100/1
000) P
H
Y’s i
n
MII PHY Mode (or
Reve
rse
MII) will
com
m
unicate
with
the 8
70
pro
c
essor. In
all
3
modul
es the
Ethernet Po
rt
s
will op
erate
at
10/100M
bp
s and the MII bus at 25Mh
z
.
A 25Mh
z
cry
s
tal i
s
multipl
i
ed by the
in
ternal PL
L p
r
oviding all
n
e
ce
ssary
clo
c
ks. O
n
power
up
an
870
GPIO p
i
n hold
s
th
e
6165
in
Re
set while
it co
nfigure
s
th
e i
n
ternal
re
gist
ers.
Thre
e po
we
r
sup
p
lie
s a
r
e
necessa
ry, 1.0V for t
he
Co
re, 1.8V fo
r the EtherNet
PHY’s a
nd
2.5V
for I/O. MII RXD
data
uses
a 2.5V to
3.3V (LV
C
8T245) level
shifter to meet the (Vih) input
requi
rem
ents of the 870
pro
c
e
s
sor, M
II TXD is 3.
3
V
tolerant al
ong
with the
other I/O con
t
rol
pins.
Evaluation Warning : The document was created with Spire.PDF for Python.
e-ISSN: 2
087-278X
TELKOM
NIKA
Vol. 11, No
. 11, Novemb
er 201
3: 670
6 – 6713
6710
Figure 5. Switch Interfa
c
e
4.2. CPLD/F
PGA Progra
mmable Dev
i
ces
1) CPL
D
A Lattice LC4
064ZE with
3
.
3VIO and 1.
8V core cont
ains lo
gic m
o
deled in Ve
ril
og afte
r
the Loki Pre
m
ium pro
c
e
s
sor to GPX interface u
s
i
ng Lattice Cl
assic V1.2 to
ols. Devi
ce is a
5.8ns d
e
vice
with a TjMax of 105°
C and
packa
ged in
a 100T
QFP.
2) XP2-3
0 FPGA
A Lattice
LF
XP2-30E
wit
h
3.3VIO/1.2
V co
re
conta
i
ning lo
gic a
nd du
al p
o
rt
memo
ry
modele
d
in
V
e
rilog
after th
e
NOE7
71
p
r
ocesso
r to
L
M
S ASIC int
e
rface
usi
ng
Lattice i
s
pP
RO
V7.2 tools. The device o
n
chip flash
co
nfigure
s
the i
n
ternal S
R
a
m
array in 2
m
s. Device h
a
s a
TjMax of 100
°C with 2
00 I/O packa
ged i
n
a 256BGA.
3) FPGA Inst
antiated Dual
Port Memory
Instantiated i
n
ternally is two 2KB synchr
on
ou
s clo
c
ked du
al port
memorie
s
. The 870
CLKOUT i
s
used to clock t
he mem
o
ries
at 66M
Hz
,
thus CPU writes
on
the falling edge and t
he
LMS ASIC write
s
on th
e risi
ng ed
g
e
. Contentio
n whe
n
both
side
s acce
ss sa
me ad
dress
simultan
eou
sl
y no long
er
e
x
ists a
s
ea
ch
side i
s
clo
c
ked on
differe
nt edge
s. Thi
s
elimin
ates the
dual port bu
sy
flag
which
i
n
se
rted wait states
a
s
p
r
e
s
ente
d
to th
e
870
“TA” inp
u
t. Thus the
O
R
3
SCY field sho
u
ld be set for 2 wait state
s
and the SET
A bit set for internal TA.
Figure 6. Dua
l
Port Memory Backpla
ne Interface
Figure 6 is th
e de
sign of d
ual po
rt mem
o
ry
ba
ckplan
e interfa
c
e. T
he dual
port
memory
clo
ck e
nabl
e
or the inte
rna
l
dual po
rt chi
p
enabl
e
are
acce
ssi
ble on
two external
pins
with pull
-
ups for de
bu
g. When
a
c
tive high
indi
cates
a
rea
d
o
r
write
cy
cle i
s
in
p
r
og
re
ss. CLKE
NA o
n
Pin
K16 o
r
R15
9
indi
cate
s
Read/Write to
CPU Side &
CLKE
NB o
n
Pin K1
4 o
r
R15
8
in
dicates
Read/Write to LMS ASIC Si
de.
4) FPGA In-Circ
u
it Program
The FPGA on
board flash m
a
y be prog
ra
mmed in thre
e ways, a
s
is
sho
w
n in Fig
u
re 7.
a. Lattice HW-USBN-2A in
-circuit do
wnlo
ad ca
ble u
s
in
g Deb
ug Card.
b. FPGA SPI
in Slave Mod
e
to 870 SPI in Maste
r
Mod
e
.
c. FPGA is d
o
wnl
oade
d u
s
ing 8
70 GPIO runni
ng an
embed
ded ve
rsio
n of VM.
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
e-ISSN:
2087
-278X
De
sign of a New Intellige
n
t Controlle
r wit
h
Switch Ma
n
agem
ent (Gu
angfu Wang
)
6711
Figure 7. FPGA On Board
Progra
m
4.3. FPGA Step2
w
i
th Inte
grate
d
Proce
ssor
To enha
nce backpl
ane p
e
rform
a
n
c
e a
larger FPG
A
(XP2-30
)
has b
een sel
e
cted in
orde
r to
in
corpo
r
ate
an
embed
ded
p
r
ocesso
r
and
asso
ciate
d
prog
ram/d
a
ta
memo
ry a
s
a
se
con
dary p
r
oject, a
s
is
shown in Fig
u
re 8.
Thi
s
impl
ementation
would em
bed
a
Lattice Mi
co
32
IP processo
r
whi
c
h
woul
d
be field u
pgra
deabl
e [
14]. T
he ne
w al
gori
t
hm woul
d be
downloa
ded
to
the FPGA u
s
i
ng eithe
r
the
SPI bus o
r
an
embe
dded
versi
on of th
e
Lattice i
s
pVM
system
ru
nni
ng
on the 8
70. S
hould
a mo
du
le never de
sire this o
p
tion t
hen a l
o
wer
cost XP2-5 in
a 256B
GA ca
n
be used in its place
and
would impl
eme
n
t only the ba
si
c d
ual p
o
rt i
n
terface. Thi
s
will req
u
ire the
sou
r
ce code
to be re
co
m
p
iled for th
e
smalle
r d
e
vice. I/O pins
were
cho
s
e
n
from the XP2
-5
device to in
su
re ba
ckwa
rd
s compatibly.
Figure 8. FPGA Step2 with Mico3
2
Pro
c
e
s
sor
4.4. Po
w
e
r S
upplies & Re
set
Figure 9 i
s
the de
sig
n
of
power
su
ppl
y. Mu
ltiple p
o
we
r rails
are re
quired to
sup
port
device
s
with l
o
w voltage core
s alon
g wi
th inru
sh cu
rrent manag
em
ent on power
up or hot swa
p
.
All 3 d
e
si
gn
s
sha
r
e
sim
ilar
power supply a
r
chit
e
c
ture
s with
some
slight
variation.
T
w
o
synchro
nou
s buck regul
ato
r
s (Int
ersil ISL910
5 @600
ma & ISL801
2 @2A)
with
integrate
d
fet
s
along
with a linear
reg
u
lato
r (TI TPS793
01 @2
00m
a)
are in
co
rpo
r
a
t
ed.
On p
o
wer
up
there
i
s
a
soft start
R/C
controlled
PF
ET that cha
r
ges a
100
uf tantalum
cap to 5 volt
s. On
ce the
voltage monit
o
r (TI TPS38
08)
sen
s
e
s
t
he ca
p volta
ge at 4.65V
for
20ms it then
enabl
es all p
o
we
r supplie
s sim
u
ltane
o
u
sl
y. The swi
t
ching
reg
u
lat
o
rs
(3.3, 1.8, 1.2,
1.0V) all hav
e a 1ms
built in soft sta
r
t and the linea
r
regul
ator
(2.5
V) tracks the
3.3V rail. On
ce
the re
gulato
r
s have
re
ach
ed ap
prox
ima
t
ely 90% of there
outp
u
t voltage the
int
e
rnal
PG (P
o
w
er
Good
) output
s a 210m
s Po
wer
OK sign
a
l
input to the pro
c
e
s
sor.
Evaluation Warning : The document was created with Spire.PDF for Python.
e-ISSN: 2
087-278X
TELKOM
NIKA
Vol. 11, No
. 11, Novemb
er 201
3: 670
6 – 6713
6712
Figure 9. Power Su
pply
5. Conclusio
n
s and Pers
pectiv
e
In this pape
r, we prop
ose
d
a new sol
u
tion to aim the pro
c
e
ss
and field part of th
e
intelligent PL
C (P
rog
r
am
mable
Logi
c Cont
rolle
r)
based in
du
strial Ethe
rnet.
It is a
com
p
lete
solution for the target segment: MMM, WWW,
F&B, Medium Hydro power. We
have discussed
the interfa
c
e
s
with the o
p
e
r
ation & m
a
n
ageme
n
t
tool
s. For the p
r
oce
s
s pa
rt th
e scop
e of o
u
r
desi
gn i
n
cl
ud
es th
e
cont
ro
llers,
the
eng
ineeri
ng
so
ft
ware to
ols (Unity Pro
)
a
nd the
inte
rface
s
with the other equipme
n
t of this level, typ
i
cally
other
controlle
rs or tools li
ke a
s
se
t managem
en
t,
SCADA or OPC server. Safety and
HSBY controllers are al
so part
of our desi
gn. For the field
part, the
sco
pe of
ou
r p
r
ogra
m
in
clu
d
e
s th
e
remot
e
I/Os and
t
he inte
rfaces with th
e oth
e
r
equipm
ent of this level, typically di
strib
u
ted I/O
s & device
s
. In this pap
er, we make
a study
on
the desi
gn of
the controlle
r. It include
s
the system
a
r
chite
c
tu
re of
IPLCbIE, the appli
c
ation
of
n
e
t
w
o
r
k
modu
le
. An
d
it foc
u
s
e
s
on
th
e d
i
sc
uss
i
on
o
f
desi
gn fo
r t
he
kernel
mo
dule
of the P
L
C-
netwo
rk mod
u
le NOC. T
h
e ha
rdware d
e
sig
n
is
es
pe
cially intro
d
u
c
ed in d
e
tail in
my pape
r. T
h
e
main pu
rpo
s
e of the NO
C module i
s
to provide tra
n
s
pa
ren
c
y bet
wee
n
the co
n
t
rol network, the
device n
e
two
r
k, an
d an e
x
tended di
stributed I/O
network, whil
e
pre
s
ervin
g
device n
e
two
r
k
determi
nism.
In a
ddition,
the NOC mo
dule
also p
r
o
v
ides
se
rvice
s
to
commu
n
i
cate
with
PL
C
appli
c
ation
s
runnin
g
o
n
th
e control n
e
twork. All
of
a
bove h
a
s be
e
n
verifie
d
a
n
d
validated
in
our
tes
t
for the produc
t.
Referen
ces
[1]
Qian Z
h
a
ng, Q
u
ji Gu
o, Qian
g
Ni, W
e
n
w
u Z
h
u, Ya-Q
in Z
h
a
n
g
. Source
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ap
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a
yer
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lticast
alg
o
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de
o distrib
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[2]
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w
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l
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unications
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y
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n
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b
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r
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m
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odi
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a
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r
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Internatio
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a
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a
n
j
ul
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ir.
Ban
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dth D
e
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it
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eter Bas
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n
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puti
n
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Comm
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ut
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E
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Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
e-ISSN:
2087
-278X
De
sign of a New Intellige
n
t Controlle
r wit
h
Switch Ma
n
agem
ent (Gu
angfu Wang
)
6713
[10]
PitchaiV
ija
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Karup
p
a
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y
c
ontro
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b
a
s
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h
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n
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e
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i
n
e
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rs.
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E
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[11]
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a
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beh
avi
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RLC
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Internati
ona
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Confer
enc
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e
t
w
ork a
n
d
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