TELKOM
NIKA Indonesia
n
Journal of
Electrical En
gineering
Vol. 12, No. 11, Novembe
r
2014, pp. 77
2
1
~ 772
7
DOI: 10.115
9
1
/telkomni
ka.
v
12i11.65
12
7721
Re
cei
v
ed
Jul
y
21, 201
4; Revi
sed Aug
u
st
24, 2014; Accepted Sept
em
ber 10, 20
14
A New Low-Costing QC-LDPC Decoder for FPGA
Zhao Han
1
, M.R. Anjum*
2
1
School of Info
rmation Sci
enc
e and T
e
chno
l
o
g
y
, Jina
n Uni
v
ersit
y
, Gua
n
g
z
hou,
Guang
do
ng Pr
ovinc
e
, 510
632
, China
2
School of Info
rmation & Elect
r
onics, Be
i
jin
g Institute of T
e
chno
log
y
,
Beiji
ng, Ch
in
a. 100
08
1.
*Corres
p
o
ndi
n
g
author, e-ma
i
l
: 3286
23
033
@
qq.com
A
b
st
r
a
ct
Based o
n
the
Genera
l
i
z
e
d
Di
stributive L
a
w
and th
e
featur
es of F
P
GAs,
th
is pap
er pro
poses
a
new
strategy for i
m
pl
e
m
e
n
tation
of Low
-Co
s
ting QC-L
DP
C Dec
oder
on
F
P
GA platform. W
e
get this n
e
w
strategy fro
m
t
he Ge
nera
l
i
z
e
d
Distri
butive
Law
, w
h
ich
is
prop
osed
to d
e
scrib
e t
he
be
l
i
ef pro
p
a
gatio
n
on
grap
hs. An
d us
ing
this
new
str
a
tegy
a
low
-
co
sting (
256
0, 1
0
24)
LDPC
d
e
c
oder
is
i
m
pl
e
m
ented
o
n
a
Xi
li
nx
Virtex-4 FPGA. Results show that
this n
e
w
strategy can
make
go
od
u
s
e of th
e p
e
rformanc
e of
L
D
P
C
codes, eve
n
th
oug
h it nee
ds l
e
ss resourc
e
.
Ke
y
w
ords
:
LD
PC deco
der, lo
w
-
costing, gen
erali
z
e
d
d
i
strib
u
tive law
,
F
P
GA
Copy
right
©
2014 In
stitu
t
e o
f
Ad
van
ced
En
g
i
n
eerin
g and
Scien
ce. All
rig
h
t
s reser
ve
d
.
1. Introduc
tion
Low
-D
en
sity
Parity
-Ch
e
c
k
(L
DPC
)
C
o
d
e
s
we
re
first
prop
osed by
R.G. Galla
ge
r [1] in
1963 an
d re
d
i
scovere
d
by David J.
C. Mackay [2
] in
1996. L
D
PC
Cod
e
s ha
s b
een attra
c
tin
g
a
large
amo
unt
of attention
sin
c
e th
en b
e
ca
use
of th
e go
od e
r
ror-co
rrectin
g
p
e
rform
a
n
c
e
a
n
d
parall
e
l d
e
co
ding. M
o
re
over, ma
ny
sta
ndards
have
adopte
d
L
D
P
C
cod
e
s
a
s
cha
nnel
codi
ng,
such as IEEEStd802.16, CCSD
S 131.1-O-2 and etc.
In pra
c
tical i
m
pleme
n
tatio
n
s
of many
e
rro
r-
co
ntrol a
nd signal
p
r
o
c
e
ssi
ng syste
m
s,
field
prog
ram
m
abl
e gate
array
s
(FPGA
s
) are
wid
e
ly us
ed
becau
se it
ca
rrie
s
m
any a
d
vantage
s. A
s
the de
sign of
high throug
h
put and lo
w-costing
LD
P
C
decode
r is i
n
great n
eed,
more
and m
o
re
LDPC d
e
cod
e
rs
con
s
truct
ed on FPGA
s are de
si
gn
e
d
. Reference
[3] propo
sed
implementati
o
n
of a low
c
o
mplexity s
o
ft-input soft output (SISO)
LDPC
de
co
de
r. With (100
8,5
04) LDP
C
co
des,
the co
sts
of the L
D
PC d
e
coder
are 11
0
9
logi
c elem
e
n
ts an
d 21
0,944
RAM bits. In[4], a flexible
partially-paral
lel LDPC Decoder i
s
pro
p
o
s
ed, and
it achieved 50M
b
p
s thro
ugh
put
with the use of
2,778 sli
c
e
s
and 29 Blo
ck RAMs on a
Virtex-2 FP
G
A
. Moreover,
a stru
cture for LDP
C
de
co
der
for long
co
de
length an
d i
s
propo
se
d i
n
[5], in
which impleme
n
ts a (95
36, 47
68) d
e
code
r
with
the u
s
e
of 3
4
127 l
ogi
c el
e
m
ents an
d 1
02RAM
s.
So
desi
gning
a
FPGA
ba
se
d,
low-co
sting and
pra
c
tical L
D
P
C
de
cod
e
r is
necessa
ry.
In this pa
per, a parall
e
l
and lo
w-co
st
ing L
D
PC d
e
co
der
archit
ecture for F
P
GA is
prop
osed,
as well
a
s
an
o
p
timization
of
the m
e
mo
ry syste
m
i
s
prese
n
ted.
Th
e a
r
c
h
itec
tu
re
is
impleme
n
ted
on a Xilinx Virtex-4 FPG
A
, (2560,10
2
4
) L
D
PC
cod
e
is cho
s
en.
The re
st of the
pape
r is
org
a
n
ize
d
as foll
o
w
. In the se
cond
sectio
n, the ne
w st
rate
gy of LDPC d
e
co
der i
s
bei
ng
prop
osed f
r
o
m
the G
ene
ralize
d
Di
stri
b
u
tive La
ws
(GDL
) [6]. In
se
ction th
ree
,
a (2
560,
10
24)
LDPC de
co
d
e
r i
s
im
plem
ented
usi
ng t
he n
e
w
de
co
ding
strate
gy. And the
re
sults a
nd a
nal
ysis
are p
r
e
s
ente
d
in se
ction four.
2. LDPC De
coding Algo
rithms
Whe
n
Galla
g
e
r first p
r
opo
sed L
D
PC
code
s in 196
2
,
a probabili
stic decodin
g
method
wa
s also pre
s
ente
d
, and t
he Belief-Pro
pagatio
n Algo
rithm wa
s introdu
ced to L
D
PC de
codi
ng
b
y
Mackay. As
we kno
w
, the BP Algorithm can b
e
viewed a
s
ma
ssage pa
ssing
on graph
s, a
nd it
obeys the Su
m-Pro
d
u
c
t Updating L
a
ws (SPUL) [7] or the GDL.
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 23
02-4
046
TELKOM
NI
KA
Vol. 12, No. 11, Novem
ber 20
14: 77
21 – 772
7
7722
2.1. The LDP
C
De
coding in Facto
r
Gra
phs
Figure 1. The
Function of L
D
PC Describ
ed by Facto
r
Grap
hs
Und
e
r the def
inition of Fact
or Graph
s, the function of a
LDPC code
describ
ed by a m×n
Matrix can
be
define
d
a
s
t
he g
r
ap
h in
F
i
gure
1. So,
b
a
se
d o
n
the
SPUL, the
de
codi
ng
pro
c
e
ss
can
be
de
scribed
a
s
the
BP algo
rith
m, and if
we
define
the
s
e pa
ssing
m
a
ssag
es in L
og-
Likeli
hood
-Ra
t
io(LL
R
) a
nd
do som
e
mod
i
fication
s
in its ch
eck no
de
update ste
p
, it become
s
the
Min-Sum al
gorithm (MSA
). Both of the two algo
rithms are well
known,
and will not be
stated
carefully in this pap
er ag
ain
.
2.2. The LDP
C
De
coding in GDL
Figure 2. The
Function of L
D
PC Describ
ed by GDL
Table 1. The
Definition of L
o
cal
Domai
n
and Lo
cal Ke
rnel Fig
u
re 2
local domain
local kernel
{
x
1
}
P
(
x
1
|
y
1
)
{
x
2
}
P
(
x
2
|
y
2
)
… …
{
x
n
}
P
(
x
n
|
y
n
)
{
x
1
,
x
3
} 1
{
x
1
,
x
2
} 1
… …
{
x
a
,
x
n
} 1
More
over, ba
sed o
n
the d
e
finition of the G
ene
rali
ze
d Dist
ributive
Laws (G
DL
),
we can
define the
lo
cal dom
ain a
n
d
the lo
cal
ke
rnel
as T
abl
e
1, and th
e fun
c
tion
of a L
D
PC code
can
be
descri
bed a
s
Figure 2. Hen
c
e, the de
cod
i
ng pro
c
e
s
s can be de
scrib
ed as follo
w:
(1) Initialization
(l
)
(0
)
1
ji
r
(
1
)
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
2302-4
046
A New Lo
w
-
C
o
sting Q
C
-
L
D
P
C De
cod
e
r f
o
r FPGA (Zh
ao Ha
n)
7723
(l
)
(1)
1
ji
r
(
2
)
(2) Variabl
e-n
o
d
e
update
(l
)
(
l
1
)
\
(0
)
(
c
0
|
y
)
(
0
)
i
ij
ij
i
i
j
i
jC
j
qK
P
r
(
3
)
(l
)
(
l
1
)
\
(1)
(
c
1
|
y
)
(
1)
i
ij
ij
i
i
j
i
jC
j
qK
P
r
(
4
)
Whe
r
e
(l
)
ij
q
is th
e massa
ge
passin
g
from
ith
variable
node to
jth
check n
ode in
lth
iteration,
i
C
is the set of variable nod
es th
at adjusted to
the
ith
variable node, and
\
i
Cj
is
i
C
without the
jth
che
c
k nod
e
.
Moreover,
ij
K
is the no
rmali
z
ation
con
s
ta
nt which is
(l)
(
l)
(1)
(
0
)
ij
ij
qq
.
(3) Che
c
k-n
ode
update
(l
)
(
l
1
)
\
11
(0
)
1
2
(
1
)
22
j
ji
i
j
iR
i
rq
(
5
)
(l
)
(
l
1
)
\
11
(1)
1
2
(
1
)
22
j
ji
i
j
iR
i
rq
(
6
)
Whe
r
e
(l
)
ji
r
is the
massag
e pa
ssi
ng fro
m
th
e
jth
ch
eck n
ode to the
ith
variable
nod
e i
n
lth
iteration,
j
R
is the
set of
variable
nod
e
s
that a
d
juste
d
to the
jth
check n
ode, a
nd
\
j
R
i
is
j
R
without the
ith
variable n
o
de.
(4)
Computing the Pseud
o-posterior Probability
(l)
(
l
1
)
(0
)
(
c
0
|
y
)
(
0
)
j
ii
j
i
i
j
i
jC
QK
P
r
(
7
)
(l)
(
l
1
)
(1
)
(
c
1
|
y
)
(
1
)
j
ii
j
i
i
j
i
jC
QK
P
r
(
8
)
Whe
r
e
(l)
i
Q
is th
e
pse
udo
-p
ost
e
rio
r
pro
babili
ty of
ith
bits
after the
lth
ite
r
ation, a
n
d
i
K
is
the norm
a
liza
t
ion con
s
tant
whi
c
h is
(l
)
(
l
)
(1)
(
0
)
ii
QQ
.
(5) De
codi
ng
If
(l)
(
l
)
(1
)
(
0
)
ii
QQ
, the
ith
bit will be decod
ed as 1, el
se
the
ith
bit will
be de
co
ded
a
s
0.
And if the decod
ed code
word satisfie
s
ˆ
0
T
CH
or the de
co
ding process rea
c
he
s the
max
iteration
s
we
set, the
deco
d
ing process
stop
s.
Similar with t
he co
nvert from BP Algori
t
hm to MSA,
we can al
so
descri
be the
step
s of LDP
C
de
codi
ng a
s
follow:
(1) Initialization
(0)
()
0
ij
Lr
(
9
)
(2) Variabl
e-n
o
d
e
update
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 23
02-4
046
TELKOM
NI
KA
Vol. 12, No. 11, Novem
ber 20
14: 77
21 – 772
7
7724
(l
)
(
l
)
\
()
(
)
(
)
i
ij
i
j
i
jC
j
Lq
L
P
Lr
(
1
0
)
Whe
r
e
(l
)
(l)
(l)
(0
)
()
l
n
(1
)
ij
ij
ij
q
Lq
q
is th
e LLR
ma
ssa
ge pa
ssi
ng from the
ith
va
riable
nod
e to
the
jth
che
ck
node in
lth
ite
r
ation.
(3) Che
c
k-n
ode
update
(l
)
(
l
)
(l)
\i
\i
()
s
g
n
(
)
m
i
n
(
)
j
j
j
ii
j
i
j
iR
iR
L
r
Lq
Lq
(
1
1
)
Whe
r
e
(l
)
(l
)
(l
)
(0
)
()
l
n
(1
)
ij
ij
ij
r
Lr
r
is the LLR ma
ssag
e passin
g
fro
m
the
jth
che
ck n
ode to th
e
ith
variable n
ode in
lth
iteration.
(4)
Computing the Pseud
o-posterior Probability
(l
)
(
l
)
()
(
)
(
)
i
ij
i
j
i
jC
LQ
L
P
L
r
(
1
2
)
Whe
r
e
(l
)
(l
)
(l)
(0
)
()
l
n
(1
)
i
i
i
Q
LQ
Q
is th
e LL
R p
s
e
u
d
o
-po
s
te
rior
p
r
obability of
it
h
bits
after the
lth
iteration.
(5) De
codi
ng
If
(l
)
()
0
i
LQ
, the
ith
bit
will be decoded as
0, el
se
the
ith
bit will
be de
cod
ed as 1.
And
if the de
code
d co
de
wo
rd
satisfie
s
0
ˆ
T
H
C
or th
e de
codi
ng p
r
ocess
rea
c
h
e
s the
max it
eration
s
we set, the deco
d
ing p
r
o
c
ess stop
s.
Acco
rdi
ng to
the features
of
FPGAs,
we ad
opt the
seco
nd
de
codi
ng meth
od to
de
sign
the L
D
PC d
e
co
der we p
r
opo
se
d. Be
cau
s
e
the
seco
nd
de
cod
i
ng meth
od
can
initiali
ze
the
decode
r by assi
gn 0 to all
L
(
r
)
ji
, an
d this step
can b
e
reali
z
ed in
the initializati
on of FPGA at
once, while the first one n
eed extra a
s
signm
ent
ope
ration to assi
gn the value of the receiv
ed
bits
to
L
(
q
)
ij
t
he valu
e of t
he
re
ceived
bits. Hen
c
e,
the second
d
e
co
ding
met
hod
uses fe
wer
sou
r
ces than
the first
one. I
n
fact, in th
e f
i
rst it
e
r
ation, t
he vari
able
-
n
ode
s up
date
step fini
she
s
i
s
equal
to the
I
n
itialization
in
MSA, but thi
s
“Ini
tialization”
use the
va
riable
-
n
ode
s
update
in
stea
d
of adding extra assignm
ent
operatio
n to the de
cod
e
r.
3. Implementation
Figure 3. The
Proce
dure of (2560, 10
24
) QC-LDP
C Deco
der
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
2302-4
046
A New Lo
w
-
C
o
sting Q
C
-
L
D
P
C De
cod
e
r f
o
r FPGA (Zh
ao Ha
n)
7725
Usi
ng the d
e
c
odi
ng alg
o
rit
h
m we
pro
p
o
s
ed
above, a
(256
0, 102
4
)
QC-L
DPC
decode
r
on FPGA i
s
i
m
pleme
n
ted i
n
this
se
ction
.
The proc
ed
ure of th
e de
cod
e
r i
s
sho
w
n in
Figu
re
3, to
further
red
u
ce the re
so
urces
con
s
um
ption, we
i
gno
re
the com
putat
ion of the
syn
d
rom
e
, and
set
a max iteratio
n throug
h the
Monte Ca
rlo
simulatio
n
m
e
thod [8].
The
stru
ctu
r
e
of the
de
cod
e
r i
s
sho
w
n
i
n
Figu
re
4, th
e Solid li
ne
s
stand
for th
e
dire
ction
of data pa
ssi
ng, whil
e the
dashed lin
es
stand fo
r t
he dire
ction
of control
sign
al and
a
ddressi
ng
sign
al. The RAM_p, RAM_
r and
RAM_q
represent RA
Ms that store the val
ues
of the received
bits, the valu
e of
L
(
r
)
ji
and
the value
of
L
(
q
)
ij
re
sp
ecti
vely. Two ad
dre
s
s ge
nera
t
ors
gen
erate
the
read/
write
ad
dre
s
ses
of RAM_p, RAM_
r and
RAM
_
q
.
The varia
b
l
e
-no
d
e
s
up
d
a
te step
and
the
che
c
k-n
ode
s update
ste
p
will
be p
r
ece
ded i
n
t
he vari
able
_
nod
s_u
pdate
model
and
the
che
c
k_n
o
d
s
_
updatem
odel,
and th
e d
e
coding
mod
e
l
deci
d
e
s
which digit the
inp
u
t bit should
be,
1 or 0. M
o
re
o
v
er, the processing
co
ntro
l model g
ene
rates
co
ntrol
sign
al for a
d
d
r
ess g
ene
rat
o
r,
node
s up
date
model de
cod
i
ng model a
c
cording to p
r
o
c
ed
ure of the
decode
r.
Figure 4. The
Structure of
(2560, 10
24)
QC-LDP
C De
cod
e
r
As the che
ck matrice
s
of LDPC
cod
e
s
are
al
ways v
e
ry large, the
numbe
r of massag
e
passe
d bet
ween
che
c
k no
des
and
vari
able n
ode
s i
s
usu
a
lly very
large,
so th
e
con
s
um
ption
of
the add
re
ss
gene
rato
r is
alway
s
very l
a
rge. In th
i
s
desi
gn, the a
ddre
s
s ge
ne
rator two
pa
rts, a
ROM
sto
r
e
s
t
he initial
add
ress of
every
sub
-
matrix
an
d an
ad
dre
ss-shifte
r
whi
c
h
co
nsi
s
ted
of
an
adde
r an
d a
mode 1
28
co
unter. Th
e a
ddre
s
s shifter gene
rate
s th
e add
re
ss fo
r each RAM by
addin
g
the in
itial address
and the n
u
m
ber of the
co
unter tog
e
the
r
, so that the
costin
g of the
address ge
ne
rator
can b
e
lowe
red.
More
over, to
sho
r
t the
de
coding tim
e
th
e de
cod
e
r co
nsum
es an
d
balan
ce th
e
reso
urce
co
sting
of th
e de
co
de
r, we choo
se
a
two-pa
ra
llel
schem
e. In thi
s
schem
e, th
e vari
able
no
de
s
update
mod
e
l
and
the
che
c
k n
ode
s
upda
te model
hav
e two
input
s
with o
ne
com
puting
co
re,
so
that the deco
d
ing time will
be half of se
rial de
co
der i
n
the sa
me code len
g
th wi
th little increa
se
in r
e
sour
ce cos
t
ing.
Finally, to fit the sp
eci
a
l two-inp
u
t upd
ate model, RA
M_r an
d RA
M_q will b
e
a
two-in
put
and t
w
o
-
outp
u
t RAM
s
,
so
that they
can
input
or o
u
tput two
valu
e
s
at
the
sa
m
e
time.
What
is
more, in
ord
e
r to let RA
M_r o
u
tputs
0s at the fi
rst iteration, the re
set po
rt
of this blo
c
k RAM
sho
u
ld be e
n
abled. And af
ter the first iterati
on, the re
set port of it will be disa
bled
again.
4. Results
A parallel l
o
w-costing LDP
C
decoder i
s
desi
gned and implem
ented on
a Xilinx V
i
rtex-4
FPGA platform. Whe
n
the
numbe
r of
qu
antizatio
n
bits and th
e max
iteration
s
a
r
e
set to 6
and
2
5
res
p
e
c
tiv
e
ly
,
the bit erro
r rate (BER
) p
e
rform
a
n
c
e o
f
the decode
r is sh
own a
s
Figu
re 5 a
nd
Table 2.
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 23
02-4
046
TELKOM
NI
KA
Vol. 12, No. 11, Novem
ber 20
14: 77
21 – 772
7
7726
Figure 5. The
BER Performance of
the (256
0,102
4)
LDPC
De
cod
e
r
Table 2. The
Codi
ng Gai
n
of (2560,1
0
2
4
) LDP
C
BER
BPSK
(Eb\N0\
d
B)
Codi
ng Gain
in Simula
tion
(Eb\N0\
d
B)
Codi
ng Gain
in FPG
A
(Eb\N0\
d
B)
1e-2
4.32 3.01
2.90
1e-3
6.79 5.16
5.05
1e-4
8.40 6.53
6.41
1e-5
9.58 7.52
7.29
As we
ca
n se
e, the co
ding
gain of the
de
cod
e
r
we p
r
o
posed in thi
s
pape
r is
over
7.2 dB
whe
n
BER i
s
1e-5, whi
c
h
is very
clo
s
e
to t
he codin
g
gain
of the
LDPC code
we
simul
a
ted
on
MATLAB. It
mean
s that, with the 6 q
u
antizatio
n bi
ts an
d 30 ma
x iterations, t
h
is L
D
PC
de
cod
e
r
can ma
ke g
o
od use of the perfo
rman
ce
of (2560, 10
2
4
) LDP
C
cod
e
.
The
co
sting
of the de
coder
propo
sed in thi
s
p
aper is
sh
o
w
n in
Table
3, and
comp
ari
s
o
n
s
with som
e
other de
co
de
rs
are al
so sho
w
n.
Table 3. The
Co
sting of the Propo
se
d Deco
der
Slices
4-inp
u
ts
LU
Ts
16K R
A
M
s
/
R
OM
s
Max Workin
g Cl
ock
Proposed
862 (3.5
%)
1,084(2.2
%
)
10(3.1
%
)
181.242MHz
Reference[9]
7,755
22,014
8,555(Re
gisters)
113MHz
Reference[10
]
46,190
34,908
138
131.411MHz
More
over, the throug
hput
of the deco
d
e
r
can b
e
cal
c
ulated a
s
bel
ow:
CL
K
T
k
T
D
c
(
1
3
)
Whe
r
e
T
C
is
the thro
ugh
p
u
t of the de
coder,
k
is
the information
bits
in a codeword,
T
D
is
th
e
decodin
g
clo
c
ks of the de
cod
e
r, and
CLK
is the freq
uen
cy of working
clo
ck. In
the deco
der
we
prop
osed,
k
=1024
bits,
T
D
= 2
083
84
clo
c
ks,
CLK
=18
0
M
Hz,
so the
throu
ghp
ut of
a si
ngle
de
co
der
T
C
=8.5Mbp
s
. But with th
e low-co
sting
of the deco
der, we
can
achi
eve a high throu
ghp
u
t
b
y
usin
g multi-p
a
rallel
de
codi
ng st
rategy. F
o
r exam
ple,
if we m
a
ke full
use
of the FP
GA we
use, we
can p
u
t 25 de
cod
e
r on o
ne
FPGA, and the throug
hput
can rea
c
h 21
2.5Mbp
s.
0
1
2
3
4
5
6
7
8
9
10
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
E
b
/N
0
BER
B
E
R
of
S
i
m
ual
t
i
on
BER
o
f
F
P
G
A
BER
o
f
B
PSK
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
2302-4
046
A New Lo
w
-
C
o
sting Q
C
-
L
D
P
C De
cod
e
r f
o
r FPGA (Zh
ao Ha
n)
7727
5. Conclusio
n
This
pape
r p
r
opo
se
s a L
D
PC de
codi
ng
algorith
m
a
c
cording to th
e feature
s
of FPGAs,
and a
low-co
sting L
D
P
C
decode
r i
s
i
m
pleme
n
ted
by usin
g the
GDL
alg
o
rit
h
m. The
re
sults
sho
w
s that t
he L
D
PC de
cod
e
r
nee
ds fewe
r
re
so
urces
comp
a
r
ed
agai
n
wi
th othe
r L
D
PC
decode
rs, an
d the deco
d
e
r ca
n rea
c
h a high through
put by usin
g multi-p
a
rallel d
e
cod
i
ng
strategy. So the low-costin
g decode
r is
flexible for different ap
plications.
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ces
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e
r. Lo
w
de
nsit
y
pari
t
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62
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a
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w
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de
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a
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18): 164
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Ca
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a
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g
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a
te
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imp
l
eme
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arit
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b
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rti
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Lei Ya
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w
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ode
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Eliec
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i
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m
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[7]
F
R
Kschischa
ng, BJ F
r
e
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e
rforma
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C
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e
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i
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m Alg
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