TELKOM
NIKA
, Vol. 11, No. 5, May 2013, pp. 2365 ~ 2370
ISSN: 2302-4
046
2365
Re
cei
v
ed
De
cem
ber 2
4
, 2012; Re
vi
sed
March 3, 201
3; Acce
pted
March 13, 20
13
A Design of Gain Boosted Error Amplifier Applied to
PWM Control
Yu Shi-Hua
1
, Wang Kai-Yu*
2
, Wei Shu-Ping
2
, Wan
g
Xiao-Feng
2
, Yang Ming-Jian
2
1
School of Co
mputer Scie
nc
e and T
e
chno
l
o
g
y
, Hul
u
n
buir
Univers
i
t
y
,
Hulu
nb
eier, 0
2
100
8, Chi
n
a
2
School of Elec
tronic Scie
nce
and T
e
chno
log
y
, Dal
i
a
n
Univ
e
r
sit
y
of T
e
chnol
og
y,
Dalia
n, 11
602
3, Chin
a
*Corres
p
o
ndi
n
g
author, e-ma
i
l
:
w
k
a
i
yu@
d
l
u
t.edu.cn
A
b
st
r
a
ct
A high g
a
i
n
, w
i
de co
mmo
n
-
m
ode a
nd h
i
g
h
sw
ing error a
m
p
lifier is pr
opos
e
d
. It can be ap
plie
d to a
PW
M control chip. T
he err
o
r amplifi
e
r ad
o
p
ts folde
d
cas
c
ode structur
e
w
i
th gain b
o
o
s
ted. T
h
is chip
is
simulat
ed
and
fabricate
d
i
n
th
e CSMC
0.5
μ
m
CMOS. The
result shows that
the err
o
r a
m
plifier
has
the
D
C
gai
n of 14
1.11
dB, the co
mmon-
mo
de i
n
p
u
t rang
e of 0~
3.
87v a
nd th
e o
u
tput sw
ing of
0.11~
4.80v. T
h
es
e
me
et the req
u
ir
ements of en
gi
neer
ing a
p
p
lica
t
ions an
d can r
eali
z
e
stabl
e system o
u
tput.
Ke
y
w
ords
:
P
W
M controller, folde
d
casco
de
amp
lifi
e
r, gain
booste
d, error amplifi
e
r
Copy
right
©
2013 Un
ive
r
sita
s Ah
mad
Dah
l
an
. All rig
h
t
s r
ese
rved
.
1. Introduc
tion
With the
rapi
d devel
opme
n
t of el
ectroni
c te
ch
n
o
logy,
the
relatio
n
ship b
e
twe
en
electroni
c
prod
uct
s
a
n
d
peo
ple'
s live
s
i
s
in
crea
sin
g
ly clo
s
e.
Al
most all
ele
c
t
r
oni
c p
r
od
uct
s
a
r
e
relate
d
to
the po
we
r m
anag
ement,
so
power m
anag
ement
mark
et i
s
al
so
dire
ctly i
n
fluen
ced
by the
prod
uctio
n
of
electroni
c p
r
odu
cts. Fu
rth
e
rmo
r
e,
switching p
o
we
r
supply technol
ogy is al
so i
n
con
s
tant i
nno
vation. Thi
s
provide
s
a b
r
oad
sp
ac
e fo
r d
e
velopm
e
n
t of switchin
g po
we
r
sup
p
ly.
PWM
cont
rol
chip
is the
co
re of
the
po
wer
reg
u
lator,
and
error am
plifier i
s
a
vital compo
nent
in
the chi
p
. Erro
r amplifie
r'
s o
u
tput swing
d
i
rectly dete
r
m
i
nes th
e maxi
mum an
d mi
nimum valu
e
o
f
the outp
u
t du
ty cycle
of th
e PWM
chip.
The fi
xed
ou
tput swing
m
a
ke
the m
a
ximum, minim
u
m
value of
chip
output d
u
ty ratio cannot
b
e
adju
s
ted.
What i
s
m
o
re
, it limits the
appli
c
ation
of the
chip a
nd affe
cts the pe
rformance of the PWM chi
p
.
Based o
n
the requireme
nts of the entire chip
, we pu
t forward a hi
gh-p
e
rfo
r
ma
n
c
e erro
r
amplifier whi
c
h
h
a
ve
high
-gain, wide common
-
mo
d
e
input rang
e
and o
u
tput swing. Thi
s
circuit
adju
s
ts the d
u
ty cycle of the pulse sig
nal
by amplifying the differen
c
e bet
we
en the feedb
ack
voltage and t
he refe
ren
c
e
voltage to achieve t
he purpose of stabili
zing the o
u
tp
ut voltage.
2. The Circui
t Struc
t
ure a
nd Workin
g Principle
2.1. Error Amplifier Circ
uit
The functio
n
of the error amplifier m
agnifie
s
the differen
c
e be
tween the fe
edba
ck
voltage and
the refe
ren
c
e voltage. T
he amplifi
e
d
result, con
n
e
cting th
e PWM
comp
arator
positive p
h
a
s
e si
de in
put,
comp
are with
the ramp
vol
t
age. The
re
sult of the
com
pari
s
on
is u
s
ed
to control chi
p
output d
u
ty cycle
of the
PWM si
gnal
ratio so
as to
control the ti
me of switch
on
and off. Finally, it keeps the output voltage st
abl
e. It i
s
a key component of the chip.
2.1.1. The Analy
s
is of G
a
in Boos
ted
Principle
The folded
cascod
e stru
cture improve
s
CMIR
com
parin
g to the rest of the op-a
m
p
stru
cture. Th
e upp
er limit
of the co
mm
on mod
e
in
p
u
t rang
e is th
e sam
e
with t
he up
per li
mi
t of
the ba
si
c two
stag
e o
perational
amplifie
r and
tele
sc
op
ic
ca
scode
a
m
plifier. O
n
t
he oth
e
r han
d, if
the value of V_BIAS can meet the M
9
and M
10
ope
rating in the linear
regi
on, it can sig
n
ificantly
lowe
r the
co
mmon-mod
e
input thre
sh
o
l
d. But in act
ual cascod
e
circuit, po
we
r sup
p
ly voltag
e
and th
e
sign
al swin
g
req
u
irem
ents lim
ited am
plifier'
s
stage.
In o
r
de
r to
incre
a
se
the
gain,
we
can b
e
u
s
ed
to add a b
ootstra
p ci
rcuit. Using
a gain bo
otstra
p circuit, we
can effe
ctively
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ISSN: 23
02-4
046
TELKOM
NIKA
Vol. 11, No
. 5, May 2013 : 2365 – 237
0
2366
increa
se the
output re
sista
n
ce of casco
de circuit. As
s
h
ow
n
in
F
i
gu
r
e
1
,
it
is the stru
cture of the
bootstrap cascod
e amplifie
r.
-
VD
D
M1
M2
+
-
OU
T
Vo
R
V_
BI
AS
Vi
-
+
+
Figure 1. Ca
scod
e S
t
ructu
r
e Circuit with
Gain Boo
s
ted
This
circuit
use
s
a
n
am
plifier a
s
a
negative fee
dba
ck l
oop t
o
co
ntrol the
volt
age
betwe
en the tran
sisto
r
M
2
’
s
gate and gro
und. If
the gain of the
amplifier is infinite, the negative
feedba
ck loo
p
can adj
ust
ed gate volt
a
ge of M
2
until the two input volt
age d
i
f
f
erence of th
e
amplifier i
s
zero. In othe
r
words, the
drain-sou
r
ce vo
lt
age of the transi
s
tor
M
1
can be a
d
ju
ste
d
to
clo
s
e to V_BIAS.
If
the drain-sou
r
ce volt
age of M1 ke
ep
s con
s
t
a
nt, the change
of the leakag
e
curre
n
t has n
o
imp
a
ct on the output volt
age. Beside
s,
the output resist
an
ce is cl
ose to infinity
.
In
actual
circuit,
the gain of
the amplifier
is a
limited v
a
lue, whi
c
h
mean
s
that the drain-so
urce
volt
age of M
1
is not a
co
n
s
t
ant valu
e a
nd the o
u
tpu
t
resi
st
a
n
ce i
s
al
so a finit
e
value.
Th
e
n
,
analyze the small-sign
al model of the circuit throu
gh the Figu
re 2.
Gm
b2Vbs
2
=-
Gmb2(
a+1)
Vds1
Vo
Vi
R
+
-
-
Ro
2
-
+
G
m2Vg
s
2
=
-Gm2
(
a+1
)Vds1
Gm
1Vi
+
Ro
1
Vds
i
Figure 2.
The
small sig
nal
model of
ca
scod
e stru
ctu
r
e with gain b
ooste
d
From th
e qu
a
lit
ative point
of
view
, the l
eakage
cu
rre
n
t of M
2
incre
a
se
wh
en the
output
volt
age in
cre
a
sin
g
.
Thu
s
i
t
incre
a
se th
e lea
k
age
cu
rre
nt and the
drain
-
sou
r
ce
volt
age of
M
1
.
Drai
n so
urce
volt
age increase throu
g
h
the amplifier with the -
α
magnification
.
This
decre
a
s
e
s
the volt
age b
e
twee
n the g
a
te and g
r
ou
nd of the M
2
.
The de
crea
se
of the gate volt
age of M
2
lead
to the leaka
ge cu
rrent’
s
decrea
s
e.
Th
is enla
r
ge
s the output re
sist
an
ce, co
mp
a
r
ing to the
ordin
a
ry ca
scod
e
st
ru
cture.
The role of
feedba
ck
can
ma
ke th
e gate volt
a
ge of M
2
ke
ep
s
c
o
ns
t
a
nt.
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TELKOM
NIKA
ISSN:
2302-4
046
A D
e
s
i
gn
o
f
G
a
in
Bo
os
te
d Er
r
o
r
Am
plifier Applied to PWM Control
(Yu Shi-Hua)
2367
Figure 3
sho
w
s
a sm
all-si
gnal e
quivale
nt circ
uit dia
g
r
am of the
ca
scode
stru
ctu
r
e with
the structu
r
e
of the bo
otstrap
ci
rcuit in l
o
w frequ
en
cies. Th
e tra
n
sistor M
1
wa
s modul
ated b
y
body effect transco
ndu
cta
n
ce. Th
e drai
n-sou
r
ce voltage of M
2
for:
V
V
V
V
V
V
V
V
ds
ds
ds
ds
g
s
g
gs
1
1
1
1
2
2
2
2
)
1
(
(1)
Ho
wever, in the usual cascode structu
r
e,
M2 of the gate-sou
r
ce voltage is V
gs2
=-
V
ds1
. If
>0, co
mpa
r
in
g to the com
m
on ca
scod
e
stru
cture,
the
factor of equ
ation (1
) have
amplified
action. It is the core of boot
strap
type ca
scode stru
ctu
r
e.
Since u
s
u
a
ll
y the only d
i
fference bet
wee
n
casco
de st
ru
cture
of M
2
and bootstrap
ca
scode
stru
cture
in
small
sign
al mo
del
is the
differe
nt V
gs2
. The V
gs2
affects o
n
ly throu
gh t
he
c
u
rr
en
t o
f
tr
a
n
s
c
o
nd
uc
ta
nc
e
g
m2
. Whe
n
analysi
s
th
e bootstrap cascod
e circui
t, we only make
the ori
g
inal
common
-
sou
r
ce commo
n-g
a
te structu
r
e
g
m2
c
onvert into (
α
+1)g
m2
. In other
words
,
the boot
strap
ca
scode
circuit can b
e
se
en a
s
a cascode
circuit th
at g
m2
beco
m
e large. So
a
bootstrap cascod
e amplifie
r tran
scond
uctance i
s
:
r
r
g
g
g
G
ds
ds
mb
m
m
m
2
1
2
2
1
]
)
1
(
[
1
1
1
(2)
Similarly, in
gene
ral th
ere
is
Gm
≈
g
m1
. Therefore,
bo
otstrap
ci
rcuit
not ne
ed to
cha
nge
the tran
sco
nd
uctan
c
e.
The structu
r
e of bootstra
p ca
scode
redu
ce
s the sou
r
ce re
si
stance R
i2
of M
2
when
comp
ared wit
h
the usual st
ructu
r
e
of
ca
scode.
Thi
s
redu
ce th
e
rat
i
o of the
d
r
ai
n-sou
r
ce volt
age
of transi
s
tor
M
1
(V
ds1
) to the output voltage (Vo), thereby
in
cre
a
sing the outpu
t resista
n
ce. The
g
m2
in Casco
de formula
is repl
ace by
(1+
α
)g
m2
. T
h
e
n
we o
b
tain
the commo
n
gate of
so
urce
bootstrap ci
rcuit resi
stan
ce
value:
r
r
g
g
r
r
g
g
r
r
R
ds
ds
mb
m
ds
ds
mb
m
ds
ds
2
1
2
2
2
1
2
2
2
1
0
]
)
1
(
[
]
)
1
(
[
(3)
Comp
ared with
ordin
a
ry ca
scode am
plifier,
output
re
sista
n
ce
of bootst
rap
ca
scode
c
i
rc
uit is
about [g
m2
(
α
+1) +
g
mb2
] rds1 times the no
rmal
level.
2.1.2. The Circuit Design
of Gain Boo
s
ted
Amplifier
We a
dd fou
r
OpAmp o
n
th
e ba
sic
ca
scode am
plifier to form the
bootstrap
circuit and
amplifies th
e
gain. The
g
a
tes of M
5
, M
6
, M
7
and M
8
don’t dire
ctly con
n
e
c
t with the fou
r
bias
voltages, but
con
n
e
c
ting th
e output of the four ope
rati
onal amplifie
rs. While the f
our am
plifiers
makin
g
up a negative feed
back loop in
crea
se the re
sistan
ce, whe
n
we se
e fro
m
the drain o
f
a
trans
is
tor.
Such a
s
e
x
presse
d in
equatio
n 3, t
he
b
ootstrap
circuit
ca
n
increa
se th
e
output
resi
stan
ce, so that the output tran
sco
ndu
ctan
ce of
the transi
s
t
o
r incre
a
ses (
+1
) t
i
mes,
whi
c
h
is the g
a
in of bo
otstrap op
eratio
na
l amplifier.
Du
e to the different bia
s
volta
ge, we
ma
ke
the gain of auxiliary amplifier at M
5
and M
6
is A
1
, and get Figure 3.
The improved
with bootst
ra
p circ
uit ca
scode structu
r
e
amplifier
r
r
g
A
r
g
A
g
r
r
R
ds
ds
m
ds
mb
m
ds
ds
out
M
6
4
6
1
4
6
1
6
6
4
|
)
)(
1
(
)}
](
)
1
(
[
1
{
6
(4)
Let the gain
M
7
and M
8
for is
A
2
r
r
r
g
A
r
r
g
A
g
r
r
r
R
ds
ds
ds
m
ds
ds
mb
m
ds
ds
ds
out
M
8
10
2
8
2
10
2
8
2
8
8
10
2
|
)
||
(
)
1
(
)}
||
(
)
1
(
[
1
{
)
||
(
8
(5)
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 23
02-4
046
TELKOM
NIKA
Vol. 11, No
. 5, May 2013 : 2365 – 237
0
2368
Based o
n
the
above two type ca
n obtain
the resi
stan
ce of circuit ou
tput:
)
6
(
||
)
8
(
'
'
|
|
R
R
R
M
M
o
out
out
(6)
Cal
c
ulate the
gain was:
R
G
A
o
V
m
(7)
As ca
n be
se
en from th
e a
bove two fo
rmulas, the
overall g
a
in of t
he ci
rcuit be
comes
large, we ach
i
eve gain bo
o
t
strap effe
ct.
3. Circuit Simulation an
d Test
Get Ta
ble
1,
comp
ari
ng to
folded
casco
de
circuit. F
r
om the
re
sult
s in
Ta
ble 1
can
be
see
n
, the gai
n of the g
a
in
bootstrap
am
plifier im
p
r
ov
es o
b
viou
sly whe
n
compa
r
ed with th
e g
a
in
of ba
sic am
pl
ifier, outp
u
t p
o
we
r
also
in
crea
sed
si
gnific
antly. At the s
a
me time, it does
n
’t have
influen
ce
on t
he oth
e
r pe
rforma
nce in
di
cators of
the
amplifier.
The
final d
e
si
gn
result
s m
eet t
h
e
requi
rem
ents
(Figu
r
e
s
3 an
d 4).
Figure 3. Simulation re
sult
of gain and
b
and
width of g
a
in boo
sted a
m
plifier
Figure 4. Simulation re
sult
of CMIR of g
a
in boo
sted a
m
plifier
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
2302-4
046
A D
e
s
i
gn
o
f
G
a
in
Bo
os
te
d Er
r
o
r
Am
plifier Applied to PWM Control
(Yu Shi-Hua)
2369
Table1. Th
e compa
r
ison of basi
c
mod
e
l'
s and gain imp
r
ove mod
e
l's
simulatio
n
re
sult.
Simulation items
Basic amplif
ier
Gain boosted am
plifier
AV 98.90dB
141.4dB
GBW 23.71MHz
20.68MHz
ICMR
0~3.93V
0~3.87V
Output S
w
ing
0.16~4.8V
0.11~4.80V
CMRR
122.85
dB
117.88dB
SR +14.61V/
μ
s,-38.5
5
V/
μ
s +13.301V/
μ
s, -43
.
04V/
μ
s
Setup time
109.56ns
119.39ns
PSRR 84.33dB
94.6
dB
Power Co
nsumpt
ion
9.72mW
18.84 mW
4. Circuit La
y
out and Chip Test
Figure 5 for t
h
is
p
a
p
e
r d
e
sign gain
boot
strap
erro
r a
m
plifier u
s
ed
in PWM
control chi
p
to
reali
z
e the la
yout.
The la
yout stru
cture meet
s mini
mum
Are
a
requireme
nt
s,
con
s
ide
r
in
g the
matchin
g
, symmetry and so on. Finally
, it succes
sful
ly t
aped out in CSMC 0.5u
m DPDM mixed
sign
al pro
c
e
ss. Using
Ag
ilent E3641A
powe
r
sup
p
l
y
,
Agilent 33520 gives a
signal, placi
ng
sign
age at
T
e
ktronix
T
D
S2
022 o
s
cilloscope a
nd Flu
k
e
15 b di
git
a
l
multimeter t
o
test chip.
T
e
st
result: output volt
age is 1.5805V
, a error of 0.5
mV
, ripple of 3mV af
ter the system steady
(as
sho
w
n in Fig
u
re 6: the curve amplificat
i
on ch
art af
ter the system st
able outp
u
t).
Figure 5. Layout of whole
chip
Figure 6. The
output cu
rve of Vout
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ISSN: 23
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Vol. 11, No
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0
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5. Conclusio
n
This pa
per d
e
s
ign a high p
e
rform
a
n
c
e g
a
in bootst
rap
error amplifie
r with high ga
in, wide
comm
on-mod
e
input rang
e
and
swi
ng.
Spice
simul
a
tion sho
w
s th
at, comp
are
d
with the b
a
sic
error
amplifie
r, in the
case
of othe
r p
r
op
erties
chan
ge
little gain
ha
s b
een
greatl
y
improved.
But
the corre
s
po
nding
po
we
r co
nsumptio
n do
ubled.
Thro
ugh
chi
p
test, the
PWM
cont
rol
chi
p
perfo
rman
ce i
s
goo
d.
Referen
ces
[1]
Z
hou Z
h
i-mi
n.
T
he classific
a
tion of S
w
itch
i
ng p
o
w
e
r s
u
p
p
l
y
an
d a
ppl
ic
ation.
J el
ectronic q
u
a
n
tity
.
200
1; 11: 36-3
7
.
[2]
Man S
i
u, Ph
ili
p KT
Mok, Ka
Na
ng
Le
ung.
A Vo
ltage
M
odePW
M
B
u
c
k
Re
gul
ator
w
i
th End
Poi
n
t
Predicti
on.
IEEE Transaction
on Circ
u
it s and System
s II:
Express Brief s
. 2006; 53(
4): 294-2
98.
[3]
Ma lei, D
i
n
g
Ying-T
ao, W
ang
Xi
ng-H
ua.
A folde
d
casc
ode OT
A using curr
ent-mo
de g
a
in-
b
o
o
st
amplifi
e
r.
IEEE International
Confer
ence
Electronics, Proc
eedings, ICSE
. 201
0; 92-
95.
ICSE 20
10-
Processing IEEE International Confer
enc
e
on Semic
o
nductor Electronic
s
.
[4]
F
eng W
en
Xia
o
, Liu
T
i
e Jun, W
ang Z
ong
Min, 96:16
12.
A
full dif
f
erenti
a
l gai
n bo
ot
strap op
eratio
na
l
amplifi
e
r des
ig
n.
J microe
lectr
onics a
nd co
mputer
. 27(1
2
): 142-
145.
[5]
Seevi
n
ck, Evert; du Plessis, Monuko; Jou
bert,
T
r
udi-Hel
een; T
heron,
Arnol
d.
Active-
boot
strap
p
e
d
gai
n-en
ha
nce
m
ent techni
qu
e for lo
w
-
volt
a
ge circuit
s
.
IEEE
T
r
ansactions on Circuit
s and System
s
II:
Anal
og a
nd Di
git
a
l Sig
n
a
l
Pro
c
essin
g
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8; 45(9): 12
50-
12
54
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