Indonesi
an
Journa
l
of El
ect
ri
cal Engineer
ing
an
d
Comp
ut
er
Scie
nce
Vo
l.
1
3
,
No.
2
,
Febr
uar
y
201
9
, pp.
8
0
1
~
8
0
7
IS
S
N: 25
02
-
4752, DO
I: 10
.11
591/ijeecs
.v1
3
.i
2
.pp
8
0
1
-
8
0
7
801
Journ
al h
om
e
page
:
http:
//
ia
es
core.c
om/j
ourn
als/i
ndex.
ph
p/ij
eecs
A compa
riso
n
of
perfo
rmance bet
ween do
ub
le
-
gat
e and
gate
-
all
-
around
nanowir
e mosf
et
No
r
F
arez
a
K
os
m
an
i
1
, F
ati
mah
A.H
amid
2
,
M
. Anas
Raz
ali
3
1
Facul
t
y
of Elect
ric
a
l
and
E
lectr
o
nic
Engi
ne
eri
ng
,
Univer
sit
i
Tun
Hus
sein
Onn Mal
a
y
s
ia,
Johor,
Malay
si
a.
2
Facul
t
y
of Elect
ric
a
l
Eng
ineeri
n
g,
Dep
art
m
ent of
Com
pute
r and
E
le
c
troni
cs
Engi
n
ee
ring
,
Univer
siti
Te
kno
logi
Ma
lay
sia
,
J
ohor
Bahru, Ma
l
a
y
si
a.
3
Nano
Sim
ula
ti
o
n
Resea
r
ch
Grou
p
(NanoSIM
),
F
ac
ul
t
y
of
Elec
tr
i
ca
l
and
Elec
t
roni
c
Eng
ine
e
ring,
Univer
siti
Tun H
uss
ei
n
Onn Mal
a
y
s
ia,
Johor,
Malay
si
a.
Art
ic
le
In
f
o
ABSTR
A
CT
Art
ic
le
history:
Re
cei
ved
Oct
24
, 201
8
Re
vised
N
ov 25
, 2
018
Accepte
d
Dec
2
9
, 201
8
Due
to
th
e
r
ap
id
sca
l
ing
of
C
om
ple
m
ent
ar
y
Meta
l
-
Oxid
e
-
Se
m
ic
onduct
or
(CMO
S),
the
struct
ure
of
the
pl
a
nar
MO
SF
ET
a
pproa
che
s
the
sc
al
ing
li
m
it
s
when
the
short
cha
nn
el
eff
e
cts
(SCEs)
bec
o
m
e
the
m
ai
n
p
roble
m
.
Th
e
Double
-
Gate
an
d
Gate
-
all
-
Around
nanowir
e
MO
SF
ET
s
are
said
to
be
the
prom
ising
ca
ndi
dat
e
to
r
eplac
e
the
pla
n
ar
MO
SF
E
T
in
orde
r
to
pursue
CMO
S
sca
li
ng.
The
ref
or
e,
thi
s
p
ape
r
pr
ese
nt
the
result
of
d
evice
sim
ula
ti
on
using
Silva
co
T
CAD
tool
s
for
Double
-
Gate
an
d
Gate
-
All
-
Arou
nd
nanowir
e
MO
S
FETs.
Th
e
purpose
of
thi
s
sim
ula
ti
on
work
is
to
c
om
par
e
th
e
per
form
anc
e
of
GA
A
nanowir
e
and
DG
MO
SFE
T
and
the
n
stu
d
y
the
eff
e
ct
of
ph
y
sic
al
p
aram
et
er
on
elec
tr
i
ca
l
b
eha
vior
for
both
devi
c
es.
T
he
result
o
f
the
sim
ula
t
ed
m
odel
of
Gate
-
All
-
Around
na
nowire
is
compare
d
with
publi
shed
da
ta.
It
was
found
th
at
when
th
e
ga
t
e
le
ng
th
of
DG
was
sca
le
d
from
80nm
to
1
0nm
,
the
subthre
shold
slope
is
inc
rea
sing
from
6
2m
V/dec
to
162.
7m
V/dec
.
W
hil
e
for
GA
A
,
th
e
subthr
eshold
slope
is
in
cr
ea
sing
from
65.
8m
V/dec
to
127m
V/dec
.
T
he
thr
eshold
vo
lt
ag
e
in
DG
an
d
GA
A
at
Lg=
80nm
are
0
.
40646V
and
-
0
.
17505V
respe
ctively
.
Eve
n
tho
ugh
heav
y
doping
was
good
for
suppress
ing
SC
E,
the
lower
doping
con
centra
ti
on
is
desira
bl
e
as
the
DG
and
GAA
nanowir
e
had
hi
gher
on
-
stat
e
cu
rre
nts
with
1.
42x10
-
3A
and
3.
23x10
-
4A
res
pec
t
ive
l
y
.
It
al
s
o
show
ed
tha
t
t
he
thre
shold
volt
ag
e
of
DG
and
GA
A
nanowi
re
inc
r
ea
s
e
from
-
0.
0734V
to
0.
2312V
and
-
0.
0319V
to
0.
2
232V
respe
ct
iv
e
l
y
whe
n
the
channel
doping
is
var
ie
s
from
lower
to
high
er c
once
ntr
at
ion
.
Ke
yw
or
d
s
:
Com
ple
m
entary
Me
ta
l
-
Ox
ide
-
Sem
ic
on
duct
or
Dou
ble
-
Gate
MOSFET
Gate
-
All
-
A
rou
nd
MOS
F
ET
Shor
t c
ha
nn
el
eff
ect
s
(S
CEs
)
Tech
no
l
og
y
Com
pu
te
r
-
Aide
d
Desig
n (TCA
D
)
Copyright
©
201
9
Instit
ut
e
o
f Ad
vanc
ed
Engi
n
ee
r
ing
and
S
cienc
e
.
Al
l
rights re
serv
ed
.
Corres
pond
in
g
Aut
h
or
:
Muh
am
m
ad
A
nas
Bi
n R
azal
i,
Faculty
of
Ele
c
tri
cal
an
d
Ele
ct
ronic E
ng
i
neeri
ng
,
Un
i
ver
sit
i T
un
Hu
s
sei
n O
nn
Ma
la
ysi
a
,
Parit R
aja,
86400, Ba
tu
Pa
hat,
Johor.
Em
a
il
:
anas
@ut
hm
.ed
u.
m
y
1.
INTROD
U
CTION
Re
centl
y,
the
effor
ts
to
m
ake
a
m
iniat
ur
iz
at
ion
of
el
ect
r
on
ic
com
pone
nt
with
a
gr
eat
per
f
or
m
ance
are
act
ively
carried
out
by
in
du
st
ry.
The
re
quirem
ent
m
entio
n
by
the
ITR
S
[1]
an
d
dem
a
nd
from
the
i
ndus
try
for
high
spe
ed
and
lo
w
powe
r
de
vice
has
trigg
e
re
d
chipm
aker
s
a
nd
tra
ns
i
stor
de
sig
ner
to
pro
duce
a
reli
able
dev
ic
e.
T
heref
or
e
,
a
rap
id
sc
al
ing
towa
r
ds
nanoscale
re
gim
e
are
widely
done
to
inc
rea
se
the
chip
de
ns
it
y
in
order
t
o
achie
ve
a
g
reat
qu
al
it
y
pr
oduct.
N
ote
that
wh
e
n
the
cha
nn
el
le
ng
t
h
of
the
de
vices
is
narrowed
,
the
abili
ty
of
the
ga
te
to
con
tr
ol
the
cha
nnel
will
deg
ra
de.
T
his
will
le
ad
to
the
SCEs
pro
blem
su
ch
as
incr
ease
of
le
akag
e
c
urre
nt
,
thres
hold
volt
age
ro
ll
-
off
an
d
s
om
e
oth
ers
pro
blem
relat
ed
to
SC
E
[
2]
.
Si
nce
plana
r
MOSFET
ca
n
no
l
onge
r
su
sta
in
the
SCE
pro
blem
wh
en
sca
li
ng
do
wn,
m
a
ny
al
te
rn
at
ives
hav
e
bee
n
pr
opose
d
Evaluation Warning : The document was created with Spire.PDF for Python.
IS
S
N
:
2502
-
4752
Ind
on
esi
a
n
J
E
le
c Eng &
Co
m
p
Sci,
Vo
l.
1
3
, N
o.
2
,
Fe
bru
ary
201
9
:
8
0
1
–
8
0
7
802
to
ove
rco
m
e
the
pro
blem
.
Do
uble
-
Gate
(DG)
an
d
Gate
-
All
-
A
rou
nd
na
nowire
(
GAA
nano
wire)
MO
SFET
hav
e
bee
n
co
nsi
der
e
d
as
reli
able
ca
nd
i
date
to
rep
la
ce
t
he
plana
r
M
OS
F
ET
[3
-
5]
.
Ma
ny
of
the
a
rc
hitec
tures
that
hav
e
bee
n
pro
po
se
d
c
onsist
of
tw
o
or
m
or
e
gates
to
con
t
ro
l
the
c
ha
nn
el
.
B
oth
of
t
he
de
vice
are
able
t
o
exten
d
the
use
of CM
OS
tec
hnol
og
y a
s they
are
good at s
uppr
essi
ng SCE
[
6]
.
The
proces
s
of
pe
rfor
m
ance
e
nh
a
ncem
ent
an
d
m
od
ific
at
io
n
of
the
dev
ic
e
need
to
be
co
nt
in
ued
ov
e
r
tim
e
to
identif
y
the
op
ti
m
u
m
con
diti
ons
that
a
dev
ic
e
c
an
achie
ve.
H
ence,
a
ne
w
s
tructu
re
desi
gn,
a
nd
dim
ension
s
ho
uld
be
im
pr
oved
to
keep
th
e
SCE
pr
oble
m
un
der
c
on
tr
ol
wh
e
n
scal
ing
down
the
channel
le
ng
th
.
By
m
a
nipulat
ing
the
ph
ysi
cal
par
a
m
et
ers
su
ch
as
sil
ic
on
thickne
ss
(tsi),
gate
le
ng
th
(
Lg
)
an
d
al
so
doping
c
oncen
trat
ion
will
hel
p
to
im
pr
ov
e
t
he
perform
ance
of
the
de
vice.
He
nce,
the
tr
ansf
e
r
c
har
act
e
risti
cs
(ID
-
VG),
le
ad
s
to
m
easur
in
g
sever
al
dev
ic
e
par
am
et
ers
su
c
h
as
subth
res
hold
slo
pe
(
SS),
T
hr
es
hold
V
ol
ta
ge
(V
T
H),
an
d
al
so
the
rati
o
of
ION/IOFF.
T
hese
pa
ram
et
e
rs
will
disclos
e
the
eff
ect
of
scal
ing
to
wards
th
e
perform
ance o
f
the
dev
ic
e
.
2.
DEVICE ST
R
UC
T
UR
E
AN
D
SI
M
ULATI
ON
3D
view
of
th
e
pro
po
se
d
cy
li
ndrical
gate
-
a
ll
-
around
na
nowire
MO
SFET
gen
e
ra
te
d
by
ATL
AS
a
s
sh
ow
n
in
Fi
gur
e 1
.
Figure
1
.
3D
vi
ew of
the
pro
pose
d
cy
li
ndrica
l gate
-
al
l
-
ar
ound
nano
wire M
OS
FE
T
gen
e
ra
te
d
by
ATL
AS
The
de
vice
sim
ula
ti
on
was
done
by
us
in
g
ATL
AS
sim
ul
at
or
in
Sil
vac
o
TCAD
to
ol.
Both
D
G
an
d
GAA
MOS
FE
T
hav
e
n
-
ty
pe
channels
with
a
doping
re
gion
of
NA
=
1.4
5x10
10
cm
-
3,
w
hile
the
so
urce
/drain
doping
co
nce
nt
rati
on
was
set
to
1x1020
cm
-
3.
Ba
sic
al
l
y,
the
ph
ysi
cal
par
am
et
ers
that
con
sist
of
th
e
gate
le
ng
th
(L
g)
tha
t was set to 1
µm
,
1
0n
m
f
or
th
e sil
ic
on
thick
ne
ss (
tsi
)
an
d
th
e g
at
e o
xi
de
th
ic
kn
ess
(to
x)
w
as set
to
1.5
nm
.
Figure
2
sho
ws
the
il
lustrati
on
of
the
D
G
a
nd
G
AA
M
OSFET
cro
ss
-
sect
io
n
s
tructu
re
us
ed
in
thi
s
stud
y.
The
a
dv
antage
of
na
no
wire
c
hannel
i
s
that
it
will
red
uce
the
c
orne
r
ef
fects
that
l
ead
to
l
ow
e
r
c
urren
t
dr
i
ve
face
b
y t
he
c
ub
ic
al
c
ha
nn
el
[
7]
.
(a)
(b)
Figure
2
.
(
a
)
T
he
str
uctu
re
of
DG MOS
FET
and (
b) GA
A n
anowire
MOS
FET
First
of
al
l,
th
e
de
vice
sim
ul
at
or
is
us
e
d
to
validat
e
m
od
e
ls
of
G
AA
M
OS
FE
T
wit
h
the
publishe
d
data
[8]
.
Fig
ure
3
sh
ows
the
com
par
ison
of
I
-
V
char
act
e
ris
ti
cs
that
hav
e
a
good
ag
reem
e
nt
wh
e
n
com
par
ed
to
the r
e
fer
e
nce
m
od
el
.
Evaluation Warning : The document was created with Spire.PDF for Python.
Ind
on
esi
a
n
J
E
le
c Eng &
Co
m
p
Sci
IS
S
N:
25
02
-
4752
A com
pa
ris
on
of p
e
rfor
mance
b
et
we
en
do
ub
l
e
-
ga
te
and g
ate
-
all
-
aroun
d n
anowire…
(
No
r Fa
r
eza
Kos
m
an
i
)
803
Figure
3
.
Tr
a
nsfer c
ha
racteri
sti
cs at V
DS
=
0.1V a
nd 1.0V
of the
sim
ulate
d
de
vice an
d
t
he
r
efe
re
nce m
odel
(d
as
he
d
li
ne
)
3.
RESU
LT
S
A
ND AN
ALYSIS
3.1.
Co
m
pari
so
n
of G
A
A a
nd DG
MO
SF
ET
Perfo
r
ma
nces
We
com
par
ed
the
basic
m
odel
of
DG
a
nd
GAA
na
n
ow
ir
e
with
the
sam
e
ph
ysi
cal
par
am
et
er
and
dim
ension
to
obser
ve
thei
r
pe
rfor
m
ance.
Fig
ur
e
4
s
hows
t
he
com
par
ison
of
tra
nsfer
c
ha
racteri
sti
cs
for
bo
t
h
DG
a
nd
G
A
A
MOSFET
.
T
he
res
ults
sho
w
that
G
A
A
has
a
bi
gger
ION/I
OF
F
rati
o
with
4.3
95x101
1
com
par
ed
to
D
G
wi
th
6.3
78x108.
A
bi
gger
ION/I
OF
F
rati
o
will
le
ad
to
a
bette
r
pe
rfor
m
ance
an
d
ver
y
sm
a
l
l
of
I
OFF
curre
nt
is
essenti
al
fo
r
sta
ti
c
po
we
r
r
edu
ct
io
n
w
hile
the
dev
ic
e
is
in
an
idle
sta
te
[9]
.
E
ven
th
ou
gh
th
e
on
-
sta
te
curre
nt
of
G
AA
is
s
m
al
le
r,
it
has
a
ver
y
sm
all
of
f
-
sta
te
current
Be
sides
that,
DG
has
bette
r
value
of
SS
with
59.6
m
V/dec
co
m
par
ed
to
G
AA
MOSFET
with
221.8
of
SS
value.
N
or
m
ally,
dev
ic
es
t
ha
t
have
bette
r
SCE
im
m
un
it
y has b
et
te
r
cha
racteri
st
ic
s o
f
SS w
he
r
e the
desire
d v
al
ue
is at
60
m
V/dec.
Figure
4
.
Tr
a
nsfer c
ha
racteri
sti
cs o
f
sim
ulated
DG an
d G
A
A
MO
SFET
at
VD =
0.1V an
d 1.0V
3.2.
The E
ff
ec
t of
V
aria
tion
Phy
sic
al P
arameter
to
w
ards E
le
ctrical B
e
havior
The
process
of
scal
ing
MO
S
FET
will
eve
nt
ually
le
ad
to
a
sm
aller
gate
l
eng
t
h,
oxide
th
ic
kn
ess
a
nd
al
so
the
chann
el
thickness.
T
hu
s
,
in
orde
r
to
obser
ve
the
perform
ance
of
the
dev
ic
e,
t
h
e
var
ia
ti
on
of
the
scal
ed
dim
ension
m
us
t
be
si
m
ultaneou
sly
ob
se
rv
e
d
wit
h
the
relat
ed
el
ect
rical
par
am
et
er
char
act
erist
ic
s.
Firstl
y,
this
stud
y
f
oc
us
es
on
the
scal
in
g
of
gate
le
ngth.
By
ta
kin
g
the
var
i
ou
s
gate
le
ng
t
hs
sta
rtin
g
from
80nm
,
60
nm
,
40nm
,
20
nm
to
10nm
,
observ
at
io
ns
have
been
m
ade
reg
ar
ding
th
e
su
bt
hr
es
hold
value,
thres
ho
l
d
volt
age,
I
ON
a
nd
I
OFF
.
The
re
duct
io
n
of
the
dr
ai
n
c
urren
t
was
noti
ceable
as
the
ga
te
le
ng
th
inc
r
ease
d
du
e
to
high
c
ha
nn
el
resist
anc
e
[10]
.
Wh
e
n
t
he
gate
le
ngth
is
shorter
,
it
c
le
arly
sh
ows
t
hat
the
s
ubth
re
sh
ol
d
slop
e
will
incr
ease
du
e
t
o
the
increasin
g
dr
a
in
curre
nt
as
sh
ow
n
in
Fig
ur
e
5.
T
he
fig
ure
sh
ows
the
sim
ulati
on
resu
lt
s
of
s
ub
t
hr
es
hold
slo
pe
for
bo
t
h
DG
a
nd
G
A
A
wh
e
n
the
gate
le
ngt
h
is
va
ried.
Bu
t
the
inc
rem
ent
rate
of
su
bt
hr
e
shold
sl
op
e
for
GAA
i
s
m
uch
bette
r
t
han
D
G
beca
use
it
is
sti
l
l
in
the
acce
pta
ble
values
e
ve
n
th
ough
the g
at
e le
ngth
appr
oach
es
10
nm
.
Evaluation Warning : The document was created with Spire.PDF for Python.
IS
S
N
:
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4752
Ind
on
esi
a
n
J
E
le
c Eng &
Co
m
p
Sci,
Vo
l.
1
3
, N
o.
2
,
Fe
bru
ary
201
9
:
8
0
1
–
8
0
7
804
Figure
5
.
S
ub
t
hr
es
hold
slo
pe
of DG a
nd GA
A
MO
SFET
s
with
var
ia
ti
on
of g
at
e le
ng
t
h (
Lg)
Be
sides
that,
the
ef
fect
of
t
he
gate
le
ng
t
h
s
cal
ing
to
wards
the
thres
ho
l
d
vo
lt
age
has
be
en
pl
otted
in
the
gr
a
ph
to
s
ee
the
beh
a
vior
of
the
el
ect
rical
par
am
et
er.
Figu
re
6
sho
ws
the
relat
ionship
of
the
thr
esh
ol
d
vo
lt
age
with
t
he
var
ia
ti
on
of
gate
le
ngth.
I
n
al
l
cases,
belo
w
the
c
riti
cal
l
eng
t
h
L
g>10
0nm
,
threshold
vo
lt
ag
e
will
decr
ease
with
the
dec
re
asi
ng
gate
le
ngth.
O
nce
the
cr
it
ic
al
le
ng
th
is
m
et
,
the
pr
ope
rtie
s
of
the
th
r
esh
old
vo
lt
age
c
an
be
var
i
e
d.
Ba
se
d
on
obser
vatio
ns
,
t
he
re
du
ct
i
on
rate
of
the
thres
ho
l
d
volt
a
ge
in
DG
is
s
m
al
le
r
than
in
GAA.
A
lowe
r
th
reshold
volt
age
is
desira
ble
espec
ia
ll
y
fo
r
low
powe
r
ap
plica
ti
on.
It
was
f
ou
nd
that
GAA
M
OS
FE
T
ha
ving
a
bet
te
r
subth
res
ho
l
d
slo
pe
but
the
n
it
ha
s
a
reall
y
low
t
hr
es
hold
vo
lt
age
com
par
e
d
to DG.
Figure
6
.
Thres
ho
l
d Vo
lt
age
c
har
act
erist
ic
s
of DG a
nd
GAA
MOSFE
Ts
versus
t
he gate
len
gth
,
L
g
On
e
of
the
wa
ys
to
op
ti
m
iz
e
the
char
act
eri
sti
cs
of
MOSF
ET
de
vice
is
t
o
m
od
ify
the
sil
ic
on
fil
m
thickne
ss.
It
is
pr
act
ic
al
to
de
pend
on
the
film
thickness
si
nce
it
is
desira
ble
to
le
sse
n
th
e
floati
ng
bo
dy
eff
ect
.
Figure
7
s
how
s
the
relat
ion
s
hi
p
bet
ween
the
thres
hold
volt
age
a
nd
the
sil
ic
on
film
thickness.
T
he
gate
le
ng
t
h
was
set
t
o
1µm
.
Ba
sed
on
obs
erv
at
io
n,
the
t
hresh
old
volt
ag
e
of
the
de
vice
will
increa
se
wh
e
n
t
he
sil
ic
on
fil
m
thickne
ss
i
ncr
e
ase.
St
ud
ie
s
ha
ve
fou
nd
that
e
ven
th
ough
t
he
re
is
only
sm
all
increm
ent,
th
e
val
ue
of
th
re
sh
ol
d
vo
lt
age
inc
rea
se
with
t
he
in
creasin
g
of
sil
ic
on
film
thick
ne
ss
[
11]
.
Bu
t
wh
e
n
a
ppr
oa
chin
g
L
g
<
30nm
,
the
resu
lt
s
m
ay
be
con
tra
dict.
W
hen
t
he
sil
ic
on
fil
m
thickness
is
gr
eat
er,
t
he
increasin
g
width
of
the
de
pleti
on
reg
i
on
s
will
de
creases
t
he
s
ource/b
od
y
a
nd
drai
n/bo
dy
ju
nction
ca
pacit
anc
e.
It
will
cause
the
gate
an
d
s
urfac
e
po
te
ntial
coup
li
ng
incr
ea
ses,
thu
s
the
th
r
esh
old
volt
ag
e
decr
eases
with
the
inc
r
ease
of
sil
ic
on
film
thickne
ss
[
12]
.
It
sho
ws
that
t
he
ga
te
le
ng
t
h
do
e
f
fect
the
r
el
at
ion
sh
i
p
bet
ween
thre
shol
d
volt
age
a
nd
sil
ic
on
thickne
ss.
The
gate
le
ng
th
and
the
fil
m
thickne
ss
sho
uld
not
be
e
xc
essivel
y
scal
ed
eve
n
th
ough
the
li
tho
grap
hy all
ow
e
d
it
in
or
de
r
to
m
ini
m
iz
e t
he
SCE
.
W
it
h
the
gate
le
ng
th
scal
in
g
ap
proac
hing
sub
-
100nm
reg
im
e,
the
body
-
doping
c
oncent
rati
on
beco
m
es
on
e
of
the
require
m
ents
to
con
tr
ol
the
SCEs
a
nd
im
pr
oves
the
pe
rfor
m
ance
of
the
dev
ic
e
[13]
.
Figure
8
sho
ws
the
c
om
par
iso
n
of
I
-
V
c
har
act
erist
ic
f
or
bo
t
h
D
G
a
nd
G
AA
with
two
diff
e
re
nt
dopi
ng
con
ce
ntrati
ons
.
Since
early
sim
ula
ti
on
s
ha
ve
i
m
ple
m
ented
l
ow
doping
c
oncentrati
on
f
or
t
he
cha
nnel
,
this
par
t
of
t
he
stu
dy
is
to
com
par
e
a
nd
obser
ve
th
e
el
ect
rical
behavio
r
f
or
li
ghtl
y
doped,
3x
10
16
cm
-
3
and
the
heavy
dope
d
c
hannel
with
5x10
18
cm
-
3
.
Heav
y
c
ha
nn
el
dopi
ng
con
ce
ntrati
on
i
s
desira
ble
f
or
suppressi
ng
S
CEs.
Evaluation Warning : The document was created with Spire.PDF for Python.
Ind
on
esi
a
n
J
E
le
c Eng &
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m
p
Sci
IS
S
N:
25
02
-
4752
A com
pa
ris
on
of p
e
rfor
mance
b
et
we
en
do
ub
l
e
-
ga
te
and g
ate
-
all
-
aroun
d n
anowire…
(
No
r Fa
r
eza
Kos
m
an
i
)
805
Howe
ver
the
l
ow
e
r
do
ping
con
ce
ntrati
on
resu
lt
s
in
a
be
tt
er
sat
ur
at
io
n
re
gion
an
d
higher
c
urre
nt
dr
ive
.
Be
sides
that,
lowe
rin
g
the
con
ce
ntrati
on
of
the
dopi
ng
will
le
ad
to
bette
r
m
ob
il
i
ty
and
le
ss
ve
locit
y
sat
ur
at
io
n
[14]
.
Figure
7
.
Thres
ho
l
d vo
lt
ag
e Vt
h
ve
rs
us
sil
ic
on
fil
m
thickn
es
s Tsi
Figure
8
.
I
D
-
V
G
curves
of
DG an
d GAA
for diffe
re
nt conce
ntrati
on
of
body
d
opin
g p
rofil
e
Table
1
s
how
the
res
ults
of
va
rio
us
e
le
ct
rical
par
a
m
et
er
of
both
dev
ic
e
w
he
n
the
do
pi
ng
con
ce
ntrati
on
is
var
ie
d.
It
s
hows
that
the
valu
e
of
the
subth
res
ho
l
d
slop
e
dec
rease
d
wh
e
n
the
dopi
ng
con
ce
ntrati
on,
as
well
as
the
dr
ai
n
curre
nt
increase
d.
Me
a
nwhile
,
the
val
ue
of
thres
hold
vo
lt
age
will
increase
wh
e
n
ap
proac
hi
ng
hi
gh
e
r
dopi
ng
c
o
nce
ntrati
on.
As
f
or
D
G
,
the
threshold
vo
lt
age
inc
reas
ed
from
-
0.
0734V
to
0.231
2V
w
hen
the
do
ping
co
ncen
t
rati
on
is
changin
g
from
low
-
do
ped
t
o
heav
y
-
do
ped.
The
GAA
nanow
i
r
e
had
a
sm
aller
increm
ent
of
t
hr
es
hold
volt
age
from
-
0.0
319V
t
o
0.2
232V
wh
e
n
the
dopi
ng
c
on
ce
nt
rati
on
increase
d.
Table
1.
T
he
r
e
su
lt
s of elect
ric
al
p
aram
et
er f
or DG a
nd
GAA
n
a
nowire
MO
SFET
with
va
r
y dopin
g
con
ce
ntrati
on
Dev
ice
Para
m
eter
Low
-
d
o
p
ed
(1x
1
0
1
0
cm
-
3
)
m
o
d
e
ratel
y
-
d
o
p
ed
(3x
1
0
1
6
cm
-
3
)
Heavy
-
d
o
p
ed
(5x
1
0
1
8
cm
-
3
)
DG
I
ON
(A
)
1
.42
x
1
0
-
3
1
.42
x
1
0
-
3
9
.99
x
1
0
-
4
I
OFF
(A)
I
ON
/I
O
FF
ra
tio
2
.99
x
1
0
-
12
2
.11
x
1
0
-
9
3
.17
x
1
0
-
12
2
.23
x
1
0
-
9
2
.36
7
x
1
0
-
15
2
.37
x
1
0
-
12
SS(
m
V
/d
ec)
5
9
.6
5
9
.5
4
8
.9
V
T
H
(V)
-
0
.07
2
1
-
0
.04
1
5
0
.40
2
0
GAA
I
ON
(A
)
3
.23
x
1
0
-
4
3
.23
x
1
0
-
4
4
.69
x
1
0
-
4
I
OFF
(A)
I
ON
/I
O
FF
ra
tio
8
.69
x
1
0
-
7
2
.69
x
1
0
-
3
8
.92
x
1
0
-
7
2
.76
x
1
0
-
3
9
.46
x
1
0
-
11
2
.02
x
1
0
-
7
SS(
m
V
/d
ec)
2
2
1
.8
2
1
9
.5
6
2
.7
V
TH
(V)
-
0
.03
1
9
-
0
.03
0
3
0
.22
3
2
Evaluation Warning : The document was created with Spire.PDF for Python.
IS
S
N
:
2502
-
4752
Ind
on
esi
a
n
J
E
le
c Eng &
Co
m
p
Sci,
Vo
l.
1
3
, N
o.
2
,
Fe
bru
ary
201
9
:
8
0
1
–
8
0
7
806
4.
CONCL
US
I
O
N
The
sim
ulatio
n
of
m
od
el
DG
and
GAA
was
com
plete
d
us
in
g
Sil
vaco
TC
A
D
too
ls.
T
he
c
om
par
ison
of
p
e
rfor
m
ance
betwee
n
the
D
G
a
nd G
A
A
was
ob
se
r
ved
a
nd
an
al
yse
d.
E
ven
th
ough
the
re
are
c
ha
ng
i
ng
in
t
he
dim
ension
w
he
n
scal
ing
the
tr
ansisto
r
siz
e,
the
de
gr
a
datio
n
rate
of
G
AA
i
s
sti
ll
bette
r
than
in
D
G.
Wh
e
n
gate
le
ng
th
is
s
hort
er,
the
s
ubth
re
sh
ol
d
slo
pe
will
increase
es
pe
ci
al
ly
wh
en
L
g<
30nm
.
It
sh
ows
that
DG
wi
ll
hav
e
higher
s
ubth
re
sh
ol
d
slo
pe
with
162.7m
V/de
c
com
par
ed
t
o
G
A
A
with
127m
V/dec
w
hen
Lg<
30nm
.
W
hile
wh
e
n
L
g>
30nm
,
GA
A
ha
ve
bette
r
subt
hr
es
ho
l
d
tre
nd
w
hich
are
nea
rly
-
ide
al
val
ue
com
par
e
d
to
D
G.
Be
sides
that,
the
cha
nges
in
doping
c
on
ce
ntrati
on
gi
ves
an
im
pact
on
the
de
vice
as
it
pr
ovides
a
hig
he
r
drai
n
curren
t
and
dec
reases
thres
ho
l
d
vo
lt
a
ge
w
he
n
the
body
c
oncentrat
ion
is
lo
we
r.
Wh
il
e
heav
y
dope
d
reg
i
on
is
good
SCE
co
ntr
o
ll
er
.
Lo
we
r
-
dope
d
cha
nn
el
s
i
n
G
AA
ha
d
3.23x
10
-
4
A
of
on
-
s
ta
te
cur
re
nt
a
nd
th
res
ho
l
d
vo
l
ta
ge
of
-
0.0
319V
com
par
e
d
to
hea
vy
-
do
ped
wit
h
4.69x
10
-
4A
an
d
0.223
2V
re
sp
e
ct
ively
.
Ho
we
ver,
DG
M
OSFET
is
ben
e
fici
al
fo
r
ultral
ow
powe
r
ap
plica
ti
on
due
to
it
s
near
-
i
deal
subthre
shold
slo
pe
cha
r
act
erist
ic
s
and
it
can
al
so
achieve
be
tt
er
isolat
ion
at
lower
co
ntr
ol
vo
lt
age.
T
he
beh
a
vior
sho
w
ed
by
G
AA
in
dicat
es
that
it
i
s
m
or
e
aff
ect
ive i
n
s
uppressi
ng
short
-
cha
nnel
-
ef
fect
s than D
G
M
O
SFET at L
g=
1µm
. Th
is i
s
be
cause
GAA ha
s b
et
t
er
thres
ho
l
d
vo
lt
a
ge
c
har
act
e
risti
cs,
e
xh
i
bits
higher
I
ON
/I
OFF
com
par
ed
t
o
th
e
D
G
MO
SFE
T.
T
he
degra
da
ti
on
rate
of
s
ubthre
sh
ol
d
sl
op
e
in
GAA
is
bette
r
com
par
ed
t
o
D
G
wh
e
n
scal
i
ng.
It
al
so
f
ound
that,
G
A
A
is
m
or
e
su
it
able
for
high
s
pee
d
a
nd
lo
w
powe
r
a
pp
li
ca
ti
on
si
nce
it
can
reduce
SC
E
an
d
has
bett
er
perform
ance
w
hen
scal
ing
c
om
par
ed
to
plana
r
MOSFET
.
B
ut,
the
fa
br
ic
at
io
n
a
nd
pr
ocess
var
ia
ti
on
is
sti
ll
a
co
ncern
f
or
G
A
A
nano
wire
w
hen it
co
ntin
ues
to
scali
ng do
wn.
ACKN
OWLE
DGE
MENTS
The
aut
hors
w
ou
l
d
li
ke
to
ac
knowle
dge
the
finan
ci
al
s
upport
f
ro
m
the
Re
search
U
niv
er
sit
y
gr
ant
of
the
Mi
nistry
of
Higher
Ed
ucati
on
(M
OHE),
Ma
la
ysi
a
unde
r
the
F
un
dam
ental
Re
se
arch
Grant
Sc
hem
e
(F
RG
S)
vot
no
1535.
Also
t
hanks
to
t
he
R
esearch
Ma
na
gem
ent
Ce
ntr
e
(RMC
)
of
U
ni
ver
sit
i
Tu
n
H
us
sei
n
Onn
Ma
la
ysi
a
(
UTH
M
)
a
nd
Un
i
ver
sit
i
Tek
no
l
og
i
Ma
la
ysi
a
(U
TM)
f
or
pro
vid
i
ng
e
xcell
ent
re
searc
h
m
anag
em
ent an
d faci
li
ti
es in
wh
ic
h
to
co
m
plete
this work.
REFERE
NCE
S
[1]
“
Inte
rna
ti
on
al t
e
chnol
og
y
ro
admap
for
sem
ic
ond
uct
ors,” p. 47, 2
015
[htt
p
//
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it
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P.
Raz
av
i
and
A.
A.
Orouji,
“
Dual
m
at
erial
g
at
e
ox
ide
sta
ck
s
y
m
m
et
ric
doub
le
ga
te
MO
SF
ET
:
Im
proving
short
cha
nne
l
ef
fects
of
nanosc
a
le
do
uble
g
at
e
MO
SFE
T,”
B
EC
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-
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Y.
Jiang
e
t
al
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,
“
Perform
anc
e
bre
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hrough
in
8
nm
gat
e
l
en
gth
Gate
-
Al
l
-
Around
Nanowire
Tra
nsistors
usi
ng
m
et
al
lic
n
anowir
e
con
tacts,
”
IE
E
E
Symp. V
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Te
chnol
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S.
K.
Mohapa
tra
,
K.
P.
Pradha
n,
and
P.
K.
Sahu,
“
Eff
ec
t
of
c
hanne
l
&
ga
te
e
ngine
er
ing
on
Double
Gate
(DG
)
MO
S
FET
-
A c
o
m
par
at
ive stud
y
,
”
2012
In
t. Conf
.
Eme
rg.
Elec
tro
n.
ICE
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–
6
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I.
Rav
i
Shanka
r,
Gaura
v
Kaus
hal
,
Sati
shM
ahes
hw
ara
m
,
Sudeb
Dasgupta,
an
d
S.
K.Manha
s
,
Mem
ber
an
d
Abs
tra
ct
—
Th
e,
“
A
Degra
dat
ion
Model
of
Double
Gate
and
Gat
e
-
All
-
Around
MO
SF
ET
sW
it
h
In
te
rfa
ce
T
rap
pe
d
Charge
s
Inc
luding
Eff
e
ct
s
of
Ch
anne
lMobil
e
Ch
arg
e
C
arr
i
ers,
”
I
EE
E
Tr
ans.
Dev
ic
e
Mate
r
.
R
el
ia
b.
,
vo
l.
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no
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2
,
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689
–
697
,
20
14.
[6]
V.
Kum
ar,
R.
Gupta,
R
.
Pree
t
,
P.
Singh,
and
R.
V
ai
d,
“
Perform
an
ce
an
aly
sis
of
Double
Gat
e
n
-
Fin
FET
using
High
-
k
dielectri
c
m
ate
ria
ls,
”
In
t. J
.
Inn
ov.
Re
s.
Sc
i. E
ng
.
Techno
l.
,
vo
l. 5
,
no
.
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,
pp
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2
–
13249,
2016
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[7]
M.
J.
Islam
and
S.
U.
Farwah
,
“
Silva
co
TCAD
b
ase
d
an
aly
sis
of
c
y
li
ndri
cal
Gat
e
-
All
-
Around
FE
T
hav
ing
Indium
Ars
eni
de
as
channel
and
Alum
in
ium
Oxide
as
gat
e
diele
ct
ri
cs,
”
J.
Nanote
chnol.
its
Appl
.
Eng
.
,
vol
.
1,
no.
1
,
pp.
1
–
12,
2016
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[8]
B.
Yu,
H.
Lu,
M.
Li
u,
and
Y.
Ta
ur,
“
Explici
t
cont
inuous
m
odel
s
for
Do
uble
-
Gat
e
and
Surrounding
-
Gat
e
MO
S
FET,
”
IEEE
Tr
ans.
Elec
tron De
vice
s
,
vol
.
5
4,
no
.
10
,
pp
.
27
15
–
2722,
2007
.
[9]
B.
Jena
,
B
.
S.
Ramkrishna,
S.
Dash,
and
G.
P.
Mishra,
“
Conica
l
surrounding
g
a
te
MO
SF
ET
:
A
poss
ibi
li
t
y
in
ga
t
e
-
all
-
aro
und
f
amil
y
,
”
Adv.
Na
t. Sc
i
.
Nanosci
.
Nano
t
ec
hnol
.
,
vol
.
7
,
n
o.
1
,
2016
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[10]
S.
Kum
ar,
H.
Parde
shi,
G.
Ra
j,
a
nd
N.
M.
Kum
ar,
“
Im
pac
t
of
gate
le
ngth
and
bar
rie
r
thickness
on
per
form
anc
e
of
InP /
InGaAs
base
d
Double
Gat
e
Meta
l
–
Oxide
-
Sem
ic
onduc
tor H
et
ero
struc
ture
Fiel
d
-
Eff
ec
t
Trans
istor
(
DG
MOS
-
HF
ET
)”
,
Superl
att
ices and Mic
r
ostructures
vol.
55,
pp
.
8
-
15
,
20
13.
[11]
B.
Majkusia
k
,
T
.
Janik,
and
J.
W
al
c
za
k
,
“
Sem
ic
onduct
or
thicknes
s
eff
ec
ts
in
the
d
ouble
-
ga
te
SO
I
MO
S
FET,
”
I
EEE
Tr
ans.
El
ectron
Dev
i
c
es
,
vo
l. 45, no. 5, pp. 1127
–
1134,
1998
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[12]
J.
Park
and
J.
C
oli
nge
,
“
Multi
pl
e
-
Gate
SO
I
MO
SF
ET
s :
Devic
e
design
guidelines
,
”
IEEE
Tr
ans.
El
e
ct
ron
Dev
i
ces
,
vol.
49
,
no
.
12
,
p
p.
2222
–
2229
,
2
002.
[13]
A.
A.
Z
ia
b
ari
,
M.
Charmi,
and
H.
R.
Masha
y
e
khi,
“
The
impac
t
of
bod
y
dop
ing
con
ce
ntr
at
ion
on
th
e
per
form
ance
o
f
nano
DG
-
MO
SFE
Ts:
A qu
ant
um
sim
ula
ti
on
,
”
Ch
ine
se
J. P
h
ys.
,
v
ol.
51
,
no
.
4
,
pp
.
844
–
853,
2013
.
[14]
Sapna
and
B.
Meha
ndia,
“
Stud
y
of
el
e
ct
ri
cal
cha
ra
cteri
sti
cs
of
SO
I
MOSF
ET
using
silva
co
TCAD
si
m
ula
to
r,
”
Curr
.
Tr
ends
Technol
.
Sc
i.
,
vol
.
1,
no
.
1
,
pp
.
15
–
18,
2012
.
Evaluation Warning : The document was created with Spire.PDF for Python.
Ind
on
esi
a
n
J
E
le
c Eng &
Co
m
p
Sci
IS
S
N:
25
02
-
4752
A com
pa
ris
on
of p
e
rfor
mance
b
et
we
en
do
ub
l
e
-
ga
te
and g
ate
-
all
-
aroun
d n
anowire…
(
No
r Fa
r
eza
Kos
m
an
i
)
807
BIOGR
AP
HI
ES OF
A
UTH
ORS
Nor
Fare
z
a
Bin
ti
Kos
m
ani
was
born
in
Johor,
Malay
si
a
in
1
994.
She
r
ecei
v
ed
th
e
B
.
S
degr
ee
s
in
elec
t
ronic
engi
n
ee
rin
g
from
Univer
siti
Tun
Hus
sein
Onn
Malay
sia
(
UTHM
)
in
2017
and
is
cur
ren
tly
working
to
ward
the
M.S.
d
egr
ee.
Her
cur
r
e
nt
rese
ar
ch
inter
ests
inc
lude
sem
ic
onduct
or
nanoe
l
ec
tron
ic
devi
c
es
sim
ula
ti
on
proc
ess
and
the
appl
i
c
at
ions
of
nanode
vi
ce
s.
Fati
m
ah
Khair
i
a
h
Abd
Ham
id
re
ce
iv
ed
th
e
B.
S
a
nd
M.S.
degr
ee
s
in
elec
troni
c
en
gine
er
ing
from
Univer
siti
Te
knologi
Mal
a
y
sia
(UTM)
in
2011
and
2013,
respe
ct
iv
ely
.
She
i
s
cur
ren
t
l
y
working
towar
d
the
PH
.
D
d
egr
ee
with
the
D
epa
rt
m
ent
of
E
lectr
i
c
al
Com
pute
r
En
gin
ee
r
ing
,
Univer
siti
T
ekn
ologi
Malay
si
a.
Her
int
ere
sts
include
sili
con
n
an
owire
devi
c
es
a
nd
var
ious
appl
i
ca
t
ions o
f m
ic
ro
-
and
nano
devi
c
es.
Muham
m
ad
An
as
Raz
a
li
re
ce
i
ved
the
B.
En
g
degr
ee
in
elec
tron
ic
s
engi
n
ee
ring
from
Univer
siti
Te
kn
ologi
Mal
a
y
s
ia
(UTM),
Skudai,
Johor,
Mal
a
y
s
i
a
in
2006
.
He
r
ec
e
ive
d
the
MS
c
(Nanoe
le
c
t
ronic
dev
ic
es)
a
nd
PhD
(El
ec
tro
nic
Eng
ine
er
ing)
degr
ee
s
from
Univer
sit
y
of
Surre
y
,
Surre
y
,
UK
in
2008
an
d
2015,
respe
c
t
ive
l
y
.
Sinc
e
20
15,
he
has
b
een
with
the
Depa
rtment
of
E
le
c
troni
c
Eng
ineeri
ng,
Univer
si
ti
Tun
Hus
sein
On
n
Malay
si
a
(UT
HM
),
Parit
Raj
a
,
Johor,
Ma
lay
s
ia
as
a
l
ectu
rer
.
His
rese
ar
c
h
int
ere
sts
in
cl
u
de
sem
ic
onductor
m
at
eri
a
l,
sem
ic
onduct
or
n
anoe
l
ec
tron
ic device
s f
abr
i
ca
t
ion
and
sim
ulation
proc
ess.
Evaluation Warning : The document was created with Spire.PDF for Python.