Indonesian J
ournal of Ele
c
trical Engin
eering and
Computer Sci
e
nce
Vol. 1, No. 2,
February 20
1
6
, pp. 273 ~
281
DOI: 10.115
9
1
/ijeecs.v1.i2.pp27
3-2
8
1
273
Re
cei
v
ed
No
vem
ber 1, 20
15; Re
vised Janua
ry 1
1
, 20
16; Accepted
Jan
uary 23, 2
016
Prediction of a New Cascaded Hybrid Multilevel Invert
e
r
with Le
ss Device Count
C.R.Balamur
ugan*, S.P.Natar
a
jan, R.Bensraj
Aruna
i Engi
ne
erin
g Col
l
eg
e, T
i
ruvannama
l
a
i
, India
*Corres
p
o
ndi
n
g
author, e-ma
i
l
: crbala
i
n2
01
0
@
gmai
l.com
A
b
st
r
a
ct
Multilev
e
l
inv
e
rters have
b
e
en
opted
for
hig
h
p
o
w
e
r a
pplic
atio
ns d
u
e
to re
duc
ed
har
mo
nic
distortio
n
, less
device v
o
ltag
e stress and
mo
du
lar stru
cture. T
h
is w
o
rk propos
es n
e
w
mo
difie
d
hybr
i
d
H-
brid
ge mu
ltil
ev
el
i
n
verter usin
g
aux
ili
ar
y sw
itch. T
h
is pro
p
o
s
ed i
n
verter
pr
oduc
es five
lev
e
ls o
u
tput w
i
th
five
pow
er d
e
vices
and c
l
a
m
pin
g
dio
des
as a
ph
ase vo
ltag
e a
n
d
ni
ne
lev
e
ls
a
s
a li
ne
volta
g
e
.
T
he lev
e
ls of t
h
e
inverters
are
d
e
cid
ed
bas
ed
on th
e p
has
e v
o
ltag
e n
o
t o
n
t
he l
i
n
e
vo
ltag
e. In this
pa
per t
he
perfor
m
a
n
c
e
of
the prop
ose
d
i
n
verter are
me
asure
d
in ter
m
s of line volta
g
e
. How
e
ver, by
increas
e in th
e nu
mb
er of le
vels
the pro
pos
ed i
n
verter w
i
th re
duce
d
n
u
mber
of sw
it
ches pr
oduc
es low
sw
itchin
g loss
es
and
i
m
prov
es th
e
efficiency of th
e inverter. T
h
i
s
metho
d
ach
i
eves t
he vari
ation of T
o
tal H
a
rmonic D
i
stor
tion (T
HD) in the
inverter a
nd o
u
tput volta
ge i
s
observe
d for
various
mo
du
latio
n
in
dices.
Simulati
on is
perfor
m
e
d
usi
n
g
MATLAB-SIMULINK for line
to line
output v
o
ltage. Variabl
e Amplitude P
hase
Dispo
sition (VAPD) str
a
tegy
provi
des o
u
tpu
t
w
i
th relatively
low
distortio
n
for all
th
e strat
egi
es. It is als
o
see
n
that V
APOD is foun
d
to
perfor
m
better
for all strategi
e
s
since it provi
des
rel
a
tively h
i
gh
er fund
a
m
e
n
tal RMS outp
u
t voltage.
Ke
y
w
ords
: THD, PWM, CF
,
F
F
, Line voltage.
Copy
right
©
2016 In
stitu
t
e o
f
Ad
van
ced
En
g
i
n
eerin
g and
Scien
ce. All
rig
h
t
s reser
ve
d
.
1. Introduc
tion
Multilevel con
v
erters offer a numbe
r of adv
antag
es
whe
n
com
pared to the con
v
entional
two level
co
nverter
co
unt
erpa
rt. Ge
ra
rdo Ceglia
et
al [1] have
discu
s
sed
a
new multile
ve
l
inverter top
o
l
ogy. Caball
e
ro et al [2] prese
n
ted ne
w a symmetri
c
al hybrid m
u
l
t
ilevel voltage
inverter. Kho
u
ch
a et al [3] propo
sed a
compa
r
ison
of symmetrical and a
s
y
mmetrical three-
pha
se H-b
r
id
ge multilevel
inverter for DTC in
du
ction motor d
r
i
v
es. Ro
sha
n
k
uma
r
et al [4]
descri
bed
a f
i
ve-level inve
rter top
o
logy
with si
ngle
-
dc
sup
p
ly by ca
scadin
g
a
flying cap
a
ci
tor
inverter a
nd
an h-brid
ge.
Bayat and Babaei [5]
p
r
e
s
ente
d
a ne
w cascad
ed
multilevel inverter
with re
du
ced
numbe
r of switche
s
. Topol
ogy for mult
il
evel inverters to attain maximum num
ber of
levels from g
i
ven dc source
s
have
be
en di
scusse
d
by Gupta
a
nd
Jain [6].
Rahil
a
et al
[7]
introdu
ce
d a
ne
w 8
1
lev
e
l inverte
r
wi
th re
du
ced
n
u
mbe
r
of
switche
s
. Minim
i
zation
ap
plie
d
dire
ctly on t
he lin
e-to
-lin
e voltage
of
multileve
l in
verters p
r
op
o
s
ed
by You
s
efpoor et al
[8].
Chava
rría
et al [9] deal
s Energy
-Bala
n
ce
Co
ntrol
of PV Ca
sca
ded M
u
ltilevel. Kangarl
u
a
n
d
Babaei [10]
have bee
n prop
osed a
gene
rali
zed
ca
scade
d m
u
ltilevel inverter usi
ng se
ries
con
n
e
c
tion of submultilevel
inverters. Balamur
uga
n et al [11] propo
sed a ne
w m
odified H-bri
d
ge
multilevel inverter
usi
ng le
ss
numb
e
r
of swit
che
s
. Yo
ungh
oon
Cho
et al [12] dev
elope
d a
carri
e
r-
based n
eutra
l voltage mo
dulation
strategy for m
u
ltilevel ca
scad
e
d
inverte
r
s u
nder un
balan
ced
dc sou
r
ces.
Murali et al
[13] made a
desig
n and
analysi
s
of voltage sou
r
ce i
n
verte
r
for
rene
wa
ble e
nergy a
ppli
c
ations.
Jama
ludin et
al [
14] pro
p
o
s
ed
a multilevel
voltage sou
r
ce
inverter
with
optimize
d
u
s
age of bidi
re
ctional switch
e
s
. Gab
r
iel et
al [15] introd
uce
d
a five-le
v
el
multiple-pole
PWM AC
– AC
conve
r
ters wi
th
re
duced
comp
onent
s count
. Lim et al
[16]
sug
g
e
s
ted a
modula
r
-cell
inverter em
ploying r
edu
ced flying
capa
citors wit
h
hybrid p
h
a
s
e-
shifted. Ra
sil
o
et
al
[1
7] prop
osed a effect
on
multilevel invert
er
supp
l
y
o
n
c
o
r
e
l
o
s
s
e
s
i
n
magneti
c
m
a
terial
s a
nd
ele
c
tri
c
al m
a
chi
ne.
Re
d
d
y et
al [18]
devel
oped
a
embe
dded
control
for
a n -Level DC – DC – AC I
n
verter.
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ISSN: 25
02-4
752
IJEECS
Vol.
1, No. 2, February 201
6 : 273 – 281
274
2. Toplog
y
and Opera
t
io
n
In conventio
n
a
l multilevel inverters, the
pow
er
semi
condu
ctor
switche
s
a
r
e com
b
ined to
prod
uce a
hi
gh fre
que
ncy
wavefo
rm i
n
po
sitive
and
neg
ative pol
arities.
The
chosen five le
vel
modified cascad
ed Hyb
r
id
H-b
r
idg
e
mul
t
ilevel invert
er with le
ss n
u
m
ber of
switches i
s
sh
own
in
Figure 1. O
n
e switchi
ng
e
l
ement a
nd f
our
diod
es
a
dded i
n
the
convention
a
l full-b
r
idge
inv
e
rter
are
connected to the
cent
er-tap
of
dc power supply
.
Proper swit
ching control
of the auxiliary
swit
ch can g
enerate half level of dc su
pply vo
ltage. Table I sho
w
s the
swit
ching state
s
a
nd
possibl
e outp
u
t voltages of
the converte
r.
3. The Proposed Multilevel In
v
e
rter
This top
o
log
y
requires l
e
ss num
ber of
comp
on
ents
comp
ared to co
nventiona
l
topologi
es. It is al
so
mo
re efficient
which l
ead
s to
simpl
e
r
and
more reliabl
e control
of
the
inverter. T
o
p
r
ovide
a large
numb
e
r of
o
u
tput leve
ls
without increa
sing the n
u
mb
er of b
r
idg
e
s,
a
new mo
dified
casca
ded h
y
brid H-bri
d
g
e
symmetri
c
a
l
multilevel converte
r is p
r
opo
se
d in this
pape
r. Tabl
e
1 sh
ows th
e
possibl
e swit
chin
g state
s
of the propo
sed inve
rter. T
able 2
displa
ys
the comp
ari
s
on between
convention
a
l
a
nd pro
p
o
s
ed
multilevel inverter.
R LOA
D
D
3
D
4
S
1
S
3
S
4
S
2
V
dc
V
dc
D
1
S
a
R LOA
D
D
3
D
4
D
2
S
1
S
3
S
4
S
2
V
dc
V
dc
D
1
S
a
R LOA
D
D
3
D
4
D
2
S
1
S
3
S
4
S
2
V
dc
V
dc
D
1
S
a
D
2
Figure 1. Sch
e
matic of cho
s
en three ph
a
s
e,
five level modified cascaded hyb
r
id
H-b
r
id
ge
inverter
Table 1. Voltage ou
put an
d swit
chin
g st
ates
Vphase a
S
a
S
1
S
2
S
3
S
4
2V
dc
0 1
1 0 0
V
dc
1 0
0 0 0
0
0 0
0 0 1
-V
dc
1 0
1 0 0
-2V
dc
0 0
0 1 1
Table 2. Co
m
pari
s
on b
e
tween existin
g
system and p
r
opo
sed
syste
m
Ty
p
e
Conventional
CMLI
Chosen h
y
brid H
-
bridge cascaded
inver
t
er
No. of s
w
itches
24
15
No. of clamping diodes
24
15
No. of DC sour
ces
6
6
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IJEECS
ISSN:
2502-4
752
Modeling and Sim
u
lation of MPPT-SEPIC Com
b
ined
Bidirectional
Control Inverse…
(Soedi
byo)
275
4. Modulatio
n Schemes
The adve
n
t of the multile
vel inverter t
opol
o
g
y has
brou
ght forth
variou
s Pulse Width
Modulatio
n
(PWM) sch
e
m
e
s
as a
me
an
s to
control
th
e switching
of
the
active
de
vices in
ea
ch
o
f
the multiple voltage level
s
in the inverter. More
n
u
m
ber of mo
d
u
lation strate
gies p
o
ssibl
e
fo
r
multilevel inv
e
rters. T
he
most
efficient
metho
d
i
s
pulse width modulatio
n schem
es
u
s
e
d
to
control the
switchi
ng of th
e active
devices in
ea
ch
of the multiple v
o
ltage level
s
i
n
the inve
rter.
In
this m
e
thod,
a fixed
D.C. i
nput voltag
e
is
sup
p
lied
to
the i
n
verte
r
and
a
cont
rol
l
ed A.C.
outp
u
t
voltage is ob
tained by adj
usting the o
n
and–off peri
ods of the in
verter devi
c
e
s
. Voltage-ty
pe
PWM inve
rte
r
s
have b
een
applie
d wi
de
ly to su
ch
field
s
as
p
o
w
e
r
s
u
pp
lies
a
nd mo
to
r
d
r
ivers
.
This i
s
be
ca
use
su
ch inv
e
rters a
r
e we
ll adapted
to
high-sp
eed
self turn-off switchi
ng devi
c
e
s
that, as solid
-state
po
we
r
conve
r
ters, a
r
e
prov
id
ed with re
cently develop
ed ad
vance
d
circui
ts.
The SPWM
a
i
ms at g
ene
ra
ting a si
nu
soi
dal invert
e
r
o
u
tput voltage
without
lo
w-o
r
de
r ha
rmo
n
i
cs.
This is po
ssi
b
l
e if the
sa
mp
ling fre
que
ncy is hi
gh
com
pare
d
to th
e f
undam
ental
o
u
tput fre
quen
cy
of the invert
er. In this p
aper m
u
ltica
rrie
r
mod
u
lat
i
on tech
niqu
es
with sin
e
referen
c
e a
r
e
pre
s
ente
d
. Numbe
r
of tri
a
ngula
r
wave
is
com
pare
d
with
a
con
t
rolled
sin
u
so
idal mo
dulati
n
g
sign
al. Th
e n
u
mbe
r
of
carriers requi
red
t
o
p
r
od
uce
the
m level
o
u
tp
ut is m-1. Mul
t
iple de
grees
of
freedo
m are
available in carri
er ba
se
d multilevel
PWM. The prin
ci
ple of the carrier b
a
sed PWM
strategy is to use m-1 ca
rri
ers
with a ref
e
ren
c
e
sign
al
for a m level inverter. Thi
s
pape
r focu
ses
on s
i
x SP
WM s
t
rat
egies
. They are: P
D
PWM, VAP
DPWM, PODPWM, VAPODPWM, VFP
W
M
and VAVFPWM.
.
4.1. Phase Disposition (P
D)
In this metho
d
use
s
fou
r
carri
ers, all the
s
e carrie
rs h
a
v
e the same
amplitude, fre
quen
cy,
and p
h
a
s
e.
Since all
ca
rriers a
r
e
sel
e
cted
with t
he same
ph
ase. All
carriers are havi
n
g
amplitude
as 1. The PD
PWM si
gnal
gene
ration fo
r mod
u
lation
index m
a
=
0.8 is
sho
w
n
in
Figure 2.
Figure 2. Modulating a
nd
carrie
r
wavef
o
rm
s for PDP
W
M strategy (m
a
= 0.8 an
d
m
f
= 40)
4.2. Variable Amplitude P
h
ase Dis
pos
ition (VAPD)
Figure 3. Modulating a
nd
carrie
r
wavef
o
rm
s for PDP
W
M strategy (m
a
= 0.8 an
d
m
f
= 40)
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 25
02-4
752
IJEECS
Vol.
1, No. 2, February 201
6 : 273 – 281
276
This metho
d
i
s
sam
e
a
s
P
D
PWM
but
a
m
plitude
arra
ngeme
n
t is
somewhat diff
erent. T
he
s
i
nus
o
idal ref
e
renc
e
wave
is
placed at the mi
ddle of the four c
a
rriers
.
The VAPD PWM s
i
gnal
gene
ration fo
r modul
ation i
ndex m
a
= 0.8
is sho
w
n in F
i
gure 3.
4.3. Phase O
pposition
Disposition
(POD)
This meth
od
is sam
e
as P
D
PWM b
u
t carri
er a
rra
ng
ement sh
oul
d be different
. In this
method u
s
e
s
two group
s
of carrie
rs th
at is po
si
tive grou
p an
d ne
gative gro
up
carrie
rs. In th
is
type the two
grou
ps
are o
ppo
site in p
h
a
se
with e
a
ch
other. It ca
n
gene
rate five
level output.
The
PODPWM si
gnal ge
neration for m
a
= 0.
8 is sh
own in Figure 4.
Figure 4. Modulating a
nd
carrie
r wavef
o
rm
s for PODPWM strateg
y
(m
a
= 0.8 an
d m
f
= 40)
4.4. Variable Amplitude P
O
D (V
APOD)
The VAPODPWM si
gnal
generation for m
a
=
0.8 is
sho
w
n i
n
Fig
u
re 5. In thi
s
method al
l
carrie
rs
pha
se shifted by
180 de
gree.
All thes
e
carriers have th
e, freque
ncy,
and ph
ase
but
different ampl
itude.
Figure 5. Modulating a
nd
carrier wavef
o
rm
s for VAPODP
WM strategy (m
a
= 0.8
and m
f
= 40
)
4.5. Variable Freque
nc
y
(
V
F)
This
metho
d
i
s
o
ne of th
e
PWM te
chni
q
ues
and it is
same as PDPWM but intermittent
carrie
r
h
a
vin
g
differe
nt
freque
ncy co
mpare
to up
per and
lo
wer ca
rrie
r
.
T
he
VFP
W
M sign
al
gene
ration fo
r m
a
= 0.8 is shown in Figu
re 6.
Evaluation Warning : The document was created with Spire.PDF for Python.
IJEECS
ISSN:
2502-4
752
Modeling and Sim
u
lation of MPPT-SEPIC Com
b
ined
Bidirectional
Control Inverse…
(Soedi
byo)
277
Figure 6. Modulating a
nd
carrie
r wavef
o
rm
s for VFPWM strategy
(m
a
= 0.8 and
m
f
= 40 for lo
wer a
nd up
pe
r switche
s
an
d m
a
= 0.8 an
d m
f
=
80 for intermediate
swit
che
s
)
4.6. Variable Amplitude V
F
(VAVF)
In this metho
d
simila
r to VF but carrie
r
am
plitude of
carrie
r is diff
erent. It can
gene
rate
five level out
put. Since
all
ca
rrie
r
s a
r
e
sele
cted
with
the same
ph
ase, th
e met
hod i
s
kno
w
n
as
VAVF strategy. The VAVF
PWM signal
generation for m
a
= 0.8 is shown in Figu
re 7.
Figure 7. Modulating and
carrier
wavef
o
rm
s for VAVFPWM strategy (m
a
= 0.8 a
nd m
f
= 40
)
5. Simulation Resul
t
s
The
ch
osen fi
ve level inve
rter i
s
m
odel
e
d
in
MATLAB
-SIMULI
N
K t
o
verify the
p
r
opo
se
d
PWM strate
gi
es
fo
r ch
ose
n
three
p
h
a
s
e Hyb
r
id
H- bri
dge
type
ca
scade
five
level invert
er for
var
i
ous
values
of m
a
rangi
ng from
0.6
– 1 an
d corresp
ondi
ng %
T
HD value
s
l
i
ne voltage
a
r
e
measured u
s
ing FFT
blo
c
k an
d they
are
sho
w
n
in Tabl
e 3.
Table
4
sho
w
s the V
RM
S
of
fundame
n
tal of inverter ou
tput for the same m
odul
ation indices.
Table 5, 6 a
nd 7 sho
w
fo
rm
factor, cre
s
t factor and
di
stortion
f
a
cto
r
s.
Fig
u
re
8-19 sho
w
the
simulate
d o
u
tput voltage
of
cho
s
e
n
hyb
r
i
d
H-b
r
idg
e
ca
scade
d i
n
verter an
d the
correspon
ding
FFT
plots wit
h
differe
nt P
W
M
strategi
es
but
only for on
e
sampl
e
valu
e of m
a
=0.8 and
m
f
=40. F
i
gure
8 sho
w
s the five level
output voltage gene
rated
by PDPWM strategy an
d
its FFT plot is sho
w
n in
Figure 9. From
Figure 9, it is ob
serve
d
that the PDPWM strategy
produ
ce
s si
gnifica
nt 30
th
, 32
nd
and 38
th
harm
oni
c energy. Figure 10 sh
ows t
he five level output
voltage generated by VAPDPWM
strategy a
n
d
its FFT plot
is s
hown in
Figure 11.
From Fi
gure
11,
it is ob
serve
d
that the
VAPDPWM strategy produc
es
s
i
gnific
ant 5
th,
7
th
and 38
th
harmo
nic
energy. Figure 12 sh
ows the
five level output voltage g
enerated by
PODPWM st
rategy and its
FFT plot is sh
own in Fi
gure
1
3
From Fi
gure
13, it is ob
se
rved that the
PODPWM
strategy produ
ce
s sig
n
ifica
n
t
33
rd
, 35
th
and
39
th
harmonic energy. Figure 14 shows
t
he five
level
output voltage generated
by VAPODPWM
strategy a
nd i
t
s FFT plot i
s
sho
w
n in
Fig
u
re 1
5
.
Fro
m
Figure 15, it is ob
se
rved th
at the strate
g
y
prod
uces sig
n
ificant 5
th
, 27
th
, 29
th
an
d
39
th
ha
rmo
n
ic ene
rgy. Fi
g.16
sho
w
s the
five level
out
put
voltage ge
nerated by VFP
W
M
strategy
and its
FFT p
l
ot is sho
w
n i
n
Figu
re 1
7
.
From Fi
gu
re
17,
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ISSN: 25
02-4
752
IJEECS
Vol.
1, No. 2, February 201
6 : 273 – 281
278
it is ob
se
rve
d
that the V
F
PWM
strate
gy pro
d
u
c
e
s
signifi
cant 5
th
, 33
rd
, 35
th
a
nd 3
9
th
ha
rm
onic
energy. Figure 18 shows the five
level output voltage generated
by VAVFPWM strategy and its
FFT plot i
s
shown in Fi
gure 19. From
Figure
19, it
is observed t
hat
the VAVFPWM
strategy
prod
uces sig
n
ificant
5
th
, 36
th
and 38
th
h
a
rmo
n
ic e
nergy. The following p
a
ra
met
e
r value
s
are
use
d
for s
i
mulation: V
dc
= 200V, f
c
= 2000
Hz, f
m
= 50Hz an
d
R (load
) = 1
0
0
ohms.
5.1.Simulation of PDP
W
M Technique
Figure 8. Simulated outp
u
t voltage gen
erated
by PDPWM tech
niqu
e for R-lo
ad
Figure 9. FFT
spe
c
trum fo
r PDPWM te
ch
nique
5.2. Simulation of VAPDPWM Tech
nique
Figure10.
Simulated outp
u
t voltage ge
nerate
d
by VAPDPWM tec
hnique for R-load
Figure 11. FFT s
p
ec
trum for VAPDPWM
techni
que
5.3. Simulation of PODP
WM Tec
hniq
u
e
Figure 12. Simulated outp
u
t voltage ge
nerate
d
by PODPWM
techniq
ue for R- load
Figure 13. FF
T spe
c
tru
m
for PODP
WM
techni
que
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IJEECS
ISSN:
2502-4
752
Modeling and Sim
u
lation of MPPT-SEPIC Com
b
ined
Bidirectional
Control Inverse…
(Soedi
byo)
279
5.4. Simulation of VAPO
DPWM T
ech
nique
Figure 14. Simulated outp
u
t voltage ge
nerate
d
by VAPODPWM technique for R- load
Figure 15. FFT s
p
ec
trum for VAPODPWM
techni
que
5.5. Simulation of VFPWM Technique
Figure16. Simulated outp
u
t voltage ge
nerate
d
by VFPWM tech
niqu
e for R-lo
ad
Figure 17. FF
T spe
c
tru
m
for VFPWM
techni
que
5.6. Simulation of VAVFP
W
M Tec
hniq
u
e
Figure 18. Simulated outp
u
t voltage ge
nerate
d
by VAVFPWM tec
hnique for R-load
Figure 19.
FFT s
p
ec
trum for VAVFPWM
techni
que
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 25
02-4
752
IJEECS
Vol.
1, No. 2, February 201
6 : 273 – 281
280
Table 3. % THD of outp
u
t voltage of ch
ose
n
hybrid
H-b
r
id
ge MLI for variou
s va
lues of
modulatin
g in
dice
s
m
a
PD
V
A
PD
PO
D
V
A
P
O
D VF V
A
V
F
1
17.74
17.76
24.10
21.57
21.41
20.98
0.9
17.76
18.05
34.59
26.67
24.29
21.21
0.8
23.53
17.36
39.50
31.25
29.97
21.64
0.7
25.27
19.44
43.12
35.11
33.38
24.67
0.6
28.70
25.79
41.19
35.36
35.91
31.20
Table 4. V
RM
S
(Fun
dame
n
ta
l) of output voltage of cho
s
en hybrid
H-b
r
idge M
L
I for variou
s value
s
of modulating
indice
s
m
a
PD
V
A
PD
PO
D
V
A
P
O
D VF V
A
V
F
1
241.7
262.5
242.1
263.5
241.8
249.5
0.9
216.8
246.4
218.7
246.6
216.7
246.4
0.8
192.9
229.8
194.2
230.1
192.9
229.7
0.7 168.2
212.5
169
212.9
168.1
212.7
0.6
143.7
196.1
143.2
195.3
143.9
196.1
Table 5. Fo
rm Facto
r
of output voltage of cho
s
en hy
brid H-b
r
idg
e
MLI for variou
s value
s
of
modulatin
g in
dice
s
m
a
PD V
A
PD
PO
D
V
A
P
O
D
VF
V
A
V
F
1 5935
6447.5
25570
27450
3390.0
1355.7
0.9
413.46
2681.1
5920
26260
741.37
2674.4
0.8 881.81
1134.0
INF
2285.4
1211.8
INF
0.7 1430.0
3558.3
INF
725.45
4295.0
10705
0.6 433.23
104.85
1189.2
1245
369.5
2225.5
Table 6. Cre
s
t Factor of ou
tput voltage of c
hosen hybrid H-b
r
id
ge M
L
I for variou
s values of
modulatin
g in
dice
s
m
a
PD V
A
PD
PO
D
V
A
P
O
D
VF
V
A
V
F
1
1.4145
1.4140
1.4142
1.4144
1.4143
1.4140
0.9 1.4142
1.4143
1.4138
1.4140
1.4143
1.4143
0.8
1.4136
1.413
1.4145
1.4146
1.4142
1.4144
0.7 1.4143
1.4145
1.4142
1.4142
1.4140
1.4141
0.6 1.4140
1.4145
1.4141
1.4142
1.4141
1.4140
Table 7. Dist
ortion Fa
ctor
of output voltage of ch
ose
n
hybrid H-b
r
i
dge MLI for variou
s value
s
of
modulatin
g in
dice
s
m
a
PD V
A
PD
PO
D
V
A
P
O
D
VF
V
A
V
F
1
0.084
0.2362
0.1144
0.2538
0.0448
0.2453
0.9 0.0468
0.2399
0.1415
0.2346
0.0302
0.2487
0.8 0.0937
0.2674
0.2311
0.2437
0.1158
0.2384
0.7 0.0674
0.2224
0.1878
0.2374
0.0717
0.2252
0.6 0.1557
0.1687
0.1266
0.1656
0.1501
0.1747
6. Conclusio
n
The p
r
op
ose
d
modified
h
y
brid H-b
r
idg
e
multilevel i
n
verter
ha
s been
simul
a
ted u
s
ing
MATLAB. The five level inverter
can
o
perate
as a
nine level inv
e
rter in th
ree
phase sy
ste
m
s
interm
s of line to line voltage. So compa
r
ed to t
he pha
se vo
ltage the lin
e to line voltage
perfo
rman
ce
are bette
r. The impo
rtant
cha
r
a
c
te
ri
stic of the pro
posed sy
ste
m
is able to
be
Evaluation Warning : The document was created with Spire.PDF for Python.
IJEECS
ISSN:
2502-4
752
Modeling and Sim
u
lation of MPPT-SEPIC Com
b
ined
Bidirectional
Control Inverse…
(Soedi
byo)
281
extended to a
n
y numbe
r of output voltage levels with
l
e
ss numb
e
r o
f
switch
es. T
h
is sy
stem ca
n
overcome
so
me of the limitat
ions of
the conve
n
tional MLI
S.
T
h
is metho
d
result
s harmo
nics
decrea
s
e
s
a
s
the numbe
r of levels increase, less
nu
mber of switches a
nd
cost
of the conve
r
ter.
Perform
a
n
c
e
indices like %THD, V
RM
S
(i
ndicating the amount of DC bu
s utilizati
on), CF, FF a
nd
DF relate
d
to
po
we
r
q
ualit
y
issue
s
hav
e been evalu
a
ted, pre
s
ent
ed and analy
z
ed.
Based o
n
pre
s
ente
d
switching
algo
rithm, the ch
osen multile
vel inverter gen
e
r
ates nea
r si
nusoidal
o
u
tp
ut
voltage and
as
a result, has
relatively l
o
w
har
m
oni
c content for the VAPDP
W
M strategy. It is
also
seen that VAPODPWM techni
que is found to perform better
for all strategies si
nce it
provide
s
rela
tively
higher fundame
n
tal RMS
out
p
u
t
voltage. Tabl
e 3 a
nd 4
shows the
total
harm
oni
c di
stortion a
nd
RMS for all ch
ose
n
mod
u
lat
i
ng indi
ce
s. T
able 5
displa
ys form fa
ctor for
all mod
u
latin
g
indi
ce
s. Ta
ble 6
and
7 d
i
splay the
cre
s
t facto
r
an
d
distortio
n
fa
ctor for all
cho
s
en
modulatin
g in
dice
s.
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