TELKOM
NIKA Indonesia
n
Journal of
Electrical En
gineering
Vol.12, No.5, May 2014, pp
. 3849 ~ 38
6
2
DOI: http://dx.doi.org/10.11591/telkomni
ka.v12i5.5207
3849
Re
cei
v
ed
No
vem
ber 2
5
, 2013; Re
vi
sed
Jan
uar
y 3, 20
14; Accepted
Jan
uary 15, 2
014
Advances on CMOS Shift Registers for Digital Data
Storage
Mohammad
Arif Sobha
n Bhuiy
a
n*, Hasrul Ni
sh
a
m
Bin Rosly
,
Mamun bin Ibne Re
az,
Khairun
Nis
a
Minhad, Hafiza
h Hu
sai
n
Dep
a
rtment of Electrical, El
ec
tronic an
d S
y
st
em
s Engi
ne
eri
ng, Univ
ersiti K
eba
ngs
aan Ma
la
ysia,
436
00, Ban
g
i, Sela
ngor, Mal
a
ysi
a
*Corres
p
o
ndi
n
g
author, e-ma
i
l
: md.arif.sobh
an@
gmai
l.com
A
b
st
r
a
ct
The shift register is the heart of
the current d
i
gital d
a
ta stora
ge system. Cur
r
ent trends of w
i
reles
s
devic
e d
e
si
gns
are
to
bal
anc
e the
p
o
w
e
r c
onsu
m
ption,
c
o
st
an
d porta
b
ility of
th
e
dev
i
c
e. The w
o
rl
d
w
ide
researc
h
is givi
ng e
m
p
hasi
z
e
on incre
a
si
ng the a
m
o
unt
of me
mory at min
i
mu
m possi
ble
space to red
u
c
e
the overa
ll si
z
e
of the devices
now
a days. This pa
per rep
o
r
ts a detaile
d
survey on d
i
fferent types of shif
t
registers i
n
C
M
OS technol
o
g
y from the
p
e
rformanc
e,
desig
n an
d ap
plicati
on
poi
nt of view
. It also
discuss
es the
techno
lo
gies
a
v
aila
bl
e for the
desi
gn
of
shift registers w
i
th
their
merits
an
d de
merits. T
h
i
s
survey w
ill act as a referenc
e
for the scientist
s
to design th
e hig
h
-perfor
m
an
ce me
mory mo
dul
e.
Ke
y
w
ords
: shi
ft registers, digi
tal storage, dy
na
mic CMOS, static CMOS
Copy
right
©
2014 In
stitu
t
e o
f
Ad
van
ced
En
g
i
n
eerin
g and
Scien
ce. All
rig
h
t
s reser
ve
d
.
1. Introduc
tion
A shift regi
ste
r
is a di
gital d
a
ta storage.
The data
can
be the letters to be displ
a
yed on a
TV scre
en, n
u
mbe
r
s i
n
a
comp
uter
or
cal
c
ulato
r
, in
terme
d
iate val
ues i
n
a di
gital filter or
part of
an elabo
rate
cod
e
or sequ
ence. Shift registe
r
s a
r
e
made up of i
ndividual sta
ges. Each st
age
can
sto
r
e
on
e
bit of i
n
form
a
t
ion, call
ed
a
binary
1
or a
0, and
u
s
uall
y
co
rre
sp
ondi
ng to
a "ye
s
"
or
"no" or else perh
a
p
s
a "present" or "a
bse
n
t"
comm
and. Fou
r
bits togethe
r can rep
r
e
s
ent
a
decim
al n
u
m
ber,
while
six
bits tog
e
the
r
ca
n ha
ndle
one AS
CII ch
ara
c
ter,
and
so
on. In a
shift
regi
ster, the contents
can b
e
mov
ed or
shifted so that
the contai
ned
information i
s
march
ed on
e
and only on
e stage at a tim
e
throu
gh the
device.
The
shifting p
r
o
c
e
ss i
s
called
cl
ocking a
nd o
ne
or more clo
cks ca
n be invol
v
ed in compl
e
ting the shift
i
ng ope
ration.
Duri
ng the e
a
rly days, sh
ift registers
with
many st
age
s we
re u
s
ed fo
r mem
o
rie
s
of
comp
uter an
d othe
r
ele
c
troni
cs g
a
zettes [1
-3].
Us
a
ges
of shift registe
r
s sub
s
tituted
mercu
r
y
delay line
s
, speedi
ng up d
a
ta pro
c
e
s
sin
g
and allo
win
g
for sm
aller comp
uter
co
mpone
nts a
n
d
perip
he
rals [4]. Today, shift regi
sters are
co
nsi
d
e
r
ed
antiquat
ed a
s
p
r
ima
r
y memo
rie
s
for
computers and ot
her electronic
devices. Circui
t boards, however,
still feature
shift regi
sters to
redu
ce
the a
m
ount of
wiri
ng ne
ede
d, e
s
pe
cially in
di
splay d
r
ivers,
digital to a
n
a
log
conve
r
te
rs,
and serial d
a
ta memory [5].
As a
pplied
to
digital
ci
rcuits, a
shift
regi
ster
is a
se
rie
s
of
flip-flop
s
based
on
se
q
uential
clo
ck timin
g
. The flip-flop
s
facilitate mo
ving data
fro
m
input to ou
tput using
se
quential lo
gic. A
clo
ck, i
n
the
form of
a
rep
eating
wave
i
n
a
sq
ua
re
p
a
ttern, i
s
u
s
e
d
to
synchro
n
ize
ho
w
dat
a
travels th
rou
gh shift regi
sters,
cre
a
ting
a short
dela
y
in the tra
n
smissi
on
of a
digital si
gnal
[6].
Most often,
shift regi
sters
of va
rying l
e
ngths are u
s
ed to
conve
r
t
parallel d
a
ta
to se
rial [
7
], but
may also b
e
use
d
for data
flow in micro
p
ro
ce
ssors o
r
to covert a
n
alog data to
digital and vi
ce
vers
a [8, 9].
Shift regi
sters a
r
e
high
-sp
eed
circuit
s
[
7
]. Pr
imarily,
a shift regi
st
er m
o
ves bit
s
of
data
either l
e
ft or
right alon
g a
circuit, d
epe
nd
ing on
st
ructu
r
e a
nd d
e
si
gn
of the
circuit. In its
simple
st
form, a shift registe
r
takes
data in at the
first st
ag
e a
nd shifts
bits
one sta
ge left
or rig
h
t as th
e
clo
ck sig
nal
s
are nee
ded
for
a data advan
ce.
Re
gisters are
i
dentifi
ed by
the num
ber
of
temporary st
orag
e slot
s a
v
ailable after each
stag
e betwe
en inp
u
t
and output
[10]. Temporary
stora
ge sl
ots allow a shift
registe
r
to d
e
lay
data sig
nals u
n
til the clock si
gnal
s app
rove da
ta
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 23
02-4
046
TELKOM
NI
KA
Vol. 12, No. 5, May 2014: 3849 – 38
62
3850
advan
ce. An 8-bit re
giste
r
,
for example,
has ei
ght
sta
ges a
nd thu
s
eight tempo
r
a
r
y stora
ge
slo
t
s
for bits
in a data s
t
ring.
Shift Registe
r
s a
r
e u
s
u
a
lly used for
d
a
ta
storage
or data m
o
vement in cal
c
ulato
r
s,
comp
uters
a
nd oth
e
r ele
c
troni
c devi
c
es
su
ch
a
s
t
w
o
bina
ry n
u
m
bers
befo
r
e
they a
r
e
ad
ded
together or to convert th
e
data from
ei
ther a
serial
to parallel o
r
parallel to
serial fo
rmat [
11].
Serial data
over shorte
r di
st
ances
of ten
s
of centimete
r
s, uses
sh
ift registe
r
s to
ge
t data into an
d
out of mi
cro
p
r
ocesso
rs. Numerou
s
pe
ri
pherals, i
n
cl
u
d
ing a
nalo
g
to digital
co
nverters, digital
to
analo
g
conve
r
ters, di
splay
drive
r
s,
an
d
memo
ry
(d
ig
ital sto
r
ag
e),
use
shift re
gi
sters to
redu
ce
the amount
of wiring i
n
circuit boa
rd
s. Some s
p
e
c
iali
zed
cou
n
t
er circuit
s
a
c
tually use shift
regi
sters to gene
rate rep
eating waveform
s. Long
er
shift regi
sters, with the h
e
lp of feedb
ack
gene
rate
pattern
s
so l
ong
that they loo
k
li
ke
ran
d
o
m
noi
se, p
s
e
udo-noi
se. T
he in
dividual
dat
a
latche
s th
at make
up
a
si
ngle
shift regi
ster
ar
e all
dri
v
en by a
co
m
m
on
clo
c
k (Cl
k
)
sig
nal m
a
king
them syn
c
h
r
onou
s d
e
vices. Shift re
gi
ster I
C
'
s
a
r
e
gene
rally p
r
ovided
with
a cle
a
r or re
set
connection so that they can be
"SET" or "RESET" as requi
red.
Instead
of usi
ng mem
o
ry el
ements in a
seque
nt
ial
sy
stem,
dynami
c
logic circuit
s
can be
use
d
to store
tempora
r
y data in differe
nt devices
[1
2-16]. In a dynamic
shift re
gister, sto
r
a
g
e
is
accompli
sh
ed
by co
ntinuall
y
shifting the
bits fr
om o
n
e
sta
ge to th
e next an
d re-ci
r
culatin
g
th
e
output of the last stage i
n
to the first stage [
17]. T
he data conti
nually circul
a
t
es thro
ugh t
he
regi
ster
unde
r the control of clo
ck. To
o
b
tain out
put,
a se
rial o
u
tpu
t
terminal mu
st be a
c
ce
ssed
at a specific clock pul
se; otherwi
se, the sequence of
bits will not
correspond to the data stored.
This p
ape
r p
r
esents
a de
tailed discu
s
sion o
n
shift regi
sters for different ap
plicatio
ns
from their
archite
c
ture
an
d perfo
rma
n
ce point of
view. The
ba
si
cs
of shift re
gisters a
nd t
heir
operation
s
are also di
scu
s
sed. The te
chn
o
logie
s
a
v
ailable for shift registers
along with th
eir
merits an
d d
e
merit
s
a
r
e
a
l
so i
n
cl
uded
i
n
this re
vie
w
.
This review
will h
e
lp the
sci
entist
s
to
have
basi
c
a
s
well
as adva
n
ced
kno
w
le
dge o
n
shift regi
ste
r
s for thei
r future research
es.
2. Shift Regi
ster
s and Cl
assifica
tions
Each flip-flop
is a binary ce
ll capabl
e of storin
g one bi
t of information [18]. A Reg
i
ster is
simply a grou
p of flip-flops.
An n-bit regi
ster ha
s a g
r
oup of n flip-flops. The b
a
sic functio
n
of a
regi
ster is to
hold
info
rm
ation
within
a digital
sy
st
em
so
as to
ma
ke it
ava
ilable to
the
logic
element
s du
ri
ng the co
mpu
t
ing pro
c
e
s
s. Since a regi
ster con
s
ist a finite numbe
r
of flip-flops a
n
d
as ea
ch of
th
ose
flip-flop
s
is cap
able
to
store
a
si
ngl
e 0
or
1, the
r
e are a
finite
numb
e
r of 0
-
1
combi
nation
s
that can b
e
stored into
a registe
r
. Ea
ch of
those com
b
ination
s
is
known as
stat
e or
conte
n
t of th
at regi
ste
r
[1
9]. With flip-fl
ops we
can
store d
a
ta bit
w
ise b
u
t u
s
u
a
lly data d
o
e
s
n
o
t
appe
ar
as si
n
g
le bit
s
. Inste
ad it i
s
comm
on to
sto
r
e d
a
ta
word
s of n
bit with
typi
cal wo
rd
l
eng
ths
of 4, 8, 16, 32 or even 6
4
bits. Thu
s
, se
veral flip
-flop
s
are com
b
in
ed to form a
regi
ster to st
ore
whol
e data words. Regi
sters a
r
e syn
c
hrono
us
circ
uits thu
s
all
flip-flops are controlled
by a
comm
on cl
ock line [18].
The Shift Re
gister is one
type of sequ
e
n
tial logi
c
circuit that is
use
d
to sto
r
e
or t
r
an
sfer
data in th
e fo
rm of bi
nary
numbe
rs an
d
then "shi
fts"
the data
out
once eve
r
y cl
ock cy
cle [2
0
].
It
basi
c
ally co
n
s
ist
s
of seve
ral sin
g
le bit
"D-T
ype Da
ta Latche
s
", one for ea
ch bit (0 or 1)
con
n
e
c
ted to
gether in
a se
rial o
r
d
a
isy
-
chain a
r
rang
e
m
ent so that t
he out
put fro
m
one
data l
a
tch
become
s
the input of the next latch and so on. The d
a
ta bits may be fed in or o
u
t of the register
seri
ally, i.e. one after the
other fro
m
ei
ther the left
or the ri
ght d
i
rectio
n, or
in
parall
e
l, i.e. all
together. Th
e
numbe
r of in
dividual data
latche
s requi
red to make u
p
a singl
e Sh
ift Registe
r
is
determi
ned b
y
the number
of bits to be stored.
Gene
rally, shi
ft registers op
erate in on
e o
f
the four different mod
e
s [2
0], they are:
1.
Serial-i
n to
P
a
rallel
-
out
(SI
P
O)
- T
he
re
gist
er i
s
lo
ad
ed
with
se
rial
data,
one
bit
at a
time, with the stored
data b
e
ing availabl
e
in parallel fo
rm.
2.
Serial-i
n to S
e
rial
-out (SIS
O) -
The
dat
a
is
shifted
serially "IN" a
nd "OUT" of
th
e
regi
ster, on
e bit at a time in either a le
ft or rig
h
t dire
ction und
er cl
ock co
ntrol.
3.
Parallel
-
in to
Serial
-out
(PISO) - T
h
e
parallel d
a
ta is l
oad
ed
into the
re
gister
simultan
eou
sl
y and is shifte
d out of the registe
r
se
riall
y
one bit at a
time unde
r cl
ock co
ntrol.
4.
Parallel
-
in to Parallel
-
out (PIPO) - The
parall
e
l data is loade
d sim
u
ltaneo
usly in
to the
regi
ster, an
d tran
sferred to
gether to thei
r re
spe
c
t
i
v
e
o
u
t
put
s by
t
he same
clo
ck p
u
lse.
The data mo
vement from
left
to right through a shift registe
r
in different mode
s is
graphically illustrated in Fi
gure 1.
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
2302-4
046
Advan
c
e
s
on
CMOS Shift Regi
sters for
Digita
l Data Storage
(Moh
a
m
m
ad Arif Sobhan Bhui
ya
n
)
3851
Figure 1. Shift Registe
r
in Different Mo
d
e
s
2.1. Serial-in to Parallel-out (SIPO)
Figure 2
sho
w
s
a 4-bit Se
rial-i
n to Parallel-o
u
t Shift Regi
ster. A
s
sume t
hat all
the flip-
flops (FFA to FFD) have ju
st been
RES
E
T (CLEA
R
input) a
nd tha
t
all the outpu
ts QA to QD
are
at logic level
"0" i.e., no parallel d
a
ta out
put. If a logic "1" is co
nne
ct
ed to the DA
TA input pin
of
FFA then on
the first cl
ock pulse the ou
tput of
FFA a
nd therefore
the re
sulting
QA will be
set
HIGH to logi
c "1" with all the other out
puts still
remai
n
i
ng LOW at logic "0
". Assume now that the
DATA input p
i
n of FFA has return
ed LO
W agai
n to
logic "0" giving
us on
e data p
u
lse o
r
0-1-0.
Figure 2. 4-bi
t Serial-in to Parallel
-
out S
h
ift Registe
r
The se
co
nd clock pulse wil
l
chang
e the output
of FFA to logic "0" and the output
of FF
B
and QB HIG
H
to logic "1" as its input D has the
log
i
c "1" level on it from QA.
The logi
c "1" has
now
moved
o
r
be
en "shifted" one
pla
c
e
along th
e reg
i
ster to th
e ri
ght as it is n
o
w at QA.
Wh
en
the third
clo
c
k pul
se a
rrive
s this l
ogic "
1
" val
ue move
s to the outp
u
t
of FFC (Q
C) and
so on
u
n
til
the arrival of
the fifth clo
ck pul
se
whi
c
h
sets all
the
o
u
tputs
QA to
QD
ba
ck aga
in to logi
c l
e
vel
"0" beca
u
se the input to F
F
A has remai
ned con
s
tant at logic level "0".
Table 1. Basi
c Moveme
nt of Data throu
gh a Shift Register
Cl
oc
k
P
u
l
s
e No
QA
QB
QC
QD
0
0
0 0 0
1
1
0 0 0
2
0
1 0 0
3
0
0 1 0
4
0
0 0 1
5
0
0 0 0
The effect of each clo
c
k p
u
lse i
s
to shif
t
the data co
ntents of ea
ch stage o
ne
place to
the right, an
d this is
sho
w
n in the foll
owin
g table
until the com
p
lete data va
lue of 0-0
-
0
-
1 is
store
d
in th
e
regi
ster. T
h
is data value
can no
w b
e
re
ad di
rectly from the o
u
tpu
t
s of QA to Q
D
.
Then th
e d
a
ta ha
s b
een
converted
fro
m
a
seri
al d
a
t
a input
sign
a
l
to a p
a
rallel
data o
u
tput.
The
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ISSN: 23
02-4
0
46
TELKOM
NI
KA
Vol. 12, No. 5, May 2014: 3849 – 38
62
3852
truth table,
shown in
Tabl
e 1,
sho
w
s t
he p
r
op
agat
i
on of th
e logi
c "1" th
rou
g
h
the regi
ster f
r
om
left to right with c
l
ock
puls
e
s
.
It is clear th
a
t
after the fourth clo
c
k pul
se,
the 4-bits
of data (0
-0-0-1
) are sto
r
ed in the
regi
ster and
will remai
n
there
prov
ided clocki
ng of
the
re
gister
has stopped. In
practi
ce the input
data to the
registe
r
may
con
s
i
s
t of va
riou
s
comb
i
n
ations
of logi
c "1" a
nd "0
". The p
r
a
c
tical
appli
c
ation of
the se
rial-i
n/parall
e
l-o
u
t shift registe
r
i
s
to co
nvert
data from
se
rial form
at on
a
singl
e wire to parallel form
at on multiple wire
s for example to illuminate LEDs (Light Emitting
Diod
es).
2.2. Serial-in to Serial-out (SISO)
T
h
is
s
h
ift r
e
gis
t
e
r
is
ve
r
y
s
i
milar
to
th
e
SIPO
a
b
o
ve
, e
x
c
e
p
t
th
a
t
th
e
d
a
t
a
w
a
s
r
ead
dire
ctly in a
parall
e
l form
from the
out
puts
QA to
QD. In this
c
i
rc
uit, da
ta are allowed to
flow
throug
h th
e
registe
r
and
o
u
t of the
othe
r e
nd. Si
n
c
e
there
i
s
o
n
ly o
n
e o
u
tput, th
e data
le
aves the
shift regi
ste
r
one bit at a t
i
me in a
seri
al pattern, h
e
n
ce th
e nam
e
Serial
-in to
Serial-Out S
h
ift
Regi
ster o
r
SISO.
The
SISO co
nfiguratio
n
i
s
one of
the si
mplest
struct
ure
s
of th
e
shift regi
sters
as it
ha
s
only three
co
nne
ction
s
, th
e seri
al in
put
(SI)
whi
c
h
de
termine
s
wh
a
t
enters th
e l
e
ft hand
flip-fl
op,
the se
rial
ou
tput (SO)
which i
s
ta
ke
n from
th
e
output of th
e rig
h
t han
d
flip-flop a
n
d
the
seq
uen
cing
clo
c
k
si
gnal
(Cl
k
). Figu
re
3 sh
ows
a
gen
eralize
d
4
bit seri
al-in seri
al-o
ut
shift
regi
ster.
Figure 3. 4-bi
t Serial-in to Serial-out Shi
ft Registe
r
SISO is the type of Shift
Regi
st
er that acts a
s
a tempora
r
y storag
e device or a
s
a time
delay device
for the data
,
with
the amount of time delay bein
g
cont
rolled
by the numb
er of
stage
s in the
regi
ster, 4, 8, 16 etc o
r
by vary
ing the ap
plicatio
n of the clo
ck p
u
lse
s
[21].
2.3. Parallel-in to Serial-out (PISO)
The Pa
rallel
-
i
n
to Seri
al-o
ut shift re
gist
er a
c
ts i
n
th
e opp
osite
way to the serial-in to
parall
e
l-o
u
t configuration.
The data i
s
lo
aded i
n
to t
he
regi
ster i
n
a p
a
rallel fo
rmat
i.e. all the dat
a
bits ente
r
the
i
r input
s sim
u
ltaneo
usly, to the pa
ra
llel
input pin
s
PA to PD of the re
giste
r
. The
data is th
en
rea
d
out
seque
ntially in the no
rm
a
l
shift-ri
ght
mode from t
he registe
r
at Q
rep
r
e
s
entin
g
the data
pre
s
ent at PA to
PD. This
out
put data i
s
transfe
rred o
n
e
bit at a tim
e
on
each clo
c
k cycle in a se
ri
al format. It is impo
rtant
to note that with this syste
m
a clo
ck p
u
l
s
e is
not requi
red
to parallel lo
ad the regi
st
er as it
is al
ready presen
t, but four clock pulses a
r
e
requi
re
d to unload the d
a
ta.
Figu
re 4 sh
ows a typical
4 bit Parallel-i
n
seri
al-out shift registe
r
.
Figure 4. 4-bi
t Parallel-in to
Serial-o
ut Shift Register
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TELKOM
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ISSN:
2302-4
046
Advan
c
e
s
on
CMOS Shift Regi
sters for
Digital
Data Storage
(Moh
a
m
m
ad Arif Sobhan Bhui
ya
n
)
3853
As thi
s
type
o
f
shift regi
ster co
nvert
s
p
a
rallel d
a
ta, su
ch
as an
8
-
bit
data
wo
rd
int
o
serial
format, it ca
n
be u
s
ed
to
multiplex ma
ny different i
nput line
s
int
o
a
single
se
rial d
a
ta st
re
am
whi
c
h can be
sent directly to a comp
uter
or
tran
smitted
over a com
m
unication
s line [22].
2.4. Parallel-in to Parallel-out (PIPO)
The final mo
de of operation is the Parallel-in to
Parallel-o
u
t Shift Regi
ster. Thi
s
type of
regi
ster al
so
acts
as a te
mporary sto
r
age devi
c
e o
r
as
a time d
e
lay device
similar to the
SISO
config
uratio
n [20]. The data is pr
esente
d
in a parallel
format to the parallel i
nput
pins PA to PD
and th
en tra
n
sferre
d tog
e
t
her di
re
ctly to their re
sp
e
c
tive outp
u
t
pins QA to
QD
by the
same
clo
ck p
u
lse. Then o
ne cl
o
ck p
u
lse load
s and
unloa
d
s
the re
giste
r
.
This a
rra
nge
ment for pa
ra
llel
loadin
g
and u
n
loadi
ng is
sh
own in Fig
u
re
5.
Figure 5. 4-bi
t Parallel-in to
Parallel-out Shift Registe
r
The PIPO sh
ift register is
the simple
st of th
e four configuration
s
as it has on
ly three
con
n
e
c
tion
s, the parall
e
l input (PI) whi
c
h determi
n
e
s
what ente
r
s t
h
e flip-f
lop, the parall
e
l output
(PO) a
nd the
sequ
en
cing
clo
ck
sign
al (Clk). Simila
r
to the Serial-i
n to Serial-o
ut shift regi
st
er,
this type of
re
gister al
so
acts a
s
a te
mpo
r
ary
st
orage
device
or
a
s
a
time
d
e
lay device, with
t
he
amount of ti
me delay b
e
i
ng varie
d
by
the freq
uen
cy of the clo
c
k pul
se
s. Also, in this typ
e
of
regi
ster there
are
no
interconne
ction
s
b
e
twee
n the
in
dividual flip
-flops si
nce no
seri
al
shifting
of
the data is re
quire
d.
2.5. Bidirecti
onal Shift Re
gisters
The re
giste
r
s discusse
d so far involved only right
shift ope
ratio
n
s. Each rig
h
t shift
operation h
a
s
the effe
ct of succe
s
sivel
y
dividing
the
binary n
u
mb
er by two. If the ope
ration
is
revers
ed (left
s
h
ift), this
has
the effec
t
of mult
iplying the numbe
r
by two. With suitabl
e gatin
g
arrang
ement a
se
rial shift regi
ster ca
n perfo
rm
b
o
th
ope
ration
s.
A bidire
ction
a
l, or
reversi
b
le,
shift re
giste
r
i
s
o
ne in
which the d
a
ta
ca
n be
shift
either left or right
[23].
A four-bit bidirec
t
ional
shift regi
ster
usin
g D flip-f
l
ops i
s
sh
own Figure 6.
Here a
set of
NAND gate
s
are
configu
r
ed a
s
OR ga
tes to
sel
e
ct
data in
puts from the
right or left ad
jace
nt bistabl
es, as
se
le
cte
d
by the LEFT/RIGHT
con
t
rol line.
Figure 6. 4-bi
t Bidirection
a
l
Shift Registe
r
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ISSN: 23
02-4
046
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KA
Vol. 12, No. 5, May 2014: 3849 – 38
62
3854
3. CMOS Shift Registers
The
rapi
d d
o
w
n-scale
in
CMOS te
ch
n
o
logy h
a
s ad
vance
d
the
rese
arch i
n
almost
all
area
s of mi
croele
c
troni
cs [24-28].
CM
OS invert
e
r
s (Co
m
plem
e
n
tary MOSF
ET Inverters) are
some of the
most wid
e
ly use
d
and ad
aptable MOS
F
ET inverters used in
chip
desi
gn [29]. They
operate
with
very little po
wer lo
ss an
d
at rel
a
tively high
spe
ed [
30]. Furth
e
rmore, th
e CMOS
inverter ha
s
good
logi
c b
u
ffer cha
r
a
c
teristi
cs, i
n
th
at, its noi
se
margi
n
s in b
o
th lo
w an
d
hig
h
states are la
rge. Thi
s
sho
r
t des
cri
p
tion
of CMOS i
n
verters
gives
a ba
sic un
de
rstan
d
ing
of t
he
how
a CMO
S
inverter
works. It will
cover inpu
t/o
utput ch
aract
e
risti
cs, M
O
SFET state
s
at
different input
voltages, an
d power lo
sses du
e to ele
c
tri
c
al cu
rrent
.
A CMOS inverter
contai
ns a PMOS and a NM
OS transi
s
tor
con
n
e
cted at the
drain a
nd
gate terminal
s, a
sup
p
ly voltage Vd
d at
the PM
OS
source te
rmin
al, and
a g
r
o
und
con
n
e
c
te
d at
the NMOS so
urce termin
al, were Vin is
con
n
e
c
t
ed to the gate term
inals an
d Vout is conn
ect
e
d
to the d
r
ain t
e
rmin
als
(Fig
ure
7). It is i
m
porta
nt
to n
o
tice that th
e
CMOS
doe
s not contain
any
resi
sto
r
s, whi
c
h ma
ke
s it more p
o
we
r
efficient t
hat a regul
ar resi
stor-MOSFE
T inverter [31
]. As
the voltage
a
t
the input
of the CMOS
device va
rie
s
betwe
en
0
and 5
volt
s, the
state of
the
NMOS an
d PMOS varie
s
a
c
cordi
ngly.
Figure 7. Sch
e
matic of a CMOS Inverter Circuit
3.1. Transistor S
w
i
t
ch M
odel
The switch m
odel of the MOSFET tran
si
stor i
s
define
d
as Ta
ble 2.
Table 2. Co
n
d
ition and Sta
t
e of MOSFET Tran
si
stor
Switch Mo
del
MOSFE
T
C
o
nd
i
t
io
n
on
MOSFE
T
State of
MOSFE
T
NMO
S
Vgs < Vtn
O
FF
NMO
S
Vgs < Vtn
O
N
PMO
S
Vsg < Vtp
O
FF
PMO
S
Vsg < Vtp
O
N
Whe
n
V
in
is
low, the
NMOS
is
"off", while the
PMOS
st
ays "on": in
st
antly cha
r
gi
n
g
V
out
to
logic high. When
V
in
i
s
hig
h
, the NMOS
is "o
n an
d th
e PMOS i
s
"o
n: drai
ning th
e voltage
at
V
out
to logic
low.
This mod
e
l o
f
the CMOS i
n
verter hel
ps to
de
scri
be t
he inve
rter conceptually,
but do
e
s
not accu
ratel
y
describ
e the voltage tran
sfer
cha
r
a
c
teristics to any e
x
tent. A more full descripti
on
employs m
o
re cal
c
ulatio
ns and more de
vice state
s
.
3.2. Multiple State T
r
ansi
stor Mod
e
l
The multiple
state tran
si
stor mo
del is
a
very
accu
rat
e
way to mo
d
e
l the CM
OS
inverter
[32]. It reduces
the
s
t
ates of the
MOS
F
ET into
three modes of
operatio
n: Cut-Off, Linear,
and
Saturated: e
a
ch
of whi
c
h
have a different dep
ende
nce
on
V
GS
and
V
DS
. Th
e
formul
as wh
ich
govern the
state and the curr
ent in that given state
is
given by Tabl
e 3.
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
2302-4
046
Advan
c
e
s
on
CMOS Shift Regi
sters for
Digita
l Data Storage
(Moh
a
m
m
ad Arif Sobhan Bhui
ya
n
)
3855
Table 3. NM
OS and PMO
S
Mode of Operatio
n
NMOS C
h
aract
e
r
istics
C
o
nd
i
t
io
n
on
V
GS
C
o
nd
i
t
io
n
on
V
DS
Mode of
O
p
e
r
at
i
on
ID = 0
VG
S < VTN
ALL
Cut-off
ID = KN [2 ( V
G
S
-
VTN )V
DS - VD
S
2
]
VGS > VTN
VDS<VGS-VT
N
Linear
ID = KN ( V
G
S –
VTN )
2
V
GS
> V
TN
V
DS
>V
GS
-V
TN
Saturated
PMOS Ch
aracte
r
istics
C
o
nd
i
t
io
n
on
V
SP
C
o
nd
i
t
io
n
on
V
SD
Mode of
O
p
e
r
at
i
on
ID = 0
VSG < -VTP
ALL
Cut-off
ID = KP [2 ( VSG-VTP )VSD
- VS
D
2
]
VSG > VTP
VSD<VSG+VTP
Linear
ID = KP ( VSG
–
VTP )
2
V
SG
> -V
TP
V
SD
>V
SG
+V
TP
Saturated
3.3. Pass Tra
n
sistor Lo
gic
A popula
r
an
d widely u
s
ed
alternative to
compl
e
ment
ary CMOS i
s
pass tra
n
si
st
or logi
c.
Pass tran
sist
or logi
c attem
p
ts to red
u
ce the numbe
r o
f
transi
s
tors required to im
plement logi
c by
allowin
g
the
prima
r
y input
s to d
r
ive gat
e termin
als
a
s
well a
s
sou
r
ce/drain te
rmi
nals [3
3]. Thi
s
is
in cont
ra
st to logic fa
milies that only
allow
p
r
ima
r
y inputs to
drive the g
a
te termin
als
of
MOSFETS. Figure
8 sh
ows a tran
si
stor level im
plem
entation of th
e AND fun
c
ti
on co
nst
r
u
c
te
d
usin
g NM
OS
tran
sisto
r
s. I
n
this g
a
te, if the B i
nput i
s
hig
h
, the to
p tran
sisto
r
i
s
turned o
n
a
n
d
copi
es th
e in
put A to the
output F.
Wh
en inp
u
t B
is
low, the
botto
m pa
ss tran
si
stor i
s
tu
rne
d
on
and pa
sses a
0. The switch driven by B seem
s to
be
redun
dant at
first glance. Its presen
ce i
s
essential
to e
n
su
re
that a
l
o
w-i
m
pe
dan
ce path
exis
t
s
to the
sup
p
ly
rails un
de
r all
ci
rcumsta
n
ces,
or, in this pa
rticula
r
ca
se, when B is low.
The potential
advantage
of pass tr
an
sistor is that
a fewer
n
u
m
ber of tran
si
stors are
requi
re
d to impleme
n
t a given functio
n
. Pass tran
sistor lo
gic u
s
es fewer d
e
vice
s and th
erefore
has lo
we
r ph
ysical
cap
a
cit
ance [34]. Un
fortunatel
y, a
NMOS devi
c
e is effective
at passing
a 0
but is po
or a
t
pulling a no
de to V
DD
. In
pass tran
si
stor logi
c, t
he pass tra
n
si
st
ors
are
used
to
pass hi
gh a
n
d
low volta
g
e
s
. The
r
efo
r
e,
whe
n
the
p
a
ss tra
n
si
stor
p
u
lls a
nod
e h
i
gh, the outp
u
t
only ch
arg
e
s up to V
DD
-VTn. In fac
t, the s
i
tuation is
wors
en
ed
by the fact
that the devi
c
e
s
experie
nce b
ody effect si
nce th
ere i
s
a sig
n
ifica
n
t sou
r
ce to bo
dy voltage when p
u
lling h
i
g
h
sin
c
e the bo
d
y
is tied to GND a
nd the source cha
r
ge
up clo
s
e to V
DD
.
Figure 8. Pass Tra
n
si
sto
r
Impleme
n
tatio
n
of an AND
Gate
3.4. Static CMOS Design
The m
o
st
wid
e
ly used l
ogi
c style i
s
static
co
mplem
ent
ary CMOS
[3
5].
The static CMOS
style is reall
y
an extensi
on of the CMOS invert
e
r
to multiple i
nputs. In review, the p
r
im
ary
advantag
e of the CMOS st
ructure is robu
stne
ss (i.e, lo
w se
ns
itivity to noise), goo
d perfo
rman
ce,
and lo
w po
wer con
s
umpti
on (with no
static power
c
onsumption
)
[36]. Therefo
r
e, most of those
prop
ertie
s
a
r
e ca
rrie
d
ov
er to large f
an-in l
ogi
c g
a
tes impl
em
ented u
s
ing
the sam
e
ci
rcuit
topology. Th
e
co
mplem
ent
ary CMOS
circuit
style falls
und
er
a b
r
o
a
d cl
ass
of logi
c
circuit
s
call
ed
static
circuit
s
in whi
c
h
at e
v
ery point in t
i
me (e
x
c
ept
d
u
ring
the
swit
chin
g tra
n
si
e
n
ts), e
a
ch ga
te
output i
s
co
n
necte
d to
eith
er V
DD
or
V
SS
via a l
o
w-re
si
stan
ce
path.
Also, the
out
puts
of the
ga
tes
assume
at all
times th
e val
ue of the
Boo
l
ean fun
c
ti
on
impleme
n
ted by
the
ci
rcuit [37]
(ign
orin
g,
once agai
n, the tran
sie
n
t effects d
u
rin
g
swit
ching
pe
riod
s). Thi
s
i
s
in contrast
to the dynam
ic
circuit cla
s
s
that relies
o
n
temporary
stora
ge
of si
gnal value
s
on the ca
pa
citan
c
e of hi
gh
-
impeda
nce ci
rcuit no
de
s. The latter ap
proa
ch
h
a
s t
he advantag
e that
the resulting gate i
s
simple
r
and f
a
ster.
On th
e
other ha
nd, i
t
s de
sig
n
an
d
ope
ration
are mo
re involv
ed tha
n
tho
s
e
of
its static coun
terpa
r
t, due to an increa
se
d sen
s
itivity to noise.
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TELKOM
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KA
Vol. 12, No. 5, May 2014: 3849 – 38
62
3856
A static CMO
S
gate is a
combinatio
n of
tw
o networks, call
ed the
pull-u
p
net
wo
rk
(PUN)
and th
e p
u
ll-d
o
wn
net
wo
rk
(PDN) [38] a
s
sh
own in
Fig
u
re
9. T
h
is shows
a g
ene
ric
N in
put l
ogi
c
gate where al
l inputs a
r
e di
stribute
d
to b
o
th t
he pull
-
u
p
and p
u
ll-d
o
w
n n
e
two
r
ks.
The fun
c
tion
of
the PUN i
s
to provide a
co
nne
ction bet
wee
n
the out
put and V
DD
anytime the o
u
tput of the logic
gate is mea
n
t to be 1
(b
ased on
the in
p
u
ts). Simila
rly, the functio
n
of the PDN i
s
to co
nne
ct th
e
output to V
SS
whe
n
the
ou
tput of the lo
gic g
a
te is
m
eant to b
e
0.
The PUN
an
d PDN net
wo
rks
are
con
s
tru
c
t
ed in a mutu
ally exclusive
fashion
su
ch
that “one an
d only one
” o
f
the networks is
con
d
u
c
ting in
steady state
[39]. In this way,
on
ce th
e tran
sient
s
have settled, a path al
wa
ys
exists betwe
en
V
DD
a
nd t
he o
u
tput F,
reali
z
ing
a
hi
gh o
u
t
put
(“o
ne”), o
r
, alte
rnatively, betwee
n
VSS and F for a low output (“zero”). Thi
s
is equival
ent
to stating that
the
output node is
always
a
low-i
m
pe
dan
ce no
de in st
eady state [4
0].
Figure 9. Co
mpleme
ntary Logi
c Gate a
s
a Co
mb
inati
on of a PUN (pull-u
p
netwo
rk) and a PDN
(pull
-
do
wn ne
twork)
Figure 10. Pulling Do
wn a
Nod
e
usi
ng NMOS and PM
OS Switche
s
Figure 11. Pulling up a Nod
e
usin
g NMO
S
and PMOS Switche
s
A transi
s
to
r can be
co
nsi
d
ered
as
a swi
t
ch c
ontrolled
by its gate
si
gnal [41]. An
NMOS
swit
ch is on
whe
n
the co
ntrolling
sign
al is high an
d is off when
the controlli
ng sign
al is low. A
PMOS tran
si
stor a
c
ts
as
an inverse
switch th
at
is
on wh
en the
controlling
si
gnal is l
o
w
a
nd off
whe
n
the
con
t
rolling
sign
al
is hig
h
. The
PDN i
s
con
s
t
r
ucte
d u
s
in
g
NMOS d
e
vices, while PM
OS
transi
s
to
rs
are used in the
PUN. Th
e p
r
imary
rea
s
on for this
c
hoic
e
is
that NMOS trans
i
s
t
ors
produce “strong zero
s,” and PMOS devices gener
ate “strong ones”. To illu
strat
e
this, consider
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TELKOM
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ISSN:
2302-4
046
Advan
c
e
s
on
CMOS Shift Regi
sters for
Digita
l Data Storage
(Moh
a
m
m
ad Arif Sobhan Bhui
ya
n
)
3857
the example
s
sho
w
n i
n
Fig
u
re
10 a
nd Fi
gure
11. In
Fi
gure
10, the
output capa
ci
tance i
s
initial
l
y
cha
r
ge
d to V
DD
. Two possible di
scha
rge scen
ari
o
’s ar
e sho
w
n.
An NMOS
device p
u
lls
the
output all the
way down to GND, whil
e a PM
OS lowe
rs th
e ou
tput no furth
e
r than |V
Tp
|,
the
PMOS turn
s
off at that point, and sto
p
s
contrib
u
ting
discha
rge
current. NM
O
S
transi
s
tors
are
hen
ce the p
r
eferred devi
c
es in the P
D
N. Simila
rly, two alte
rnativ
e app
roa
c
he
s to charging
up a
cap
a
cito
r are
sho
w
n in F
i
gure 1
1
, with the out
put
load initially at GND. A PMOS switch
su
cceed
s in
cha
r
gin
g
the
output all th
e
way to V
DD
, while th
e
NM
OS devic
e fails
to raise the
output above
V
DD
-V
Tn
. This
explain
s
why
PMOS transi
s
tors
are pref
erentially u
s
e
d
in a PUN.
3.5. D
y
namic
MOS Desig
n
The dynami
c
stora
g
e
me
ch
anism
i
s
wide
ly us
ed for momenta
r
y storage of data in digital
circuits [4
2]. Among the te
chn
o
logie
s
wi
dely used for digital de
sig
n
, MOS tech
nology p
r
ovid
es
two un
usual f
eature
s
th
at lead to p
a
rti
c
u
l
arly
efficient
way to
store
data mom
ent
arily. The
s
e t
w
o
feature
s
a
r
e
the MOS tra
n
si
stor’
s
extremely
hig
h
i
nput resi
stan
ce
and th
e a
b
ility of an M
O
S
transi
s
to
r to f
unctio
n
a
s
a
nearly id
eal e
l
ectri
c
al
swit
ch.
The circuit combi
nation of
these
fe
atu
r
es
with the
sou
r
ce te
rminal
of
one M
O
S tra
n
si
stor
co
nne
cted to th
e ga
te terminal
of
a se
co
nd M
O
S
transi
s
to
r all
o
ws ele
c
tri
c
a
l
cha
r
ge to
be sto
r
ed
m
o
menta
r
ily o
n
or
rem
o
ved from the
gate
terminal of the s
e
c
o
nd trans
i
s
t
or [43].
The three ci
rcuit
s
of Fig
u
re 1
2
, 13, 14 show
typi
cal
circuit co
nfiguratio
ns
use
d
to
achi
eve dyna
mic cha
r
ge
storag
e. The p
a
ss tran
si
stor and tra
n
smi
ssi
on g
a
te de
vices
are
ofte
n
desi
gne
d with
the minimum
size tran
si
stor to redu
ce l
a
yout are
a
. Figure
12 i
s
useful with NM
OS
circuit, while t
he other two example
s
fro
m
CMOS ci
rcuits.
Operation of t
he ci
rcuit of F
i
gure
12 d
e
p
end
s
on
wh
ether the
pa
ss t
r
an
sisto
r
i
s
of
f or on.
If the pa
ss transi
s
tor is at
a hi
gh lo
gic
voltage, t
hen
the p
a
ss tra
n
si
stor
co
ndu
cts. In thi
s
ca
se,
the gate
term
inal of
the i
n
verter inp
u
t tra
n
si
stor will
b
e
cha
r
ge
d o
r
discha
rge
d
a
c
cordi
n
g
to t
h
e
logic voltag
e at the input to the pass transi
s
to
r. Th
e
time requi
re
d to cha
r
ge
or di
scharge
the
gate termin
al
will dep
end o
n
the gate ca
pacita
n
ce,
the pass tra
n
si
stor resi
stan
ce, and the si
g
nal
sou
r
ce. Th
e
gate
can
be
discha
rge
d
to
0 V, o
r
ca
n
be
cha
r
ge
d t
o
V
DD
– V
TN
.
This sets th
e
gate
terminal
to eit
her l
ogi
c 0
or logi
c 1 val
u
e
,
respe
c
tively. Becau
s
e
th
e inverte
r
in
p
u
t voltage
ran
ge
has
bee
n re
d
u
ce from the
norm
a
l ra
nge
of V
L
to V
DD
to a sm
alle
r ra
nge of V
L
to
V
DD
– V
TN
by the
pass tran
si
stor, the swit
ch
ing thre
shol
d voltage V
M
should be lo
wered by incre
a
sing the inverte
r
sizi
ng rat
i
o
k
from 4 to abo
ut 8.
Figure 12. NMOS Dynami
c
Storag
e Circuit
Figure 13. CMOS Dynami
c
Storag
e Circuit
When the gate of the
pass transistor i
s
at
logi
c l
o
w
voltage, the
pass t
r
ansist
or i
s
off,
thereby i
s
olat
ing any
cha
r
g
e
on th
e gate
cap
a
cita
nce
of the inverte
r
input tra
n
si
st
or. Thi
s
cha
r
g
e
(or the l
a
ck
thereof
)
rep
r
ese
n
ts th
e
stored
logi
c v
a
lue. If the
store
d
cha
r
g
e
were
pe
rfe
c
tly
isolate
d
, the logic valu
e would be
store
indefinitely. Ho
wever, the
isolation i
s
l
e
ss than p
e
rf
ect,
prima
r
ily be
cause of le
akage th
rou
g
h
the reve
rse
-
bia
s
ed
dio
d
e create
d
b
e
tween
the p
a
ss
transi
s
to
r so
urce diffusio
n
and the substrate
[35]
. Leaka
ge al
so o
c
curs th
roug
h the p
a
ss
transi
s
tor swi
t
ch. Because the stor
ed
charge will l
e
ak away over
time, this ci
rcuit is term
ed
a
dynamic
storage ci
rcuit. For dynami
c
storage
wi
th p
r
esent MOS
device
s
, the
prima
r
y ch
arge
leakage
path
occu
rs thro
u
gh the
diod
e
between
so
urce diffu
sion
and th
e
sub
s
trate. A
s
M
O
S
pro
c
e
s
ses are
created with
linear
ly
scaled-do
wn d
e
vice
s, su
b
-
t
h
re
shol
d lea
k
age through
the
pass tran
si
stor’s
cha
nnel
will be
come t
he pre
domi
n
a
n
t leaka
ge fa
ctor.
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KA
Vol. 12, No. 5, May 2014: 3849 – 38
62
3858
Dynami
c
sto
r
age can be i
m
pleme
n
ted i
n
CMOS
by
repla
c
in
g the
pass tran
si
stor with
transmissio
n gate, as
sho
w
n in Fig
u
re 13. Note t
he i
n
crea
se in
circuit complexit
y
cau
s
ed by t
h
e
addition
of p
-
cha
nnel
tran
sistor in th
e transmi
ss
ion
g
a
te an
d the
requireme
nt for
a d
ual-pol
arity
control sign
al
.
The situatio
n
can be all
e
viated some
what
with th
e ci
rcuit of
F
i
gure
14
in
this
circuit, calle
d
a level-re
st
oring inve
rter; n-ch
annel
pass tran
si
st
or is follo
we
d by a spe
c
ial
inverter with
a wea
k
p
-
cha
nnel fe
edb
ack tran
sisto
r
to
re
store th
e l
ogic hig
h
lev
e
l. The
p
-
cha
nnel
transi
s
to
r mu
st be si
zed to have an e
quivalent re
si
stan
ce mu
ch
greate
r
than
the serie
s
p
u
ll-
down re
si
sta
n
ce
of the pa
ss tran
si
sto
r
and any
circu
i
t that drives t
he pa
ss tran
sistor in
put. T
h
e
pass tran
si
stor ca
n discha
rge the invert
er gate to 0 V to give a good low logi
c level. In
this ca
se,
the inverter output is high
and
the p-channel feed
back transi
stor is off.
As explained earlier, an
n-chan
nel pa
ss tra
n
si
sto
r
can
not rai
s
e the
voltage high enou
gh to ensu
r
e that
the p-ch
ann
el
transi
s
to
r of the inverter i
s
off.
Neverthe
less, the pass tran
sisto
r
can pull the inverter input h
i
gh
enou
gh to fo
rce th
e inve
rter’s
output to
a low
lo
gic
voltage. This low voltage
turns
on the
p-
cha
nnel fe
ed
back tran
sist
or, thereby p
u
lling the
i
n
verter i
nput to
the upp
er
su
pply voltage
and
holdin
g
it there.
Figure 14. CMOS Pass Transi
s
tor Stor
age Ci
rcuit wi
th Level Re
storation
Dynami
c
storage
i
s
wid
e
ly
used within
MOS
ci
rcuits be
cau
s
e
of
the si
mplicity
of the
requi
re
d circu
i
try [44]. The NMOS versio
n of figur
e 12
requi
re
s only
three tra
n
si
stors, while th
e
CMOS versio
n of Figure 1
4
requi
re
s just four tr
ansi
s
t
o
rs. Th
us, dy
namic
storag
e is are
a
-efficient
comp
ared to the static sto
r
age ci
rc
uits. A frequent use of dynamic st
orag
e circuits is to cre
a
te
shift regi
sters [45]. The followin
g
discu
s
sion
sh
o
w
s shift registe
r
s
that are built
upon a
gen
eric
MOS dynami
c
sto
r
age
sta
ge co
nsi
s
ting
of a pass tran
sisto
r
and a
simple inverte
r
for NMOS or a
level-restoring inverter for
CMOS.
3.6. D
y
namic
VS Static
Dynami
c
and
static sto
r
a
g
e
are pa
rt of digital stora
ge:
a.
Dyna
mic Storage: Thi
s
type
of sto
r
age devic
e a
llows the
u
s
er to
work
within the
stora
ge d
e
vice, makin
g
ch
ange
s while
workin
g withi
n
the file, and
easily saving
chan
ge
s to a
file
or d
a
taba
se.
This type
of storage
devi
c
e h
a
s
m
any
advantag
es
to wo
rk
withi
n
gen
ealo
g
ical
databa
se
s an
d freque
ntly alter the data file,
and add, remove, and chang
e inform
ation [47].
b. Static Storage: Thi
s
typ
e
of
sto
r
a
ge
device
allo
ws the u
s
e
r
to
save data
at a
sp
ecifi
c
point in time
and cre
a
te a
non-vul
n
e
r
abl
e versi
on
of the data that
may not be e
a
sily altered
or
deleted, a
s
wi
th dynamic st
orag
e device
s
[48].
Table 4. Co
m
pari
s
on b
e
tween Static Lo
gic an
d Dyna
mic Logi
c
Static Logi
c
D
y
n
a
mic
L
ogic
Valid logic le
vels are st
ead
y
-
state
operating points
[40]
The ope
ration d
epends on temp
orar
y storag
e of
charge in parasitic node capacitances [32]
Outputs a
r
e g
e
n
e
rated in
respon
se to input voltag
e
levels after a
certain time de
lay
,
and
it can
preserve its outp
u
t levels as long as there is po
w
e
r
[22]
The stored charg
e
does not remain indefinitely
,
so
must be upd
at
ed or
ref
r
eshe
d. This re
quire
s
establishment of an update
or
recharge pa
th to th
e
capacitance frequentl
y
enough t
o
preserve valid
voltage levels [4
6]
All gate output
nodes have a
c
onducting path
t
o
V
DD
or
GN
D, e
x
cept
w
h
e
n
inp
u
t changes are
occurring [5]
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