Indonesi
an
Journa
l
of El
ect
ri
cal Engineer
ing
an
d
Comp
ut
er
Scie
nce
Vo
l.
23
,
No.
3
,
Septem
ber
20
21
,
pp.
1
674
~
1680
IS
S
N: 25
02
-
4752, DO
I: 10
.11
591/ijeecs
.v
23
.i
3
.
pp
1674
-
1680
1674
Journ
al
h
om
e
page
:
http:
//
ij
eecs.i
aesc
or
e.c
om
Effici
ent
hardwa
re imp
lem
entatio
n for lig
htwei
ght mCrypt
on
algorith
m usin
g FPGA
Ya
sir
A
mer
Abbas,
Ah
me
d
Sa
la
h H
amee
d,
S
afa H
az
im
Alw
an,
Ma
r
yam
Ad
n
an F
adel
Depa
rtment
o
f
C
om
pute
r
Engi
n
e
eri
ng,
Coll
ege of
Engi
n
ee
ring
,
U
nive
rsit
y
of
Di
y
a
la
,
Baqub
ah, I
ra
q
Art
ic
le
In
f
o
ABSTR
A
CT
Art
ic
le
history:
Re
cei
ved
Feb
26
,
2021
Re
vised
Ju
l
27
,
2021
Accepte
d
Aug
8
,
2021
The
l
ight
w
ei
ght
cr
y
p
togra
ph
y
i
s
used
for
low
ava
i
la
bl
e
resour
ce
s
devi
c
es
such
as
rad
io
fr
eque
nc
y
ide
nt
ifica
t
ion
(RFID
)
tags
,
int
ern
et
of
t
hings
(IoT
s)
and
wire
le
ss
se
nsor
net
works
.
In
such
ca
se
,
th
e
l
ight
weigh
t
cr
y
ptogr
aphic
al
gorit
hm
s
should
conside
r
power
con
sum
pti
on,
design
are
a
,
spee
d,
and
throughput
.
Th
is
pape
r
pre
sents
a
new
arc
hitec
tu
re
of
m
Cry
pton
li
ghtwei
gh
t
cr
y
p
togra
ph
ic
a
l
gorit
hm
which
conside
rs
the
a
bove
-
m
ent
ione
d
condi
ti
ons
.
Resourc
e
-
share
d
struct
ure
is
used
to
red
uce
the
are
a
of
the
new
arc
hi
te
c
tur
e.
The
proposed
a
rch
itect
ur
e
is
implemente
d
using
ISE
Xili
nx
V14,5
and
Sparta
n
3
FP
G
A
pla
tform.
The
sim
ula
ti
on
r
esult
s
int
roduc
e
d
tha
t
the
proposed
design
area
is
375
of
sl
ic
es,
up
to
302
MH
z
oper
ating
f
req
uency
,
a
throughput
of
64
6
Mbps
,
eff
ic
i
en
c
y
of
1
.
7
Mbps
/sli
ce
and
0
.
089
W
at
t
power
consum
pti
on.
Thus,
th
e
pr
oposed
arc
h
it
e
ct
ure
ou
tpe
rfor
m
s
si
m
il
ar
arc
hi
te
c
ture
s
in t
erms
of
area, spe
ed,
eff
i
ci
en
c
y
an
d
throughput.
Ke
yw
or
ds:
FPGA
Hardwa
re a
rc
hi
te
ct
ur
e
Ligh
t
weig
ht
m
Crypton
VHDL
This
is an
open
acc
ess arti
cl
e
un
der
the
CC
B
Y
-
SA
l
ic
ense
.
Corres
pond
in
g
Aut
h
or
:
Ah
m
ed
Sala
h
Ham
eed
Dep
a
rtm
ent o
f C
om
pu
te
r
E
ng
i
neer
i
ng
,
Un
i
ve
rsity
o
f
D
iy
al
a
Diya
la
, Baq
uba, Colle
ge
of
E
ng
i
neer
i
ng Bra
nch
P.
O.
B
OX
-
1,
Ir
a
q
Em
a
il
: ah
m
edh
a
m
eed_
en
g@u
od
iy
al
a.ed
u.
i
q
1.
INTROD
U
CTION
L
i
g
h
t
w
e
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g
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y
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w
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r
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s
.
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l
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n
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o
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I
o
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s
)
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r
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l
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s
s
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n
s
o
r
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t
w
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k
s
.
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n
l
o
w
-
r
e
s
o
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r
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v
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r
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u
m
p
t
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z
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f
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a
r
d
w
a
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n
d
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c
o
s
t
o
f
i
m
p
l
e
m
e
n
t
a
t
i
o
n
[
1
]
-
[
4
]
.
L
o
w
-
r
e
s
o
u
r
c
e
s
d
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v
i
c
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q
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p
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[
5
]
-
[
8
]
.
T
h
i
s
l
i
m
i
t
a
t
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n
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n
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s
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v
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,
h
a
r
d
[
9
]
.
S
e
c
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r
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y
a
p
p
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t
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[
1
0
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-
[
1
3
]
.
T
h
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5
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Evaluation Warning : The document was created with Spire.PDF for Python.
Ind
on
esi
a
n
J
E
le
c Eng &
Co
m
p
Sci
IS
S
N:
25
02
-
4752
Eff
ic
ie
nt h
ard
ware im
pleme
nt
ation
f
or
li
ght
we
igh
t
mCrypt
on a
l
gorit
hm usi
ng FP
GA
(
Y
asi
r Am
er
A
bbas
)
1675
2.
RE
LATE
D
W
ORKS
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p
a
r
a
l
l
e
l
m
o
d
e
l
d
e
s
i
g
n
.
T
h
e
r
e
a
l
t
i
m
e
t
e
s
t
i
n
g
p
r
o
v
i
d
e
d
i
n
[
1
7
]
s
h
o
w
s
a
n
e
f
f
i
c
i
e
n
t
h
a
r
d
w
a
r
e
d
e
s
i
g
n
w
i
t
h
l
o
w
e
n
e
r
g
y
c
o
n
s
u
m
p
t
i
o
n
.
In
So
li
m
an
et
al.
[
18]
prese
nt
ed
an
opti
m
ized
tw
o
ver
si
on
s
of
the
AE
S
a
lgorit
hm
in
whic
h
a
sm
all
and
lo
w
po
wer
con
s
um
ption
im
ple
m
entat
ion
fo
r
sec
ur
it
y
app
li
cat
io
ns
in
I
oT
is
pro
vid
e
d.
These
de
sig
ns
us
e
an
it
erati
ve
l
oopi
ng
an
d
pi
pe
li
ned
a
rch
it
ec
ture
i
n
dev
el
opin
g
the
te
ch
ni
qu
e
of
im
ple
m
enting
t
he
A
ES
-
128
sta
nd
a
rd
al
gor
it
h
m
[18]
.
In
[19]
pro
pose
d
reli
able
er
r
or
detect
ion
arch
it
ect
ures
f
or
tw
o
of
fa
m
ou
s
Crypto
gr
a
phic
a
lgorit
hm
s
(S
im
on
and
S
pec
k).
T
he
propos
ed
arc
hitec
tur
e
s
ha
ve
inc
reas
ed
in
the
c
over
age
of
error
detect
io
n
an
d
redu
ce
d
in
desig
n
com
plexity
.
The
po
wer,
ar
ea,
an
d
delay
tim
e
of
the
new
i
m
ple
m
entat
io
n
a
re acce
ptabl
e an
d
the
d
e
sig
n
is e
ff
ic
ie
nt
f
or lo
w res
ources
li
gh
twei
gh
t
appli
cat
ion
s
[
19
]
.
M
h
a
o
u
c
h
e
t
a
l
.
[
2
0
]
p
r
o
p
o
s
e
d
a
n
o
p
t
i
m
i
z
e
d
v
e
r
s
i
o
n
f
o
r
P
i
c
c
o
l
o
b
l
o
c
k
c
i
p
h
e
r
i
n
F
P
GA
.
T
w
o
s
u
g
g
e
s
t
e
d
d
e
s
i
g
n
s
i
t
e
r
a
t
i
v
e
a
n
d
s
e
r
i
a
l
a
r
c
h
i
t
e
c
t
u
r
e
s
o
f
P
i
c
c
o
l
o
c
i
p
h
e
r
a
r
e
p
r
e
s
e
n
t
e
d
a
n
d
s
h
o
w
e
d
a
r
e
d
u
c
e
d
a
r
e
a
i
m
p
l
e
m
e
n
t
a
t
i
o
n
r
e
l
a
t
e
d
w
i
t
h
i
m
p
r
o
v
e
m
e
n
t
i
n
s
p
e
e
d
c
o
m
p
a
r
e
d
t
o
t
h
e
s
t
a
n
d
a
r
d
i
m
p
l
e
m
e
n
t
a
t
i
o
n
o
f
t
h
e
a
l
g
o
r
i
t
h
m
[
2
0
]
.
A
b
d
u
l
l
a
h
e
t
a
l
.
[
2
1
]
s
u
g
g
e
s
t
e
d
a
n
e
w
f
l
e
x
i
b
l
e
a
r
c
h
i
t
e
c
t
u
r
e
t
o
i
m
p
l
e
m
e
n
t
P
R
I
N
C
E
a
l
g
o
r
i
t
h
m
f
o
r
h
i
g
h
s
p
e
e
d
,
s
m
a
l
l
a
r
e
a
,
a
n
d
l
o
w
p
o
w
e
r
d
e
s
i
g
n
.
T
h
e
F
P
G
A
i
m
p
l
e
m
e
n
t
a
t
i
o
n
i
s
u
s
e
d
t
o
b
u
i
l
d
a
p
r
o
c
e
s
s
o
f
e
n
c
r
y
p
t
i
o
n
w
i
t
h
q
u
a
n
t
u
m
c
r
y
p
t
o
g
r
a
p
h
y
p
r
o
t
o
c
o
l
(
B
B
8
4
)
i
n
o
n
e
c
l
o
c
k
c
y
c
l
e
.
T
h
e
p
r
e
s
e
n
t
e
d
a
r
c
h
i
t
e
c
t
u
r
e
s
c
o
u
l
d
f
i
t
a
l
l
b
a
s
i
c
c
r
y
p
t
o
g
r
a
p
h
i
c
a
l
g
o
r
i
t
h
m
s
t
h
a
t
u
s
e
t
o
b
u
i
l
d
a
l
g
o
r
i
t
h
m
s
f
o
r
a
p
p
l
i
c
a
t
i
o
n
s
l
i
k
e
s
m
a
r
t
c
a
r
d
a
n
d
o
t
h
e
r
p
o
r
t
a
b
l
e
d
e
v
i
c
e
s
[
2
1
]
.
3.
MCR
YPTO
N ALGO
RITH
M
MC
rypto
n
is
a
64
-
bit
li
gh
twei
gh
t
blo
c
k
ci
ph
er
crypt
ogra
phic
al
go
rithm
presented
i
n
20
06
[
22
]
,
[
23
]
.
S
ubsti
tuti
on
p
e
rm
utati
on
(
SP
)
structu
re
is
use
d
in
desi
gn
of
m
Crypton
al
gorithm
arch
it
ect
ur
e.
T
he
al
gor
it
h
m
is
cl
assifi
ed
ac
cordin
g
t
o
t
he
key
siz
e
in
t
o
m
Crypton
-
64,
m
Crypton
-
96
and
m
Crypton
-
12
8.
The
pro
po
s
ed
i
m
ple
m
entat
io
n
is
an
a
rc
hite
ct
ur
e
of
64
-
bit
m
Crypton
with
a
key
siz
e
of
64
-
bit.
The
ov
e
rall
view
of
t
he
pr
ese
nted
arc
hi
te
ct
ur
e is s
how
n
in
Fig
ure
1.
Figure
1.
The
ov
e
rall
v
ie
w of t
he prese
nted
arch
it
ect
ure
MC
rypto
n
an
d
Crypto
n
al
go
rithm
s
us
e
a
4
×4
ar
ray
to
re
pr
ese
nt
an
8
-
by
te
data
blo
c
k
[
22
]
.
T
he
al
gorithm
m
a
i
nly
has
five
di
f
fer
e
nt
pr
ocesse
s:
the
nonlinea
r
s
ub
sti
tuti
on
proces
s,
t
he
bit
per
m
utati
on
process
,
the
row
-
t
o
col
um
n
transpositi
on
pr
ocess,
ke
y
scheduli
ng
proces
s
an
d
key
add
it
ion
proce
ss.
T
welv
e
rou
nd
s
of
the
five
proces
ses
m
entioned
above
a
re
ap
pl
ie
d
to
the
plain
te
xt
with
a
64
-
bit
init
ia
l
key.
The
r
ow
-
t
o
col
um
n
trans
posit
ion
proces
s
rep
eat
e
d
twic
e
and
th
e
bit
per
m
utatio
n
process
re
pe
at
ed
on
ce
befor
e
pr
ov
i
ding
the
64
-
bit ci
ph
e
r
te
xt.
64
-
b
i
t
p
l
a
i
n
te
x
t
I
n
i
tia
l
k
ey
a
d
d
i
tio
n
N
o
n
l
i
n
e
a
r
s
u
b
s
t
i
t
u
t
i
o
n
Bi
t
p
e
r
mu
t
a
t
i
o
n
Ro
w
-
to
-
c
o
l
u
mn
t
r
a
n
s
p
o
s
i
t
i
o
n
K
e
y
a
d
d
i
t
i
o
n
Ro
w
t
o
c
o
l
u
mn
t
r
a
n
s
p
o
s
i
t
i
o
n
Bi
t
p
e
r
mu
t
a
t
i
o
n
Ro
w
t
o
c
o
l
u
mn
t
r
a
n
s
p
o
s
i
t
i
o
n
64
-
b
i
t
c
i
p
h
e
r
t
e
x
t
12
r
o
u
n
d
K
e
y
s
c
h
e
d
u
l
i
n
g
Us
e
r
ke
y
(
64
b
i
t
)
Evaluation Warning : The document was created with Spire.PDF for Python.
IS
S
N
:
2502
-
4752
Ind
on
esi
a
n
J
E
le
c Eng &
Co
m
p
Sci,
Vo
l.
23
, N
o.
3
,
Se
ptem
ber
20
21
:
16
74
-
16
80
1676
4.
VHDL I
M
PL
EMENT
ATION
OF
M
CRYPTO
N ALG
ORI
TH
M
The
top
m
od
ul
e
of
the
pro
po
s
ed
desig
n
is
show
n
in
Fig
ur
e
2.
The
desig
n
involve
s
three
input
ports
and
on
e
ou
t
pu
t
po
rt.
T
wo
of
the
input
ports
are
us
e
d
as
interface
po
rts
to
the
plainte
xt
64
-
bit
and
the
ke
y
64
-
bit
w
hile
t
he
thir
d
in
pu
t
port
is
us
e
d
as
1
-
bi
t
enab
le
to
the
syst
e
m
design
.
The
outp
ut
po
rt
is
re
pr
ese
nting
t
he
64
-
bit ci
ph
erte
xt.
The
re is no need
t
o
us
e a l
arg
e F
PGA bo
ard
si
nce th
e to
ta
l nu
m
ber
o
f
t
he
pi
ns
that wa
s u
sed
as in
pu
t/
outp
ut
is 19
3 on
ly
.
In
Fi
gure
3,
da
ta
flow
for
the
desi
gned
ha
rdwar
e
is
s
ho
wn.
Each
dif
f
eren
t
process
of
m
Crypton
al
gorithm
is
buil
t
as
sta
nd
al
one
com
po
ne
nt
a
nd
in
w
hich
t
he
plainte
xt
an
d
key
is
process
ed.
Twel
ve
r
ep
eat
ed
rou
nd
s
of
tran
sform
at
io
n
are
us
ed
to
buil
d
the
process
of
encr
y
ption.
Each
rou
nd
of
tr
ansfo
rm
ation
will
go
thr
ough all
the
four sta
ges
of t
he
al
go
rithm
[
22
].
Figure
2
.
To
p
m
od
ule of m
Crypton R
TL
Figure
3
.
The
data fl
ow of
th
e m
Crypton
4
.
1.
Nonli
near
Su
bs
tituti
on
In
t
his b
l
ock
a
4×
4 nip
ple ar
ra
y and
fou
r
S
-
boxe
s of size 4
-
bit (S
0,
S
1,
S2,
an
d S
3)
a
re us
ed
to
do the
process
of
nonl
inear
s
ubsti
tuti
on
as s
how
n
i
n (
1)
-
(
3).
S2 = S
0
-
1 a
nd
S3 = S
1
-
1
(1)
a = (a
0,
a1, a
2, a3)
(2)
γi(
a)
=
(Si(
a0
)
,
S
i+
1(a
1)
, S
i+
2(a
2)
, S
i+3(a
3)
)
(3)
The
s
ubsti
tuti
on
un
it
is
design
e
d
with
64
-
bit
for
input
and
64
-
bit
f
or
ou
tp
ut.
This
com
po
ne
nt
con
ta
in
s
64
L
UT
that
is
buil
t
with
the
RO
M
of
siz
e
16
*4
to
c
hange
va
lue
of
S
-
boxes
.
Fig
ur
e
4
s
hows
th
e
RTL o
f
s
ubsti
tuti
on co
m
pone
nt.
4
.
2.
Perm
uta
tion
To
buil
d
a
pe
r
m
uta
ti
on
proce
ss
a
hardw
i
re
s
tructu
re
is
us
e
d
rather
tha
n
bu
i
lding
it
with
a sh
ift
ci
rcu
it
that
increase
the
area
of
the
desig
n.
T
his
com
po
ne
nt
in
ve
ry
si
m
ple
arc
hitec
ture
us
i
ng
VH
D
L
an
d
the
sli
ce
nu
m
ber
is
ve
r
y
s
m
al
l
becau
s
e
it
bu
il
t
fr
om
hard
war
e
wiri
ng
t
o
tran
sfe
r
locat
ion
of
data
and
AND
gate
with
const
ant.
Fig
ure
5
s
how
s
t
he
num
ber
of
the
input/
outpu
t
buff
e
r
an
d
A
ND
gate
that
us
ed
t
o
bu
il
d
a
per
m
utati
on
operati
on in ha
rdwar
e
.
Evaluation Warning : The document was created with Spire.PDF for Python.
Ind
on
esi
a
n
J
E
le
c Eng &
Co
m
p
Sci
IS
S
N:
25
02
-
4752
Eff
ic
ie
nt h
ard
ware im
pleme
nt
ation
f
or
li
ght
we
igh
t
mCrypt
on a
l
gorit
hm usi
ng FP
GA
(
Y
asi
r Am
er
A
bbas
)
1677
Figure
4
.
RTL
su
bst
it
ution
c
om
po
nen
t
of m
Crypto
n
Figure
5
.
RTL
per
m
utati
on
c
om
po
nen
t
of m
Crypto
n
4
.
3
.
Row
-
to
-
c
olumn tr
an
sp
os
itio
n
Mov
i
ng
t
he nipp
le
s
with
(i,
j
)
locati
on
ad
dr
e
sses into
(j,
i)
locati
on addr
es
ses can
ea
sil
y pro
vid
e
row
-
to
-
c
olu
m
n
tran
sp
osi
ti
on
.
T
his
operati
on
did
no
t
c
os
t
t
he
ha
rdwar
e
de
sig
n
beca
use
the
ha
rd
wire
is
c
hange
th
e
locat
ion
of
4
-
bi
t fr
om
row
t
o colum
n
.
4
.
4
.
Ke
y
s
che
duli
ng
In
m
Crypton
,
the
key
sc
he
du
li
ng
al
gori
thm
inv
olv
es
two
operati
on
s
gen
e
rate
the
ro
un
d
key
op
e
rati
on
us
in
g
S
-
box
a
nd
update
the
key
var
ia
bles
with
ro
ta
ti
on
[
24
]
,
[
25
]
.
I
n
t
he
pro
po
s
ed
arc
hitec
ture
a
RAM
of
c
onst
ant
key
va
riab
le
s
is
us
ed
.
Th
e
nu
m
ber
of
ke
y
var
ia
bles
is
twel
ve
w
hich
is
equ
i
valent
to
the
rou
nd
nu
m
ber
of
t
he
tran
sf
orm
at
ion
s.
The
s
i
m
ple
arch
it
ect
ur
e
is
us
e
d
to
decr
eas
e
ha
rdwar
e
,
in
a
dd
it
ion
sam
e
com
po
ne
nt
us
ing
in
r
ound
is
us
e
d
is
par
t
.
Fi
gure
6
sho
w
s
t
he
S
-
Bo
x
an
d
XO
R
operati
on
t
hat
us
ed
in
the
fi
r
st
par
t
of
the
key
sche
du
li
ng c
om
po
nen
t.
Figure
6
.
RTL
key sc
hedulin
g com
po
ne
nt
of
m
Crypton
Evaluation Warning : The document was created with Spire.PDF for Python.
IS
S
N
:
2502
-
4752
Ind
on
esi
a
n
J
E
le
c Eng &
Co
m
p
Sci,
Vo
l.
23
, N
o.
3
,
Se
ptem
ber
20
21
:
16
74
-
16
80
1678
4
.
5
.
Ke
y
a
d
dition
It
is
the
proc
e
ss
of
a
ddin
g
t
he
resu
lt
of
a
n
r
2c
process
to
the
key
prov
i
ded
by
the
ke
y
sche
du
li
ng
process
. T
he pr
ocess o
f
a
dd
it
ion i
s a sim
ple b
it
to bit
x
-
or l
og
ic
operati
on.
5.
SIMULATI
O
NS
A
ND R
ES
ULTS
L
i
g
h
t
w
e
i
g
h
t
m
C
r
y
p
t
o
n
a
l
g
o
r
i
t
hm
s
w
e
r
e
d
e
s
i
g
n
e
d
a
n
d
t
e
s
t
e
d
u
s
i
n
g
X
i
l
i
n
x
I
S
E
s
o
f
t
w
a
r
e
,
v
e
r
s
i
o
n
1
4
.
5
a
n
d
a
l
l
s
i
m
u
l
a
t
i
o
n
s
h
a
ve
b
e
e
n
d
o
n
e
b
y
I
S
i
m
.
T
h
e
p
r
o
p
o
s
e
d
a
l
g
o
r
i
t
hm
h
a
s
b
e
e
n
d
e
s
i
g
n
e
d
w
i
t
h
V
H
D
L
l
a
n
g
u
a
g
e
.
U
s
i
n
g
I
S
i
m
,
t
he
V
H
D
L
c
o
d
e
s
w
e
r
e
a
n
a
l
y
z
e
d
a
n
d
s
y
n
t
h
e
s
i
z
e
d
,
p
l
a
c
e
d
a
n
d
r
o
u
t
e
d
i
n
F
P
G
A
d
e
v
i
c
e
s
S
p
a
r
t
a
n
3
-
x
c
3
s
1
0
0
0
-
5
f
g
3
2
0
.
D
i
f
f
e
r
e
n
t
p
e
r
f
o
r
m
a
n
c
e
m
e
t
r
i
c
s
s
u
c
h
a
s
t
h
e
a
r
e
a
,
t
h
r
o
u
g
h
p
u
t
a
n
d
p
o
w
e
r
w
e
r
e
c
om
p
u
t
e
d.
The
low
la
te
ncy
an
d
lo
w
ha
rdware
i
m
ple
m
entat
i
on
are
the
ta
rget
of
the
desi
gn
pr
ese
nted
in
this
pa
per.
T
he
total
sli
ces 375, the
m
Crypton
c
ons
ist
f
r
om
a
dd
c
onsta
nt
64 sli
ces
,
key s
che
duli
ng
64
sli
ces, the
r
ou
nd that c
on
sist
s
from
(
su
bst
it
ution
,
pe
rm
utati
on
,
t
ran
s
fer
a
nd ad
d
co
ns
ta
nt
)
96
sli
ces,
s
ubsti
tuti
on
ha
s
on
ly
been
32,
fi
nally
the
per
m
utati
on
a
nd R
ow
t
o
C
olum
ns
tran
sfe
r
in
v
e
ry sm
all b
ec
ause it
is
hard
war
e
w
ire
only
.
T
h
e
h
a
r
d
w
a
r
e
i
m
p
l
e
m
e
n
t
a
t
i
o
n
h
a
s
b
e
e
n
t
e
s
t
e
d
u
s
i
n
g
I
S
i
m
s
i
m
u
l
a
t
i
o
n
s
o
f
t
w
a
r
e
.
A
t
e
s
t
v
e
c
t
o
r
s
f
o
r
t
h
e
p
l
a
i
n
t
e
x
t
6
4
-
b
i
t
a
n
d
t
h
e
k
e
y
6
4
-
b
i
t
e
n
t
e
r
t
h
e
d
e
s
i
g
n
e
d
s
y
s
t
e
m
a
s
i
n
p
u
t
s
.
T
h
e
p
r
o
c
e
s
s
i
n
g
o
f
t
h
e
i
n
p
u
t
s
w
i
t
h
t
h
e
d
i
f
f
e
r
e
n
t
c
o
m
p
o
n
e
n
t
s
o
f
t
h
e
p
r
o
p
o
s
e
d
d
e
s
i
g
n
a
n
d
p
r
o
d
u
c
i
n
g
t
h
e
c
i
p
h
e
r
t
e
x
t
i
s
t
a
k
i
n
g
3
0
c
l
o
c
k
c
y
c
l
e
s
.
F
i
g
u
r
e
7
s
h
o
w
s
t
h
e
s
i
m
u
l
a
t
i
o
n
r
e
s
u
l
t
s
o
f
t
h
e
l
a
s
t
r
o
u
n
d
o
f
d
a
t
a
e
n
t
e
r
e
d
in
t
o
t
h
e
d
e
s
i
g
n
e
d
s
y
s
t
e
m
a
n
d
t
h
e
l
a
s
t
t
h
r
e
e
c
o
m
p
o
n
e
n
t
s
.
T
h
e
p
r
o
p
o
s
e
d
a
r
c
h
i
t
e
c
t
u
r
e
h
a
s
b
e
e
n
p
r
o
v
e
d
t
o
b
e
e
f
f
i
c
i
e
n
t
f
o
r
w
o
r
k
i
n
g
w
i
t
h
h
i
g
h
f
r
e
q
u
e
n
c
y
a
n
d
h
i
gh
t
h
r
o
u
g
h
p
u
t
u
s
i
n
g
a
s
m
a
l
l
n
u
m
b
e
r
o
f
s
l
i
c
e
s
.
T
h
e
s
l
i
c
e
n
u
m
b
e
r
i
s
r
e
d
u
c
e
d
i
n
s
h
i
f
t
o
p
e
r
a
t
i
o
n
b
y
u
s
i
n
g
L
U
T
t
e
c
h
n
i
q
u
e
.
L
U
T
u
s
e
s
t
h
e
c
h
a
n
g
e
o
f
l
o
c
a
t
i
o
n
s
b
e
t
w
e
e
n
i
n
p
u
t
a
n
d
o
u
t
p
u
t
d
a
t
a
t
o
a
c
h
i
e
v
e
t
h
e
s
h
i
f
t
o
p
e
r
a
t
i
o
n
.
T
h
e
s
h
i
f
t
o
p
e
r
a
t
i
o
n
t
h
a
t
i
s
b
u
i
l
t
w
i
t
h
L
U
T
c
o
u
l
d
b
e
e
x
e
c
u
t
e
d
i
n
o
n
e
c
l
o
c
k
c
y
c
l
e
.
U
s
i
n
g
a
s
m
a
l
l
n
u
m
b
e
r
o
f
s
l
i
c
e
s
c
a
n
r
e
d
u
c
e
t
h
e
c
o
s
t
o
f
d
e
s
i
g
n
a
n
d
m
a
k
e
t
h
e
p
r
o
p
o
s
e
d
d
e
s
i
g
n
s
u
i
t
a
b
l
e
t
o
b
e
u
s
e
d
w
i
t
h
R
F
I
D
d
e
v
i
c
e
s
a
n
d
I
o
T
a
p
p
l
i
c
a
t
i
o
n
.
A
c
om
par
at
ive
of
a
rea
(total
nu
m
ber
of
sli
c
es),
powe
r
(m
Watt
),
a
nd
t
hr
ough
pu
t
(M
bp
s
)
we
re
s
how
n
in
Fig
ur
es
8,
9,
and
10
res
pect
ively
.
The
pro
po
s
ed
a
rch
it
ect
ur
e
resu
lt
s,
s
ho
w
go
od
t
hroug
hput
with
sm
al
l
area
and
lo
w
po
we
r
co
ns
um
ption
as
it
is
sh
own
in
Table
1.
R
esults
hav
e
be
en
com
par
ed
with
dif
fer
e
nt
stud
ie
s.
The
res
ults
of
t
he
propose
d
de
sign
e
d
sho
w
a
thr
ough
pu
t
of
646
Mb
ps
a
nd
e
ff
ic
ie
ncy
of
1.
7
Mb
ps
/sl
ic
e
with
total
p
owe
r
e
qual
to 8
9
m
W
a
tt
o
nly.
Figure
7
.
The
te
st vecto
r
sim
ulati
on
of m
Crypto
n
Figure
8
.
Total
num
ber
of slic
es r
es
ults
Figure
9
.
P
ow
e
r
(m
W
at
t)
res
ul
ts
Evaluation Warning : The document was created with Spire.PDF for Python.
Ind
on
esi
a
n
J
E
le
c Eng &
Co
m
p
Sci
IS
S
N:
25
02
-
4752
Eff
ic
ie
nt h
ard
ware im
pleme
nt
ation
f
or
li
ght
we
igh
t
mCrypt
on a
l
gorit
hm usi
ng FP
GA
(
Y
asi
r Am
er
A
bbas
)
1679
Figure
10
.
T
hr
oughput
(Mb
ps) r
e
su
lt
s
Table
1.
Per
for
m
ance
c
om
par
isons
of
mC
ryp
ton
with
previ
ous st
ud
ie
s
Alg
o
rith
m
Blo
ck
Size
Dev
ice
Max
Freq.
(M
Hz
)
Thr/p
u
t
(M
b
p
s)
Total
Slices
Ef
f
icien
cy
(M
b
p
s/Slice)
Po
wer
(
m
W
att
)
Prop
o
sed
m
C
ry
p
to
n
64
Sp
artan
-
II
I
302
646
375
1
.7
89
[
1
7
]
64
Virtex
-
4
FF6
6
8
3
1
.76
5
2032
956
2
.12
6
165
[
1
8
]
64
XC7
Z01
0
clq
2
2
5
-
3
2
6
6
.29
1280
521
2
.45
170
[
1
9
]
64
Xilin
x
Z
y
n
q
-
7000
-
854
471
1
.8
251
[
2
0
]
64
Xilin
x
Spartan
-
3
8
1
.82
1
6
8
.9
397
0
.42
5
-
6.
CONCL
US
I
O
N
In
this
pa
per,
eff
ic
ie
nt
ha
rdwar
e
arc
hitec
ture
f
or
the
m
C
rypto
n
li
gh
t
we
igh
t
enc
ryptio
n
al
gorithm
is
introd
uced.
T
he
pro
po
se
d
a
r
chite
ct
ur
e
pro
vid
e
s
a
n
op
ti
m
iz
at
ion
to
th
e
area
an
d
po
wer
c
onsu
m
ption
.
T
he
resou
rce
-
s
har
e
d
str
uctu
re
has
a
good
im
pact
on
a
rea
re
duct
ion
.
All
com
po
ne
nts
are
desi
gn
e
d
to
operat
e
in
a
sing
le
cl
oc
k
cy
cl
e
and
a
fe
w
nu
m
ber
s
of
sli
ces.
T
he
im
ple
m
entat
ion
res
ul
ts
us
ing
the
S
par
ta
n
-
3X
il
in
x
FPGA
platfo
rm
pr
esented
that
on
ly
375
sli
ces
are
require
d
to
a
chieve
302
M
Hz
of
ope
rati
ng
f
reque
ncy
w
i
th
89
m
W
at
t
power
consum
ption
.
Fu
rt
her,
a
thr
ough
pu
t
of
646
Mbp
s
an
d
ef
fici
ency
of
1.7
M
bp
s/sl
ic
e
is
a
ch
ie
ved.
Th
us
, t
he ob
ta
i
ned res
ults
pro
ved that t
he
propose
d
a
rch
it
e
ct
ur
e is
su
it
abl
e f
or
sm
all an
d m
ob
il
e d
evice
s.
REFERE
NCE
S
[1]
S.
Atie
wi
et
al
.
,
"S
ca
la
bl
e
and
Secur
e
Big
Da
ta
I
oT
S
y
st
em
Base
d
on
Multi
f
actor
Authent
i
cation
and
L
ight
weigh
t
Cr
y
ptogr
aph
y
,
"
i
n
IEEE Access
,
vol.
8
,
pp
.
11349
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-
113511,
2020
,
doi: 10.
1109
/ACCESS
.
2020.
3002815
.
[2]
A.
Shah
and
M
.
Engi
n
ee
r
,
“
A
Surve
y
of
Li
ght
weight
Cr
y
ptogr
aphi
c
Algor
it
hm
s
for
IoT
-
Based
Applic
a
ti
ons,
”
Springer
,
Singap
ore
,
2019
,
v
ol. 6
69,
pp
.
283
-
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[3]
D.
Yang,
W
.
-
F.
Qi,
and
H.
-
J.
Chen,
“
Obs
erv
at
ions
on
the
trunc
ated
diffe
r
ent
i
al
of
SP
bloc
k
ci
pher
s
and
thei
r
appl
i
ca
t
ions
to
m
Cry
p
ton
and
C
RYP
TON
V1.0,
”
IET
Informatio
n
Sec
urit
y
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vo
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no.
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017.
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[4]
T.
Ei
senb
art
h
,
S.
Kum
ar,
C.
Paar
,
A.
Pos
chmann
and
L.
Uhs
ade
l,
"A
Surve
y
of
L
ight
we
ight
-
Cr
y
ptogr
ap
h
y
Im
ple
m
ent
at
ions
,
"
in
I
EE
E
Des
ign
&
Test
of
Computers
,
vol.
24,
no
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6
,
pp.
522
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-
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.
2007
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i
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2
007.
178
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[5]
V.
A.
Tha
kor,
M.
A.
Raz
za
qu
e
and
M.
R.
A.
Khanda
ker
,
"Lig
htwei
ght
Cr
y
pto
gra
ph
y
Algori
th
m
s
for
Resourc
e
-
Constrai
ned
IoT
Devic
es:
A
Rev
ie
w,
Com
par
ison
and
Resea
rch
Opportunit
ie
s
,
"
in
IEE
E
A
cc
ess
,
vol.
9,
pp.
2817
7
-
28193,
2021
,
doi
:
10.
1109
/ACCE
SS
.
2021.
3052867
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[6]
H.
Tong,
J.
Hua
ng,
and
C.
Qi,
“
A
Novel
L
ight
w
ei
ght
Cr
y
p
tograph
y
Sch
eme
Ba
sed
on
Stand
ard
iz
ed
IOT
Dat
a,”
Proce
ed
ings
of
t
he
2020
Int
ernati
onal
Conf
ere
nc
e
on
Cyb
erspace
Innov
ati
on
o
f
A
dvanc
ed
Te
chno
logi
es
,
2020
,
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.
379
-
386,
doi
:
10
.
1145/3444370.
3
444601.
[7]
L.
Ning,
Y
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MCD
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App
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Li
ghtwe
igh
t
Cr
y
ptogr
aphic
Ciphe
r
Based
on
ISO
and
NI
ST
Li
ghtwei
gh
t
Cr
y
ptogra
ph
y
Se
cur
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R
equi
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e
RF
ID
C
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m
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W
it
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P
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h
m
a
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a
n
d
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P
a
a
r
,
"
D
e
s
i
g
n
s
p
a
c
e
e
x
p
l
o
r
a
t
i
o
n
o
f
p
r
e
s
e
n
t
i
m
p
l
e
m
e
n
t
a
t
i
o
n
s
f
o
r
F
P
G
A
S
,
"
2
0
0
9
5
t
h
S
o
u
t
h
e
r
n
C
o
n
f
e
r
e
n
c
e
o
n
P
r
o
g
r
a
m
m
a
b
l
e
L
o
g
i
c
(
S
P
L
)
,
2
0
0
9
,
p
p
.
1
4
1
-
1
4
5
,
d
o
i
:
1
0
.
1
1
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PG
A
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IC
EBE
R
G
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k
c
iphe
r
,
"
Inte
rnational
C
onfe
renc
e
on
In
f
orm
ati
on
Techn
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:
Coding
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ITCC
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o
m
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c
t
F
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G
A
I
m
p
l
e
m
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n
t
a
t
i
o
n
o
f
t
h
e
A
E
S
A
l
g
o
r
i
t
h
m
,
”
i
n
I
n
t
e
r
n
a
t
i
o
n
a
l
w
o
r
k
s
h
o
p
o
n
c
r
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p
t
o
g
r
a
p
h
i
c
h
a
r
d
w
a
r
e
a
n
d
e
m
b
e
d
d
e
d
s
y
s
t
e
m
s
,
S
p
r
i
n
g
e
r
,
2
0
0
3
,
p
p
.
3
1
9
-
3
3
3
,
d
o
i
:
1
0
.
1
0
0
7
/
9
7
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-
3
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Y.
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“
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INCE
I
P
-
Co
re
on
F
ie
ld
Program
m
abl
e
Gate
Arra
y
s
(FP
GA
),
”
Re
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Jour
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of
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ie
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ur
i
t
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i
ca
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chi
t
ec
tur
es
for
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i
abl
e
and
f
aul
t
det
ection
Sim
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Speck
cr
y
pt
ogra
phic
a
lgori
t
hm
s
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FPGA,
"
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ightw
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t
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o
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k
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GA
,
"
2020
5t
h
Inte
rnational
Confe
renc
e
on
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anc
ed
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ologi
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ss
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A
.
A
l
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a
r
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d
N
.
R
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O
b
e
i
d
.
"
E
f
f
i
c
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e
n
t
I
m
p
l
e
m
e
n
t
a
t
i
o
n
f
o
r
P
R
I
N
C
E
A
l
g
o
r
i
t
h
m
i
n
F
P
G
A
B
a
s
e
d
o
n
t
h
e
B
B
8
4
P
r
o
t
o
c
o
l
,
"
J
o
u
r
n
a
l
o
f
P
h
y
s
i
c
s
:
C
o
n
f
e
r
e
n
c
e
S
e
r
i
e
s
,
v
o
l
.
1
8
1
8
,
n
o
.
1
,
p
p
.
0
1
2
2
1
6
,
20
2
1
,
d
o
i
:
1
0
.
1
0
8
8
/
1
7
4
2
-
6
5
9
6
/
1
8
1
8
/
1
/
0
1
2
2
1
6
.
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H.
Li
m
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.
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“
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pton
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L
ig
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gh
t
Blo
ck
Ciphe
r
for
Secur
ity
of
Low
-
Cost
RF
ID
Ta
gs
and
Sensors
,
”
in
Info
rm
ati
on
Sec
uri
ty A
ppl
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li
an
,
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ta
n
aly
s
i
s
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m
Cry
p
ton
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Inte
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nal
Journal
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t
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Cr
y
p
to
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and
LE
D
aga
i
nst
bic
li
qu
e
c
r
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ta
na
l
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"
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,
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“
Cr
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ta
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sis
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m
Cry
pton
-
A
li
gh
twe
ight
bloc
k
ci
ph
e
r
for
sec
urity
of
RF
ID
ta
gs
and
sensors
,
”
Int
ernat
ional
Journal
o
f
Comm
unic
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on
Syste
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