TELKOM
NIKA Indonesia
n
Journal of
Electrical En
gineering
Vol. 14, No. 3, June 20
15, pp. 481 ~ 4
9
2
DOI: 10.115
9
1
/telkomni
ka.
v
14i3.794
9
481
Re
cei
v
ed Fe
brua
ry 17, 20
15; Re
vised
Ap
ril 29, 201
5; Acce
pted
May 15, 20
15
Comparative St
udy of a Three Phase Cascad
ed H-
Bridge Multilevel Inverter for Harmonic Reduction
Rosli Omar*
1
,
Mohammed
Rashe
e
d
2
, Mariz
a
n Sulaiman
3
, M. R
Tamijis
4
Univers
i
ti T
e
knikal Mal
a
ysi
a
Melak
a
, F
a
culty of
Electric
al
Engi
neer
in
g, Industria
l Po
w
e
r,
7610
0 Ha
ng
T
uah Ja
y
a
, Du
rian T
ungg
al, Melak
a
, Mala
ysia.
*Corres
p
o
ndi
n
g
author, e-ma
i
l
: rosliomar
@
ut
em.edu.m
y
1
, moham
ed_tc
hno
@
y
ah
oo.com
2
,
marizan
@
utem
.edu.m
y
3
, moh
a
madr
om@ute
m.edu.m
y
4
A
b
st
r
a
ct
T
he ai
m
of thi
s
researc
h
pr
oject is t
o
a
n
a
l
y
z
e
a
nd
desi
gn of
ener
gy
storages in el
ectrica
l
distrib
u
tion sy
stem. In this
pap
er pr
esent
s a co
mp
arati
v
e study
bet
w
een sin
u
so
id
al p
u
lse
w
i
dth
mo
du
latio
n
(S
PWM) and spa
c
e vector pu
lse
w
i
dth
mo
dul
ati
on (SVPWM) techn
i
qu
e, bas
ed o
n
ge
nerat
e
sign
al five l
e
v
e
l of casca
de
d H-bri
dge for
reducti
o
n
har
mo
nics i
n
the
multi
l
ev
el i
n
v
e
rter outp
u
t. A
mu
ltilev
e
l i
n
ver
t
er is a preferr
e
d cho
i
ce for
most me
di
um-v
ol
tage a
nd h
i
g
h
-
pow
er ap
plic
ati
ons, as w
e
ll as
cascad
ed H-
bri
dge (C
HB) five
-level
inverters
due to it
s adv
antag
es such
as low
cost, lig
ht w
e
ight an
d
compact si
z
e
. It is suitable par
ticularly for use
in a ca
scade
d
H-bridg
e
multil
evel inv
e
rter d
ue to reduc
e
d
total har
mo
nic
distortio
n
(T
HD
). Harmo
n
ic co
ntent in
thre
e p
hase
mu
ltilev
e
l
invert
er can
b
e
investi
gate
d
by ge
nerati
ng
(SPWM) and (
SVPWM) algo
rithm s
i
g
nal
b
a
sed
on
a fiv
e
-lev
el (CH
B
). The pro
pos
e
d
system is d
e
si
gne
d usi
ng MA
TLAB/SIMULINK consists
of cascad
ed H-br
i
dge (C
HB) mul
t
ilevel i
n
verter.
Ke
y
w
ords
:
Cascaded H-bridge (CHB), SVPWM, SPWM,
total har
monic
distortion (THD).
Copy
right
©
2015 In
stitu
t
e o
f
Ad
van
ced
En
g
i
n
eerin
g and
Scien
ce. All
rig
h
t
s reser
ve
d
.
1. Introduc
tion
The develop
ment
of po
we
r
el
ectroni
cs and
i
n
crea
se
d po
we
rs inv
o
lved a
nd th
e
flexibility
of the use of semi
con
d
u
c
tors h
a
s el
ectrician
s
en
cou
r
aged to und
e
r
take
signifi
cant asso
ciations
of static
co
n
v
erters po
we
r to ele
c
tri
c
machi
n
e
s
A
multilevel inverter i
s
a p
r
e
f
erre
d choi
ce
for
most mediu
m
-voltage an
d high-po
wer a
pplication
s
, as well a
s
ca
scad
ed H-bri
d
ge (CHB) two-
level inverte
r
s du
e to its advantag
es su
ch a
s
l
o
wer commo
n
-
mod
e
voltag
e, lowe
r
/
dv
dt
,
redu
ce
d total
harm
oni
c di
stortion
(T
HD) i
n
output
volta
ge current a
n
d
re
du
ced vol
t
age on
po
we
r
swit
chin
g for a gen
eral
ci
rcuit of 5
-
lev
e
l ca
scad
ed
H-b
r
id
ge inv
e
rter [1]. Co
nverting a
st
atic
stru
cture tha
t
comp
rises
mainly appli
c
ations
of po
wer
ele
c
troni
c is
becomi
ng in
cre
a
si
n
g
ly
importa
nt for po
we
r of th
e topol
ogy. It ha
s to
ad
ap
t to the
gro
w
th of the
po
wer to
co
nve
r
t a
multilevel inverter, fo
r exa
m
ple three to
pology
ca
sca
ded
H-b
r
id
ge
(CHB), dio
d
e
clam
ped
(NPC)
and flying Ca
pacito
r
(F
C) [
2
] Cells
with sep
a
rate
d DC so
urce
s sh
own in Fig
u
re
1.
Figure 1.
Top
o
logie
s
of Mu
ltilevel Inverter, (a)
Ca
scad
ed H-B
r
idg
e
(CHB
),
(b)
Diod
e Cla
m
ped (NPC), (c
) Flying Ca
pacito
r
(F
C)
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 23
02-4
046
TELKOM
NI
KA
Vol. 14, No. 3, June 20
15 : 481 – 49
2
482
Our jo
b is to
the Implementation of tech
nical SPWM which is to minimize
the rate
harm
oni
cs
(T
HD) of the
o
u
tput wave [3
]. The perfo
rmance of the
inverter, fo
r
any wh
at co
n
t
rol
strategy
rel
a
ted to
co
nten
t harm
oni
cs
of its
o
u
tput
voltage. A l
o
t of techniq
ues have
be
en
studie
d
to re
duce ha
rmo
n
i
cs. Pul
s
e
wid
t
h modul
ation
(PWM
) te
ch
nique
gives t
he effect
on t
h
e
swit
chin
g lo
sse
s
inve
rter,
harm
oni
c con
t
ents in the
o
u
tput wavefo
rm, and ove
r
al
l perfo
rman
ce
of
the inverte
r
[4, 5]. Sinuso
i
dal PWM
(SPWM) i
s
an
effective method to red
u
ce lo
we
r o
r
der
harm
oni
cs
while varying
the outp
u
t voltage In
cont
ra
st, Phase Di
spositio
n (P
D) modulatio
n o
f
a
CHB i
s
h
a
rm
onically high
quality due
to
dire
ct ha
rmo
n
ic e
n
e
r
gy alt
ogethe
r
with
carrie
r h
a
rm
o
n
ic.
In ca
se
of th
e thre
e-pha
se inverte
r
, th
e ratio
of the
fundame
n
tal
comp
one
nt of
the utmo
st li
ne-
to-line voltag
e to the direct supply voltage is
86.6%
[6]. Space vector p
u
lse width mod
u
la
tion
algorith
m
(S
VPWM) is
a more attracti
ve candi
date
and its adva
n
tage is the
six se
ctor vol
t
age
16
VV
that ope
rate
s sta
r
ting fro
m
each
switching ve
ctor a
s
a p
o
int in
complex (
,
) sp
ace
and con
s
ist
s
of six secto
r
s, with each ha
ving
an angl
e
of 60 degre
e
as sh
own in Figure 2 [7, 8].
Figure 2. Sp
ace ve
ctor di
agra
m
for a two-l
e
vel inverter
Each secto
r
consi
s
ts of
2
1
n
triangle. SVPWM diagram of an n-level inverter consi
s
t
s
of 125 five-le
v
el, [9]. In this pa
per presents a
co
mpa
r
ative stu
d
y b
e
twee
n si
nu
soidal p
u
lse wi
dth
modulation (SPWM) and
space ve
ctor pulse wi
dth
modulation
(SVPWM) techni
que, based on
gene
rate
sign
al five level of casca
ded
H-bridg
e
fo
r red
u
ction h
a
rm
o
n
ics in the m
u
ltilevel inverter
output. Th
e a
i
m of thi
s
stu
d
y is to
impl
ement
th
e
ca
rrie
r
frequ
en
cy paramete
r
with m
odulati
on
index for
achieving the l
o
w h
a
rm
oni
c disto
r
tion.
Harmo
n
ic
co
ntent in three
pha
se m
u
ltilevel
inverter can
be investigat
ed by
generating (SP
W
M)
and
(SVPWM
)
algorithm
si
gnal
based on a
five-level (CHB). The p
r
opo
sed
syst
em is
de
sig
ned u
s
ing M
A
TLAB/SIMULINK con
s
i
s
ts of
ca
scade
d H-bridg
e
(CHB
) multilevel inverter.
2. Multile
v
e
l
In
v
e
rter
The Con
c
ept
s of multileve
l inverters (M
LI) dep
end
s
not only on t
w
o voltag
e le
vels to
cre
a
te th
e A
C
sign
al. Inst
ead, it i
s
a
d
d
ed to
mo
st le
vels of volta
g
e
to the
othe
r to cre
a
te a
form
of reinfo
rced
smooth
wave
, with a
lo
w d
v
/dt and le
ss
harm
oni
c di
st
ortion [1
0]. With more in
th
e
inverter volta
ge level
s
it creates
a sm
oo
ther wa
veform become
s
,
but with ma
n
y
levels of de
sign
become
s
m
o
re
com
p
lex,
with mo
re
compon
ents a
nd mu
st
be
more
comple
x cont
rolle
r f
o
r
inverter [11]. The multilevel inverters diagram
s
Fi
g
u
re
3. Illustrate
s
of the inverte
r
s h
a
ve be
en
2-
level inverter, 3-level
invert
er, an
d the
N-level inve
rter. All the capa
citors in
clu
d
e
to a voltag
e
of
Vdc
.
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
2302-4
046
Com
parative
Study of a Th
ree Pha
s
e
Ca
scade
d H-
B
r
i
dge Multile
vel
Inverte
r
for…
(Ro
s
li Om
ar)
483
Figure 3. Output Voltage o
f
(a) 2 Level
s Inverter (b
) 3
Levels Invert
er (c) 5 level
s
Inverters [12]
3. Pulse Width Modula
t
io
n (PWM
) Tec
hniques
In the e
a
rly
1970
s, the
majority of P
W
M
inve
rters u
s
in
g te
ch
nique
s
ba
se
d on
the
sampli
ng m
e
thod. Sinu
soid
al pul
se
width
modul
ati
on o
f
the primitive
techni
que
s,
whi
c
h a
r
e
used
to su
pp
re
ss the h
a
rm
oni
cs, pre
s
e
n
t in
a
qua
si-s
q
u
a
r
e
wave.
Over the yea
r
s, he
has devel
ope
d
techni
cal PWM whe
r
e the obje
c
tives we
re to im
prove
perfo
rman
ce,
simplify PWM strategi
es
and
appli
c
ation
s
of microp
ro
ce
ssors l
a
ter, to
produ
ce
a re
ductio
n
of ha
rmoni
c disto
r
tion
a
nd red
u
c
e
swit
chin
g losse
s
[7]. Has been exten
ded to seve
ral prin
ciple
s
sup
port level
s
ba
sed PWM
technology as a m
eans of
cont
rolling the active
dev
ices in a mul
t
ileve
l converter. PWM three
techni
que
s commonly u
s
e
d
are
-
the sin
u
soi
dal PWM
technol
ogy [8].
1) Hig
h
-q
ualif
y utilization of a DC po
wer
sup
p
ly
that is to deliver a higher o
u
tput voltage
with the s
a
me DC
s
u
pply.
2)
Goo
d
linea
rity in voltage and/ or curre
n
t control.
3)
L
o
w ha
rm
onic content
s in the
output
voltage a
nd /or
current
s, esp
e
ci
ally
in the
lo
w-
freque
ncy reg
i
on.
3.1. Sinusoidal Pulse-Wi
dth Modula
t
i
on (SPWM
)
Control te
chn
o
logy is the
most p
opul
ar
met
hod of
pul
se width
m
o
d
u
lation sine
a
dapter’
s
two traditio
n
a
l
levels. The t
e
m sin
u
soidal
PWM
refe
re
nce i
s
ma
de t
o
the produ
cti
on of the PWM
output signal
with
a sin
e
wave
a
s
a
m
o
dulation
sig
n
a
l [10]. The
o
n
and
off in
stants
of a P
W
M
signal ill thi
s
case,
can be det
ermined
by comparing the sinuso
i
dal signal (w
ave modulati
on)
with a tri
ang
ular
wave f
r
eque
ncy
(carrier
wave
),
as
sho
w
n
in
Figure 4
si
nusoidal P
W
M
techn
o
logy i
s
com
m
only u
s
ed i
n
in
du
strial a
pp
licatio
ns a
nd
abb
reviated he
re
as SP
WM [1
1].
Freq
uen
cy o
f
the mo
dul
ating
wave
determi
ne
s t
he fre
que
ncy
of the
outp
u
t voltage.
The
enlargem
ent
of the hei
g
h
t of the m
odulatio
n
ind
e
x of the waveform a
n
d
determi
ne
s the
comp
ositio
n turn control the RMS
value
of the output voltage [12].
Figure 4. Sinusoi
dal Pulse
Width M
odul
ation for thre
e-ph
ase inverter
The
RMS val
ue of th
e o
u
tput voltage
can b
e
vari
ed
by ch
angin
g
t
he mo
dulatio
n ind
e
x.
The o
u
tput v
o
ltage
of the i
n
verter
contai
ns
harmoni
cs. Ho
wever,
to
be
paid
for t
he h
a
rm
oni
cs of
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 23
02-4
046
TELKOM
NI
KA
Vol. 14, No. 3, June 20
15 : 481 – 49
2
484
the band
aro
und the
carri
e
r freq
uen
cy
and its
comp
l
i
cation
s [13]. To perfo
rm
si
nusoidal P
W
M
usin
g analo
g
circuit, use a
seri
es of b
r
icks:
1) Hig
h
-frequ
ency trian
gul
ar wave g
ene
rator.
2) Sine wave gene
rato
r.
3) Co
mpa
r
ato
r
.
4) Inverte
r
ci
rcuits
with de
a
d
-ba
nd g
ene
rator to ge
nerate com
p
lime
n
tary driving
Signals
with req
u
ired
dead b
and.
3.2. Space Vector Pulse-
Width Mo
dulation (SVPWM)
Harmoni
c co
ntent
in multi
l
evel
inverte
r
s ca
n
be
inv
e
stigate
d
by
gene
rating
a
sp
ace
vector
pul
se width
modulation algorit
h
m (
SVPWM
)
si
gnal
based on
a standard
two-level
SVPWM. It
uses a
simpl
e
mappi
ng t
o
generate
gating si
gnal
s for the inverter. The
ci
rcuit
stru
cture and
switching st
ates of
a five-level casca
ded H-b
r
idge
inverter are introdu
ce
d. The
swit
chin
g inst
ant of a SVPWM pul
se wa
veform is sho
w
n in Figu
re
6.
Figure 5. Switc
h
ing ins
t
ant
of a SVPWM pulse waveform
The pro
p
o
s
e
d
modulatio
n
is compa
r
e
d
in five-level
ca
scade
d inverter to re
du
ce high
total harmo
ni
c disto
r
tion, a
nd red
u
ce co
st based on
fi
ve-level ca
scaded
H-b
r
idg
e
that con
s
ist
s
of
four loo
k
up ta
ble 24 switchi
ng one DC so
urce inve
rte
r
s. Space vecto
r
modul
ation (SVM) for five-
level inverter consist
s
of
16 triangles, in wh
i
c
h tria
ngle on
e ha
s 13 switchi
n
g
states ve
cto
r
s,
triangle two-f
our have 1
0
switching
states vect
o
r
s, triangle three ha
s 11 switchi
ng stat
es
vectors, trian
g
le five-seve
n
-nin
e have
7 swit
ch
in
g states ve
ctors, tr
iangle
si
x-eight have
8
swit
chin
g
sta
t
es ve
ctors, t
r
iangl
e ten
-
t
w
elve-fo
u
rte
e
n
-
sixteen
ha
ve 4
switchin
g state
s
vect
ors
and
t
r
iangl
e eleven-thi
r
tee
n
-fifteen hav
e
5 switchi
n
g
state
s
ve
ctors [13]. A
s
sh
own
in
Figu
re 6.
The alg
o
rith
m can b
e
ea
sily extended to an O
N
-lev
e
l
inverter. Its
appli
c
ation i
s
for ca
scad
ed
H-
bridg
e
topolo
g
y as well.
Figure 6. Space vecto
r
dia
g
ram fo
r five-level inverter [
10]
0
0.
01
0.
02
0.0
3
0.
0
4
0.
05
0.
06
0.
07
0.0
8
0.
09
-0
.
8
-0
.
6
-0
.
4
-0
.
2
0
0.
2
0.
4
0.
6
0.
8
Ti
m
e
(
S
)
P
h
a
s
e V
o
l
t
a
g
e(
V
)
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
2302-4
046
Com
parative
Study of a Th
ree Pha
s
e
Ca
scade
d H-
B
r
i
dge Multile
vel
Inverte
r
for…
(Ro
s
li Om
ar)
485
4. Proposed
Design o
f
Sw
i
t
ching Mo
dulation
4.1. Sinusoidal Pulse Width Modula
t
i
on (SPWM
)
The gen
erations of gatin
g
signal
s with
sinu
soi
d
al Pu
lse Wi
dth Mo
dulation SP
WM are
sho
w
n in
Fig
u
re a. the
r
e
are
sinu
soi
d
al refe
ren
c
e
wave
s (
)
ea
ch shifted by
120
0
. A carri
e
r wave i
s
comp
ared wi
th the refere
nce
sign
al correspon
ding
to a phase
to
gene
rate
th
e gating sig
nal for
that pha
se.
Co
mpa
r
ing
the ca
rrie
r si
gnal with
th
e referen
c
e ph
ase
prod
uces
,
and
respe
c
tively as sh
own in
Figure b. the instantan
e
o
u
s
line-to
-line
o
u
tput voltage
is
the outp
ut voltage a
s
sho
w
n i
n
Figure
c, is
gene
rated by
eliminating t
he co
ndition
that tw
o switching d
e
vices in the
sa
me arm
can
not
con
d
u
c
t at the sa
me time.
The n
o
rm
ali
z
ed
ca
rri
er freque
n
cy
sho
u
l
d be o
d
d m
u
ltiple of thre
e.
Thus,
all ph
a
s
e-volta
ge
(
)
are i
denti
c
al
, but 120
0
o
u
t
of phase
wi
thout even
harm
oni
cs;
more
over h
a
rmonics at fre
quen
cy mult
i
p
le of thre
e
are id
entical
in amplitud
e
an
d
pha
se in all p
hase. For in
stance, if
the ninth harm
oni
cs voltage in p
hase
a
is:
(1)
The co
rrespo
nding ni
nth h
a
rmo
n
ics in p
hase
b
will be:
9
˜
9
s
i
n
9
120
)
˜
9
s
i
n
9
1080
)
˜9
s
i
n
9
aN
tw
t
w
t
wt
(2)
Thus, the a
c
output line vo
ltage
doe
s n
o
t contain th
e
ninth harmo
nics
.
Therefore, fo
r odd multiple
s of thre
e times t
he n
o
rm
a
lized
ca
rrie
r
frequ
en
cy
, the harmo
nics
in the ac
o
u
tput voltage
appea
r at
nor
m
a
lized freque
ncy
c
ent
ered
around
and its
multiple, specifically, at:
(3)
(4)
Figure 7. Simulink Five Lev
el of control
si
gnal Cascad
ed H-B
r
idg
e
Multilevel Inverter
,
ra
rb
rc
an
d
,
ra
rb
rc
and
1
g
2
g
5
g
13
ab
Vs
g
g
cf
,
aN
bN
cN
an
d
9
˜9
s
i
n
9
aN
tw
t
ab
aN
bN
mf
f
hm
f
nj
m
f
k
1
nj
m
f
k
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ISSN: 23
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046
TELKOM
NI
KA
Vol. 14, No. 3, June 20
15 : 481 – 49
2
486
Figure 8 Switchin
g IGBT for Five-Level
s
Ca
scade
d H-Bridge Multile
vel Inverter
Figure 9.
Simulation
mod
e
l
i
ng of SPWM gene
rating Fi
ve-level CHB inverter
The
con
s
id
ered a
goo
d qu
ality of the o
u
tput vo
ltage
if the mod
u
l
a
tion ind
e
x (MI) in the
rang
e of 0 t
o
0.95. Th
e
five levels th
at build a
m
u
ltilevel inverters m
odel i
s
exposed o
u
t in
MATLAB/SIMULINK
as
sh
own i
n
Fig
u
re
7. Moreov
er,
the si
mulatio
n
diag
ram
s
fo
r the
seven
a
nd
nine l
e
vel
si
milarly a
r
e
shown in
on
e
block. In
this
sim
u
lation,
t
he con
s
tant
SPWM wa
s use
d
.
Each bl
ock consi
s
ts of 4
switch
es IGBT
in Ca
scade
d
H-Bri
dge
(CHB) a
s
sho
w
n in Figu
re 8.
The
value of ca
rri
er freq
uen
cy
(
f
c
) u
s
ed in t
h
is de
sig
ned
is about 1
8
kHz. Figu
re
9 Simulation
modelin
g of SPWM gen
erat
ing five-level CHB inve
rter.
4.2. SVPWM Algorithm for CHB-MLI
This sectio
n pre
s
ent
s the
general spa
c
e vect
o
r
mo
dulation ap
pli
ed in the pre
s
ente
d
three
-
ph
ase n-level CHB i
n
verter.
[14]
is the heig
h
t of a secto
r
Si
, which i
s
an eq
uilateral
triangle
of un
ity side a
s
sh
own i
n
Figu
re
10. Space vector
sel
e
ctio
n and
switchi
ng
state se
quen
ce of the inverter a
r
e disc
u
s
sed. The
line-to-lin
e voltage,
can
be
obtaine
d thro
ugh the invert
er pha
se volt
age:
(5)
(6)
0.8
6
(6
3
/
2
)
h
, ,
RS
T
VV
V
sin(
2
9
0)
R
Vm
f
s
2
sin
(
2
9
0
)
3
S
Vm
f
s
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
2302-4
046
Com
parative
Study of a Th
ree Pha
s
e
Ca
scade
d H-
B
r
i
dge Multile
vel
Inverte
r
for…
(Ro
s
li Om
ar)
487
(7)
Acco
rdi
ng th
e three
-
pha
se to two-ph
ase fram
e tran
sformation, th
e output voltage of the
three
-
level
N-level ca
scad
e
d
H-bri
dge
in
verter
ca
n be
rep
r
e
s
ente
d
by a spa
c
e v
e
ctor in th
e
frame:
(8)
Figure 10. Sector on
e for two-l
e
vel inverter [14]
Whe
r
e
and
are
the
real
and im
agin
a
ry com
pone
nts of
the
sp
ace vecto
r
re
sp
ectively.
is the mag
n
i
t
ude and
is the pha
se
angle of the
spa
c
e ve
cto
r
. The spa
c
e
vector
,
referenc
e vector, two-
level
inverter,
on-ti
me calculatio
n within
a
se
ctor
for
a two-level i
n
verter volt-seco
nd equ
ation is
Ha
s b
een discu
s
se
d in [15]: To apply SVPWM
techni
que, first, the angle (
)
and secto
r
(
)
of
need to be determine
d by using:
(9)
(10)
In Equation (9) and (10
)
,
is the angle o
f
the referen
c
e vector with
respe
c
t to
axis,
is th
e angle with
in
the se
ctor and
is
its se
ctor
operation, a
n
d
int
an
d
re
m
are
stand
ard
mathem
atical fu
nctio
n
s
of intege
r and
remi
nd
er,
respe
c
tively [8]. The spa
c
e vecto
r
dia
g
ram
of a three
-
p
h
a
s
e v
o
ltage
sou
r
ce inverte
r
is a
hexagon, consisting of six sector
s. The
purpose of SVPWM algorithm is to ident
ify the triangle in
whi
c
h the
tip
of the refere
nce ve
cto
r
is locate
d.
Each trian
g
le
ca
n be treated
as a
vecto
r
o
f
a
two-level
inve
rter. T
he O
N
-time ca
n b
e
calcul
ated
u
s
in
g the
small
vector
an
alogy
of the
ON-time
equatio
n of a two-level inv
e
rter a
r
e di
scussed [8]. In
this simul
a
tio
n
, the diagra
m
for a five-level
inverter
usi
n
g SVPWM techni
que to
generate a
ca
scaded H-Bri
dge inverter
consi
s
ted of
24
IGBT switche
s
and fou
r
DC so
urce Inst
ead of six
Dc source p
r
evi
ous
work in
CHB invert
er,
as
sho
w
n i
n
Fig
u
re
11. The
harm
oni
c an
d THD p
r
of
il
es of th
e out
put voltage a
nd current of
the
CHB inve
rters have
bee
n
investigate
d
. THD for vo
lta
ge five-level
output Casca
ded
H-Bri
dge
in
2
si
n
(
2
9
0
)
3
T
Vm
f
s
24
1c
o
s
c
o
s
2
33
24
3
0s
i
n
s
i
n
33
R
S
T
VV
V
VV
V
V
//
V
,
1
,
2
,
..,
6.
Si
i
i
S
Vr
ef
/3
re
m
1
/3
i
Si
n
t
0(
0
0
360
)
(0
6
0
)
(1
6
)
ii
SS
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 23
02-4
046
TELKOM
NI
KA
Vol. 14, No. 3, June 20
15 : 481 – 49
2
488
multilevel inverters
wa
s m
easure
d
whe
n
Modul
ation
Index (MI)
wa
s eq
ual to
0.5
to 0.6, 0.75,
0.8
and 0.95. Th
e fundame
n
tal freque
ncy,
f
was 50
Hz a
nd the invert
er switching f
r
equ
en
cy wa
s 18
kH
z.
Figure 11.
Simulation
modeling of SVPWM generating
Five-level CHB
inverter
5. Simulation Resul
t
5.1. Sinusoidal Pulse Width Modula
t
i
on (SPWM
)
In this pa
per
will p
r
e
s
ent
d
a
ta an
d
re
sult
gat
he
re
d fro
m
di
scusse
d i
n
p
r
e
c
edin
g
p
apers. In
t
h
i
s
w
o
r
k
o
f
m
u
l
t
i
l
e
v
e
l
i
n
v
e
r
t
e
r
ca
scaded
H-Bright
(CHB)
three
phase
based
are
u
s
i
n
g
on
sinusoidal pulse width mo
dulation
(SPWM) control
i
n
v
e
r
t
e
r
,
a
s
i
m
u
l
a
t
i
o
n
m
o
d
u
l
e
b
y
MATLAB
/
Simulink thre
e phase multileve
l inver
t
er
s, Based
on
the simu
latio
n
results, a
Five-le
v
el SPWM
inver
t
er is Presented to alle
via
t
e harmonic com
ponents of output vo
ltage. The simulation results for
the
five-le
v
el
cascaded H-Bridge
multile
v
el
in
verter
o
u
tput
voltage
line
to
line
(
ܸ
ି
)
wav
e
form, as
shown in Fig
u
re 12 with
modulation in
dex (MI) equ
als to 0
.
6
the
full wave
with modula
t
ion
index
(MI) equa
ls to
0.75
, 0.8
and
0.9
as show
n
in
Figure
13,
14 and 15
res
pective
ly.
Figure 12. Lin
e
Voltage SPWM, MI=0.6
0
0.
0
5
0.
1
0.
1
5
0.
2
0.
25
0.
3
0.
3
5
-1
50
-1
00
-50
0
50
10
0
15
0
Ti
m
e
(
S
)
L
i
n
e
Vo
l
t
a
g
e
(
V)
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
2302-4
046
Com
parative
Study of a Th
ree Pha
s
e
Ca
scade
d H-
B
r
i
dge Multile
vel
Inverte
r
for…
(Ro
s
li Om
ar)
489
Figure 13. Lin
e
Voltage SPWM, MI=0.75
Figure 1
4
. Line Voltage S
P
WM, MI=0.8
Figure 15. Lin
e
Voltage SPWM, MI=0.95
Figure 16. Ha
rmoni
c Voltag
e SPWM, at
MI=0.6
Figure 17. Ha
rmoni
c Voltag
e SPWM, at
MI=0.75
0
0.
05
0.
1
0.
15
0.
2
0.
2
5
0.
3
0.
3
5
-
200
-
100
0
100
200
Ti
m
e
(
S
)
Li
n
e
V
o
l
t
a
g
e
(
V
)
0
0.
05
0.
1
0.
15
0.
2
0.
25
0.
3
0.
35
-
300
-
200
-
100
0
100
200
300
Ti
m
e
(
S
)
L
i
n
e
V
o
l
t
age
(
V
)
0
0.
05
0.1
0.
15
0.2
0.25
0.
3
0.35
-30
0
-20
0
-10
0
0
10
0
20
0
30
0
Ti
m
e
(
S
)
L
i
n
e
Vo
l
t
a
g
e
(
V)
0
5
10
15
20
0
2
4
6
8
10
H
a
r
m
on
i
c
o
r
der
F
u
nda
m
e
n
t
al
(
5
0H
z
)
=
17
1.
9 ,
T
H
D
=
29.
9
3
%
M
a
g
(
%
of
F
undam
e
n
t
a
l
)
0
5
10
15
20
0
1
2
3
4
5
H
a
rm
oni
c
order
F
undam
ent
al
(50H
z
)
=
1
86.
5
,
T
H
D
=
25.
4
5
%
M
a
g (
%
of
F
u
nd
a
m
e
n
t
a
l
)
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 23
02-4
046
TELKOM
NI
KA
Vol. 14, No. 3, June 20
15 : 481 – 49
2
490
Figure 18. Ha
rmoni
c Voltag
e SPWM, at
MI=0.8
Figure 19. Ha
rmoni
c Voltag
e SPWM, at
MI=0.95
FFT analysi
s
of the SPWM five levels casc
a
ded H-Bridg
e
multilevel inverter
output
are
sh
own in
Figu
re
16, 1
7
, 18, a
nd
1
9
continu
o
u
s
ly. The T
H
D
V
for voltage
o
b
tained
of th
e
output ca
sca
ded H-Brid
ge
multilevel inverter
when
modulatio
n in
dex equal
s to
0.6, 0.75, 0.8
is lower when
the modulati
on index eq
u
a
ls to 0.95.
5.2. Space Vector Pulse-
Width Mo
dulation (SVPWM)
In orde
r to validate the p
e
rform
a
n
c
e o
f
the propo
se
d schem
es, a
simulatio
n
m
odel for
three
-
ph
ase CHB multilev
e
l inverters
was devel
op
e
d
.
Line voltage
for the three
-
pha
se casca
ded
H-Bri
dge
five-level inve
rter with
mod
u
lation in
dex
of
0
.
6-0.75,
0.8 a
nd 0.9
5
a
r
e
shown in
Figu
re
20, 21, 22 an
d 23 co
ntinuo
usly.
Figure 20. Line Voltage SVPWM MI=0.6
Figure 21. Line Voltage SVPWM MI=0.75
0
5
10
15
20
0
2
4
6
8
10
12
H
a
r
m
on
i
c
or
der
F
undam
en
t
a
l
(5
0H
z
)
=
300.
7 ,
T
H
D
=
23
.
8
6%
M
a
g (
%
of
F
u
nda
m
e
n
t
a
l
)
0
2
4
6
8
10
12
14
16
18
20
0
0.
5
1
1.
5
2
2.
5
3
3.
5
4
4.
5
Harm
oni
c
orde
r
Fu
n
d
a
m
e
n
t
a
l
(
5
0
H
z
)
=
329
.
1
,
TH
D=
22
.
1
9%
M
a
g
(
%
of
F
unda
m
ent
al
)
0
0.01
0.
02
0.
03
0.0
4
0.05
0.
06
0.
07
0.0
8
0.09
-2
0
0
-1
0
0
0
10
0
20
0
Ti
m
e
(
S
)
L
i
n
e
V
o
l
t
age
(
V
)
0
0.
01
0.
02
0.
03
0.
04
0.
05
0.
0
6
0.
07
0.
08
0.
09
-
200
-
100
0
100
200
Ti
m
e
(
S
)
L
i
n
e
Vo
l
t
a
g
e
(
V)
Evaluation Warning : The document was created with Spire.PDF for Python.