TELKOM
NIKA
, Vol.11, No
.1, Janua
ry 2013, pp. 279
~28
6
ISSN: 2302-4
046
279
Re
cei
v
ed O
c
t
ober 3, 20
12;
Revi
se
d No
vem
ber 3, 201
2; Acce
pted
De
cem
ber 6,
2012
The Implementation of S-curve Acceleration and
Deceler
ation Using FPGA
Guangy
ou Yang*
1,2
, Zhiji
an Ye
1,2
, Yur
ong Pan
1,2
and Zhiy
a
n M
a
1,2
1
School of Mec
han
ical En
gi
ne
erin
g, Hube
i U
n
iversit
y
of T
e
chno
log
y
, W
u
h
a
n
, Chin
a
2
State Ke
y
La
b
.
Of Digital Ma
nufacturi
ng Eq
uipm
ent & T
e
chno
log
y
(H
US
T
)
,
W
uhan, Ch
i
n
a
*corres
pon
di
ng
author, e-mai
l
: pekka@
126.c
o
m
A
b
st
r
a
ct
T
h
is pa
per a
n
a
l
y
z
e
s
the
basic
princi
pl
e of S-
cu
rve
acc
e
ler
a
tion and dec
ele
r
ation,
a
nd pre
s
ents a
n
imple
m
entati
o
n
meth
od
of S-curve
contr
o
l
algor
ith
m
b
a
s
ed o
n
F
P
GA. T
he S-curve
function
mo
d
u
le
dia
g
ra
m
and
i
m
p
l
e
m
e
n
tin
g
meth
od
of PW
M spee
d
adj
us
ting
are
descri
bed
in
F
P
GA. T
he steps
of S
-
curve
spee
d diss
oci
a
tion
mo
dul
e a
nd PW
M vari
a
b
le fre
q
u
ency
spee
d co
ntrol
are sh
ow
n in
this pa
per. Hi
g
h
Performanc
e a
nd Ca
pac
ity Mixed H
D
L Si
mulati
on softw
are – Mod
e
lSi
m
is used to ve
rify the alg
o
rit
h
m
Verilo
g HD
L co
de exec
uted i
n
F
P
GA. At last,
a test ex
peri
m
ent utili
z
i
ng s
u
ch alg
o
rith
m
mentio
ne
d ab
ov
e is
carried
o
u
t on
one
x-y w
o
rkin
g stan
d. T
here
is a
go
od agre
e
ment betw
e
e
n
si
mu
lati
on an
d
ex
peri
m
ent. T
h
e
exper
imenta
l
r
e
sults i
ndic
a
te
that t
he al
gor
ithm
is si
mp
le
a
nd re
lia
ble
e
n
o
ugh to
meet d
i
fferent ap
plic
ati
o
n
re
q
u
i
r
em
en
ts.
Key
w
ord
:
FPGA; S-curve;
Accel
e
ration/
deceleration; PWM.
Copyrig
h
t
©
2013
Univer
sitas Ahmad
Dahlan. All rights res
e
rv
ed.
1. Introduc
tion
The spee
d control of mot
o
r a
c
celeration and d
e
cel
e
ration i
s
a
cru
c
ial fa
ctor when
high spee
d a
nd preci
s
io
n positio
n of motor is
need
e
d
[1], [2]. Th
e comm
on
speed
cont
rolli
ng
curve
s
are lin
ear, index an
d S-cu
rve. The flexibility
of
control syste
m
with linear
spe
ed co
ntrol
is
poor. It trigg
e
r
s p
o
tential p
r
oblem
s such
as
sho
c
k an
d
accele
ration/
deceleration
mutations
wh
en
the motor sta
r
t up a
nd a
cceleratio
n
/de
c
eleratio
n ph
a
s
e i
s
ove
r
. T
herefo
r
e, thi
s
algo
rithm is
no
t
suited fo
r a control
system
which re
quires hig
h
sp
ee
d and p
r
e
c
isi
on. By contra
st, the S-cu
rve
algorith
m
is
usu
a
lly used
in ma
ny hig
h
grade
mult
i-ax
is
mot
i
on
co
nt
rol
sy
st
ems.
I
t
r
edu
ce
s
sho
c
k a
nd
m
a
ke
s full
u
s
e
of the m
o
tor
perfo
rman
ce
by attenuatio
n of the
moto
r d
e
celeration
in
start-up
stag
e [3]. In o
r
de
r to im
prove t
he
real
-t
ime perfo
rman
ce
of
motion
co
ntrol system, the
accele
ration/
deceleration spe
ed contro
l
algorith
m
m
u
st be
sim
p
l
e
[4]. This p
aper analy
z
e
s
S-
curve
spe
ed
control algo
rit
h
m and reali
z
ation in FPG
A
.
2. Sy
stem structur
e of S-curv
e acceler
ation and d
ecelera
t
ion
based on FP
GA
System stru
ct
ure of S-curv
e method imp
l
em
ented in F
P
GA is sho
w
n as Figu
re 1.
Figure 1. S-curve
sy
st
em st
ru
ct
ur
e
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 23
02-4
046
TELKOM
NIKA
Vol. 11, No
. 1, Janua
ry 2013 : 279 – 2
8
6
280
The S-cu
rve disso
c
iation
module i
n
the
Figure
1
extracts seve
ral poi
nts from continuo
us
spe
ed-tim
e
S-cu
rve an
d co
nverts tho
s
e
spe
ed value t
o
corre
s
p
ondi
ng frequ
en
cy value (de
c
im
al)
for every poin
t. The more p
o
ints extra
c
te
d, the
higher
pre
c
isi
on of S-cu
rve re
alize
d
in FPGA.
In this pape
r the motor drive works in
pos
itio
n mod
e
, which ch
a
nge
s motor
speed by
altering th
e frequ
en
cy of input si
gnal.
Thus,
the
regulatio
n of motor
spe
e
d
usin
g S-curve
controlling al
gorithm can be
a
c
hieved by
altering
th
e frequ
en
cy of spe
ed con
t
rolling p
u
lse. In
Figure 1, In orde
r to adju
s
t the sp
eed
of mo
tor, the PWM spee
d reg
u
lation
model
conve
r
ts
freque
ncy val
ue pro
d
u
c
ed
by S-curve module to co
rre
sp
ondi
ng frequ
en
cy pul
se output, a
nd
different freq
uen
cy value has different frequ
en
cy pul
se.
2.1 S curv
e s
p
eed disso
ciation modul
e
The pri
n
ci
pal
of S-cu
rve accele
ration a
n
d
deceleratio
n [5] is sho
w
n
as Figu
re 2.
Figure 2. The
princi
ple of S-cu
rve a
c
cele
ration an
d de
cele
ration
The rel
a
tion
ship of spe
ed
and de
cel
e
rat
i
on
is describ
ed in formul
ate (1), an
d
the relation
sh
ip betwe
en a
c
celeration
and jerk
)
(
t
j
in formulate (2
).
dt
t
dv
t
a
/
)
(
)
(
(1)
dt
t
da
t
j
/
)
(
)
(
(2)
Without impa
cting controlli
ng perfo
rma
n
c
e, thre
e hypotheses
can
be dra
w
n:
(a)
4
5
3
4
1
2
0
1
t
t
t
t
t
t
t
t
(b) ;
(c) ;
;
;
;
;
In above formulas,
is accele
rating ti
me. Assu
me
that decele
r
ation time e
qual
s
accele
ration t
i
me; so the
deceleration
time is
also
.
Formul
as
(3
) and (4
) are derived from
formula
s
(1
)
and (2
) ba
se
d on above h
y
pothesi
s
.
While :
2
2
1
Jt
v
(3)
0
t
1
t
2
t
t
t
t
v
j
a
J
J
A
V
/2
V
t
4
t
3
t
5
t
()
vt
()
at
()
at
20
tt
T
10
/2
tt
T
0
()
0
vt
1
()
/
2
vt
V
2
()
vt
V
3
()
vt
V
4
()
/
2
vt
V
5
()
0
vt
T
T
1
0
tt
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
2302-4
046
The Im
plem
e
n
tation of S-curve Accele
ra
tion and Deceleratio
n
Usin
g FPGA (
G
u
a
ngy
o
u
Y
a
ng
)
281
While :
(4)
, utilizing counter/timer to get ru
nning time:
. This algorithm
update
s
th
e spe
ed and
correspon
ding
output
freq
u
ency
at eve
r
y cycle
t
, and it is usually
microsecond level,
is
the value
of
counter.
Utilizing formul
as (1
), (2), (3) and (4), the final
spe
ed calcula
t
ing formula
s
(5) a
nd (6
) ca
n be derive
d
as follo
ws:
While :
(5)
While :
(6
)
The value of
on every poi
nt of the S-cu
rve can be
derived from
formula
s
(5)
and
(6). T
hen
de
cimal frequ
e
n
cy value
co
rre
sp
ondi
ng
t
o
different sp
eed can be derived
f
r
om
the
formula of sp
eed an
d freq
uen
cy
(the u
n
it
of is um/s
and
is HZ,
is a con
s
tant an
d
it
has
different
value in different system, f
o
r expe
ri
me
n
t
al system,
is set to 20) [
6
]. Figure
3 is
S-cu
rve’s in
st
antiation figure in FPGA.
Figure 3. The
S-cu
rve mod
e
l instantiatio
n
figure in FP
GA
2.2 PWM spe
e
d regula
t
ion model
Freq
uen
cy value
derived f
r
om corre
s
po
nding
spe
ed
value nee
ds t
o
be co
nvert
ed to
corre
s
p
ondin
g
pul
se
outp
u
t. While th
e
ne
w type of
po
wer ele
c
tronic po
we
r
compon
ents a
r
e
appe
arin
g d
a
ily, Pulse
Wi
dth Mod
u
lati
on (P
WM
)
co
ntrol
ways b
e
com
e
m
a
in
stream [7], [8]
by
usin
g all-co
ntrolling
switch
power
com
pone
nts. In
t
h
is p
ape
r, m
o
tor d
r
iver
works i
n
po
siti
on
mode a
nd ca
n adju
s
t moto
r sp
eed by
ch
angin
g
the
fre
quen
cy of PWM si
gnal
(keepin
g
duty ratio
unchan
ged
). Figure 4 is th
e basi
c
mod
e
l
of PWM.
Figure 4. The
basi
c
model
of pulse
width
modulation
12
tt
t
22
1
(4
2
)
4
vJ
t
T
t
T
2
4/
J
VT
c
tt
n
c
n
1
0
tt
22
2
2/
c
vV
t
n
T
12
tt
t
22
2
2
/(
4
2
)
cc
vV
T
T
t
n
T
t
n
T
v
f
kv
v
f
k
k
f
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 23
02-4
046
TELKOM
NIKA
Vol. 11, No
. 1, Janua
ry 2013 : 279 – 2
8
6
282
In Figu
re 4,
circul
ation
co
u
n
ter
cou
n
t ex
tern
sam
p
ling
pul
se a
nd it
s value i
s
a
d
d
ed 1
at
every sa
mpli
ng cy
cle. Th
e com
p
a
r
ator will co
mpa
r
e
cou
n
ter valu
e with value
loade
d in buf
fer
regi
ster. Whe
n
the output value of cou
n
t
er is le
ss
tha
n
half of the cou
n
ting valu
e of pulse
cycle,
the outp
u
t of
co
mpa
r
ato
r
stays l
o
w lev
e
l. Wh
en
the
y
are
eq
ual,
the outp
u
t
ch
ange
s i
n
to hi
gh
level. Whe
n
the outp
u
t value is
equ
al to the c
ountin
g value of p
u
l
se
cycle, the
output level
i
s
cha
nge
d fro
m
high to l
o
w. Thus
a pul
se cycl
e is
over. In every
cycle of comp
arato
r
’s
co
unt
ing,
the co
mpa
r
at
or o
u
tputs
different fre
que
ncy pul
se
du
e to differe
nt pulse
cycle
s
of modul
atin
g
sign
al fro
m
i
nput, so that
the
spe
ed
regulatio
n
of
motor
ca
n b
e
a
c
hieved
u
nder the
po
si
tion
mode of moto
r drive.
Figure 5 i
s
t
he in
stantiati
on figu
re of
PWM mo
del.
This
mod
e
l desi
g
n
s
a
common
controlled fre
quen
cy divisi
on ma
chine,
whi
c
h
can m
eet variou
s requireme
nt describ
ed ab
o
v
e
usin
g ha
rd
wa
re p
r
og
ram
m
ing lan
gua
ge
Verilog
HDL [
9
]
on Q
u
a
r
tus-II [10] re
sea
r
chin
g platfo
rm.
Comp
ared to
Figure
4, re
set is re
set si
g
nal, clk i
s
inp
u
t clock, cy
cl
e is cy
cle val
ue of pul
se (i
t is
the value of
derived from 2.1)
and
clko
ut is PWM ou
tput signal.
Figure 5. Instantiation figure of PWM mo
del in FPGA
PWM mo
del
is reali
z
ed
in
FPGA u
s
ing
hardw
are
p
r
ogra
mming
l
angu
age V
e
ri
log HDL
an
d
its
core co
de is
sho
w
n a
s
bel
ow.
wire[31:0] duty; // occupy proportion
assign duty = compare_reg/2; //occupy proportion is always 50%
reg[31:0] compare_count;//count of pulse
//regcompare_reg_refresh_flag;
always @ (negedge reset or posedgeclk)
begin
if(!reset)
begin
clkout<=
0;
compare_count<=
0;
end
else if (compare_reg != 0)
begin
/* when output value of comparator is half of cycle value ofpulse, the output level
of comparator changes to high level.*/
if(compare_count == duty)
begin
clkout<=
1;
compare_count<= compare_count + 1;
end
/* when outp
ut value of
comparator is equal to c
ycle value o
f
pulse, the
output leve
l
of comparator changes from high to low. */
else if (compare_count == compare_reg)
begin
clkout<=
0;
compare_count<=
1;
end
else
compare_count<= compare_count + 1;
end
else
begin
compare_count<=
0;
clkout<=
0;
end
end
f
re
s
e
t
cl
k
c
y
c
l
e[
31
.
.
0
]
cl
ko
u
t
PW
M
_
M
odule
ins
t
VC
C
re
s
e
t
IN
P
U
T
VC
C
cl
k
IN
P
U
T
VC
C
cy
cl
e
[
3
1
:
0
]
IN
P
U
T
cl
ko
u
t
OU
T
P
U
T
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
2302-4
046
The Im
plem
e
n
tation of S-curve Accele
ra
tion and Deceleratio
n
Usin
g FPGA (
G
u
a
ngy
o
u
Y
a
ng
)
283
Timing sim
u
l
a
tion of PWM
model in FPGA is sh
own
as Figu
re 6.
Figure 6. Timing simul
a
tion
result of PWM model in F
P
GA
3. Implementation of S cu
r
v
e accelera
t
ion and dece
leration
In order to
simplify operatio
n, accele
ration ti
me, con
s
tan
t
speed time and
deceleration
t
i
me are set to1 second, sp
eed refres
h cycle is set to 200 us. The
speed of starti
ng
up mom
ent (t=0) i
s
set to zero an
d st
able runni
ng
stage
(
)
is
set to 20mm/s. For
con
c
rete im
pl
ementation
s
of ea
ch
sp
ee
d sta
ge
cu
rve
in Fig
u
re 2
(
a
)
, the foll
owin
g corre
s
po
ndi
ng
equatio
ns
ca
n be derive
d
from form
ula
s
(5) a
nd (6
).
whe
n
and :
(7)
whe
n
,
and
:
(8)
is 5
0
Mh
z p
u
l
s
e
co
unter. I
n
the
accele
rati
on
stage,
is
set to
ze
ro
initially and
add 1
op
erati
on throug
hou
t the stag
e. After 1
se
cond
, the accel
e
ra
tion is
over
a
nd
rea
c
he
s
maximum va
lue. In con
s
t
ant sp
eed
stage,
ke
ep
s con
s
tant. F
o
r the p
r
o
c
e
ss i
n
speed
deceleration
stag
e, the
re
sult i
s
complete
ly th
e opp
osite
of accele
rati
on st
age;
with
decrea
s
e
s
as 1 o
p
e
r
ation
i
s
contin
ued
to be
subtract
ed from the
maximum val
ue. Th
us,
mo
tor
will stop at th
e end of de
ce
leration
stage
.
S-cu
rve a
c
ce
leration a
nd
deceleration
model i
s
real
ized in FP
G
A
using h
a
rd
ware
prog
ram
m
ing
langua
ge Ve
rilog HDL a
n
d
its core co
de
is sho
w
n a
s
belo
w
.
begin
/******************************************************************************
The first speedup stage
PWM_INITAL_COUNT is the
counting value corresponding to minimum initial speed that can
be realized in FPGA, and its precision depends mainly on the control accuracy and spee
d
of the refresh interval. The higher control
precision of the system,
the smaller
the
refresh interval, the smaller minimum initial speed needed to be realized and this
parameter va
lue is also
smaller. Whe
n speed valu
e is reduced
to a certai
n degree, it
s
corresponding frequency pulse outp
ut cannot b
e
achieved
within the
limitation of the
hardware its
elf. In the
test, this v
alue is set
to 300. FIR_
STAG_TIMES i
s
the counte
r
value corresponding to the end of the first stage of acceleration and is set to 2500 in
test system.
is the speed value when
. This algorithm
is finally r
ealized by m
ultiplier and divider in
FPGA,
will add 1 at ev
ery rise of
the refresh
clock (spe
ed_change_clk), at the
end of fi
rst acceler
ation stage
=
FIR_STAG_TIMES=2500.
****************************************************************/
23
tt
t
1
0
tt
45
tt
t
2
16
/
10000(
/
)
c
vn
u
m
s
12
tt
t
23
tt
t
34
tt
t
2
200
00
(
10000
2
)
/
2500
(
/
)
c
vn
u
m
s
c
n
c
n
c
n
c
n
c
n
2
div
_3_r
esul
t
1
6
/
10000(
/
)
c
nu
m
s
1
0
tt
c
n
c
n
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 23
02-4
046
TELKOM
NIKA
Vol. 11, No
. 1, Janua
ry 2013 : 279 – 2
8
6
284
if (s_count>= PWM_INITAL_COUNT &&s_count<= FIR_STAG_TIMES)
begin
v <= div_3_result;
end
/*************************************************************
The second speedup stage
TOTAL_SPEEDUP_TIMES is
the counting
value corr
esponding to
the end o
f
the secon
d
acceleration stage and is
set to 5000 in
test system
.
is the speed value when
.This algorithm is finally realized by multiplier and divider in FPGA,
will add 1 at
every rise o
f
the refres
h clock(speed_change_clk),
=TOTAL_SPEEDUP_TIMES=5000 at th
e
end of second acceleration stage, and will keep its value not changed in constant spee
d
stage.
*************************************************************/
if(s_count> FIR_STAG_TIMES &&s_count<= TOTAL_SPEEDUP_TIMES )
begin
v
<=
20000
-
div_1_quo;
end
/*************************************************************
The first speeddown stage
The first
stage of d
eceleration is an in
verse proce
ss of the
second st
age of
acceleration. FIRST_SPEEDDOWN_STAR_POINT is counting value corresponding to the mom
ent
when deceleration stage(the end of the
constant stage)
is over,
SECON_SPEEDDOWN_STAR_POINT is the co
unting value corresponding to the mo
ment when fi
rst
deceleration stage(the moment at the beginning of second deceleration) is over.
*************************************************************/
if(s_count>=FIRST_SPEEDDOWN_STAR_POINT&&s_count<=SECON_SPEEDDOWN_STAR_POINT)
begin
v <= 20000 - div_1_quo;
end
/*************************************************************
The second speeddown stage
The second
deceleration stage is a
inverse pr
ocess of th
e first acc
eleration stage.
S_CARVE_END_POINT is the
speed value
corresponding to the mo
ment when S
curve algorithm
is running over
***********************************************************/
if (s_count>SECON_SPEEDDOWN_STAR_POINT &&s_count<= S_CARVE_END_POINT)
begin
v <= div_3_result;
end
Combi
ned
wi
th PWM
spe
ed a
d
ju
sting
model, th
e
si
mulation
re
sult for
accel
e
ration
and
deceleration
of the S curve algorith
m
u
s
ing Mo
del
si
m is sh
own a
s
Figu
re 7.
(a) Waveform of S curve accele
ration
stage
(b) Waveform of S curve deceleration
stage
Figure 7. Wa
veform of S curve accel
e
ra
tion and de
ce
leration
stage
Seen from t
he figure a
b
o
ve, the expecte
d
ch
an
ge between
output pulse freque
ncy
in
accele
ration
stage a
nd de
cele
ration
sta
ge is con
s
iste
nt.
2
div
_1_quo
20000
(
10000
2
)
/
2500(
/
)
c
nu
m
s
12
tt
t
c
n
c
n
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
2302-4
046
The Im
plem
e
n
tation of S-curve Accele
ra
tion and Deceleratio
n
Usin
g FPGA (
G
u
a
ngy
o
u
Y
a
ng
)
285
4. Applicatio
n experimen
t
Usi
ng m
o
tion
co
ntrol
platfo
rm b
a
sed
on
ARM-FP
GA[11],[12] to test
the effect
of
S cu
rve
algorith
m
re
a
lized in
FPG
A
(EP2C5
Q2
08C8 from Al
tera), the
exp
e
rime
ntal dev
ice u
s
ing i
n
the
tes
t
is
s
h
ow as
Figure 8.
Figure 8. The
experime
n
tal
device in S-
curve of accel
e
ration a
nd d
e
cel
e
ratio
n
While
FPGA
is ru
nnin
g
S-cu
rve
algo
rithm,
it i
s
al
so
coll
ectin
g
the
data
of moto
r
encode
r at the sam
e
time, and tho
s
e d
a
ta will be u
p
l
oade
d to PC throug
h Ethernet to di
spl
a
y.
The re
sult is
sho
w
n a
s
figu
re 9.
Figure 9. The
motion cont
rol result of S-curve b
a
sed
on FPGA
Seen from the cha
r
t, the curve
sha
pe is
co
nsi
s
tent with the theoretical sha
p
e
fundame
n
tall
y. In this te
sti
ng
system, th
e date
colle
cting cycle
for motor en
cod
e
r
i
s
200
us
a
nd
the colle
cting
date of PC from FPGA ha
s no follo
wi
ng
pro
c
e
ss, so the cu
rve is n
o
t very smoot
h.
If a display wi
th higher a
ccura
cy and mo
re sm
ooth is
need
ed, som
e
other meth
ods
can b
e
taken
su
ch a
s
red
u
c
ing the d
a
te colle
cting
cycle and
u
s
ing
certai
n data trailing process algorithm.
5. Conclusio
n
The
cont
rolle
r ba
se
d o
n
hard
w
a
r
e
pro
g
rammi
ng l
a
ngua
ge h
a
s
advantag
es like
high
system i
n
teg
r
ation a
nd
sho
r
t de
sign
cy
cl
e, whi
c
h
ma
kes it m
a
in
stre
am in
chi
p
d
e
s
igni
ng. Fo
r t
h
e
open motio
n
control
syst
em, res
earch
ing and reali
z
ing a
c
cele
ra
tion and de
celeratio
n
mo
del
usin
g hardware with reu
s
ing fun
c
tion
and re
lated
functional
model, takin
g
advantage
of
D
r
iver signal
s
p
eed
dire
ction
F
eedback signal
feedback pul
s
e
of encoder,
feedback signal of
grating
bar
Si
g
n
al isolating
an
d converting
interface board
driver
ARM
D
e
vel
o
p
m
ent
b
oard
(
s
3c2410)
F
P
GA core
board
EP2C5Q208C8
sw
i
t
ch
er
Sever motor
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 23
02-4
046
TELKOM
NIKA
Vol. 11, No
. 1, Janua
ry 2013 : 279 – 2
8
6
286
reconfigu
r
a
b
le ability (algo
r
ithm re
config
urabl
e)
of the
programma
b
l
e logic devices FPGA, then
the motion control chip whose function
s are
cu
stom
ized
can be
achi
eved flexibly acco
rdi
n
g to
requi
rem
ent.
Ackn
o
w
l
e
dg
ements
This
work h
a
s
bee
n supp
orted by Op
e
n
Re
sea
r
ch
Found
ation o
f
State Key L
ab. of
Digital Man
u
facturi
ng Equi
pment and T
e
ch
nolo
g
y, HUST, Chin
a (Grant
No.DM
E
TKF2009
01
7).
Referen
ces
[1]
Che
n
Z
e
yu, Z
hao Gu
an
g
y
a
o
.
F
u
zzy
Co
ntrol Stra
teg
y
a
nd Sim
u
lati
on
for Dual E
l
e
c
tric T
r
acke
d
Vehic
l
e Motio
n
Control.
Appl
i
ed Mech
anics
and Mater
i
als
.
201
1; 130-
134:
309-3
12.
[2]
T
an KK, Huang SN,
Dou HF
,
Lee T
H
,
Chin SJ,
Lim
SY. Adaptiv
e rob
u
st motion contro
l for preci
s
e
trajector
y
tr
acki
ng ap
plic
atio
ns
.
ISA T
r
ansacti
ons
. 200
1; 40(
1); 57-71.
[3]
Z
hang Hu
a
y
u,
W
ang
F
u
mao, Xu F
angq
ua
n.
Stud
y o
n
the
Algor
ithm
of S Curv
e
Acceler
a
tion/de
celeration.
Moder
n Man
u
fac
t
uring T
e
ch
nol
ogy an
d Equ
i
p
m
e
n
t
. 2006; 2:
21-2
2
.
[4]
Yang Y
an, W
ang Y
unku
an,
Song Yi
ng
hu
a. Impl
eme
n
ta
tion of Accel
e
ration/D
e
cel
e
ra
tion of N
C
S
y
stem Bas
ed
on F
P
GA.
Ma
nufacturi
ng T
e
chno
logy & Ma
chin
e T
ool
. 20
07; 2: 31-3
4
.
[5]
Lin Yis
o
n
g
, T
a
ng Z
h
a
oho
ng,
Ou Rui
x
i
a
n
g
, L
i
n Jin
p
in
g, Gon
g
Demi
ng. An
Ac
/decel
aratio
n Calc
ulati
o
n
Method for S C
u
rve.
Manufact
u
rin
g
T
e
chn
o
lo
gy & Machin
e T
ool
. 200
5; 11:
74-7
5
.
[6]
Pan W
u
, Res
earch a
nd
De
sign a
n
Rec
o
nfigur
ation M
o
tion Co
ntrol S
y
stem Bas
ed
on Net
w
o
r
ks.
Contro
l System Bas
ed on N
e
tw
orks
. 2009; 5:59-6
0
.
[7]
Kumar, Mal
lis
e
tti Rajes
h
, L
eni
ne, D
u
rais
am
y
Babu,
Ch S
a
i.
A varia
b
l
e
s
w
it
chin
g freq
ue
nc
y
w
i
th
bo
ost
po
w
e
r factor correctio
n conv
erter.
T
e
lkomni
ka
. 2011; 9(
1): 47-5
4
.
[8]
Li Z
h
aoh
ui, S
h
en Ga
ng. D
e
si
gn
of di
gital
p
u
lse
w
i
dt
h mo
dul
ator b
a
se
d
on C
P
LD.
E
l
e
c
trical Dr
iv
e
Autom
a
tion
. 20
04; 6(3):7-9.
[9]
Sutikno, T
o
le.
F
P
GA for ro
botic
app
licati
ons:
F
r
om
an
droi
d/huma
n
o
i
d ro
bots to
a
r
tificial m
en.
Te
lkom
n
i
ka
. 20
11; 9(3): 40
1-4
02.
[10]
William Kl
eitz. Digita
l
Electro
n
i
cs
w
i
t
h
VHD
L
(Q
uartus II Version). Pub
lish
e
r
: Prentice Hal
l
.
Cop
y
r
i
g
h
t:
200
6.
[11]
Yang Gua
n
g
y
ou, Li Ming,
Z
hang D
aod
e
and Xu
W
a
n
.
Ethernet Interface of Hig
h
Speed D
a
ta
Acquis
i
tion S
y
s
t
em Based o
n
ARM-F
PGA.
Advanc
ed Sci
e
n
c
e Letters
. 201
1; 4: 2538
–25
4
2
.
[12]
Yang Gu
ang
you, Li Min
g
, Z
han
g Shu
a
n
g
q
i
ng a
nd
Xu W
an. Rese
arch
and
im
plem
ent
ations of th
e
IEEE 1588 Precision T
i
me Prot
ocol bas
ed on ARM-Linux
.
Advanc
ed M
a
terials
Res
earc
h
.
20
11; 1
5
6
-
157: 14
92-
149
6.
Evaluation Warning : The document was created with Spire.PDF for Python.