TELKOM
NIKA Indonesia
n
Journal of
Electrical En
gineering
Vol.12, No.5, May 2014, pp
. 3705 ~ 37
1
2
DOI: http://dx.doi.org/10.11591/telkomni
ka.v12i5.4188
3705
Re
cei
v
ed Au
gust 19, 20
13
; Revi
sed
De
cem
ber 1
3
, 2013; Accepte
d
Jan
uary 4, 2014
Input-Current and Load Voltage Sharing in Input-
Parallel Output-Series Connected Boost Half Bridge
DC-DC Converter Using Stable Control Scheme
Amir Mahmo
od Soomro*
1
, Shahna
w
a
z
Farhan Kha
h
ro
2
, Shahna
w
a
z T
a
lpur
3
,
Liao Xiaozh
ong
4
, Farhan
Manzoo
r
5
1,2,
4,5
School of Automatio
n
, Beiji
ng Institute
of
T
e
chnol
og
y,
Beiji
ng 10
08
1, P. R. China
1,3
Mehran Univ
ersit
y
of En
gin
eeri
ng an
d T
e
chno
log
y
, Jams
horo, Sin
dh, P
a
kistan
*Corres
p
o
ndi
n
g
author, e-ma
i
l
: aamir.m.soo
mro@gma
il.co
m
A
b
st
r
a
ct
T
h
is pap
er ex
p
l
ores a c
onfig
u
r
ation for b
oost
half bri
dge
DC
-DC conv
erters
, connecte
d in
para
lle
l
at the i
n
p
u
t an
d seri
es at th
e
outp
u
t, such t
hat the c
onv
er
ters share
the
inp
u
t curre
nt a
nd l
o
a
d
vo
ltag
e
equ
ally. A sta
b
le c
ontrol
sc
he
me
has
be
e
n
dev
el
ope
d t
o
ach
i
ev
e this
obj
ective. In
order to v
e
rify
the
effectiveness
and sta
b
i
lity o
f
control sc
he
me, i
n
p
u
t-
par
a
llel
outp
u
t-seri
es (IPOS) con
nected
bo
ost
half
brid
ge (BHB) DC-DC C
onver
ter has bee
n si
mu
late
d for the di
fferent loa
d
cond
itions suc
h
as for fixed loa
d
,
half lo
ad a
nd c
ontin
uo
usly var
y
ing l
o
a
d
. T
he results are
fo
u
nd to be s
a
tisfactory at each
loa
d
con
d
itio
n
an
d
valid
ate the pr
opos
ed co
nver
ter structure.
Ke
y
w
ords
: bo
ost half bridg
e
(BHB), DC-DC converter, in
put
-par
all
e
l out
put series (IPOS), input current
shari
ng (ICS), output
volt
age
shari
ng (OVS)
Copy
right
©
2014 In
stitu
t
e o
f
Ad
van
ced
En
g
i
n
eerin
g and
Scien
ce. All
rig
h
t
s reser
ve
d
.
1. Introduc
tion
Re
cently, many applicatio
ns re
quires
hi
gh output
voltages, the
IPOS conn
ection i
s
reno
wn
ed
a
nd is p
r
ese
n
tly used
in
su
ch
appli
c
ations.
With
indep
end
en
t output voltage
controlle
rs, st
anda
rd DC-DC conve
r
ters
can a
c
hieve
equal ICS an
d OVS [1]. A sch
eme ba
sed
on com
m
on
output voltage loop and in
dividual inne
r
current loop
s is discu
s
se
d in [2]. DC-DC
conve
r
ters a
r
e commonly
used in
re
sidential,
ind
u
s
trial and ae
rospa
c
e envi
r
onm
ents.
T
he
power su
ppli
e
s have
hi
gh power den
sit
y
and
hi
gh
re
liability due t
o
the a
d
van
c
ement in
mo
dern
sci
entific te
ch
nology. Va
st
resea
r
ch h
a
s bee
n ma
de,
over la
st fe
w
decade
s, to
d
e
velop i
s
olat
ed
DC-DC conv
erters whi
c
h possess
the
capability of processi
ng th
e energy effectively [3-8]. For
high po
we
r d
ensity, it is nece
s
sary to h
a
ve hi
gh
swit
chin
g freq
uen
cy. However,
increa
se of the
electroma
gne
tic interfe
r
en
ce a
nd i
n
cre
a
se
of
switching lo
sse
s
may be
cau
s
ed by in
crea
sin
g
swit
chin
g fre
quen
cy. Num
ber of appli
c
a
t
ions are
fou
nd in literature whe
r
e low i
nput voltage has
to be
convert
ed into
hig
h
output voltag
e. It is
h
a
r
d
to
su
s
t
a
i
n
h
i
gh
in
pu
t
c
u
rr
en
t s
t
re
ss
es an
d
high output
v
o
ltage stresses
fo
r
th
e si
ngle modul
e [9,
10].
A
n
e
w
cont
rol strategy
ha
s be
en
pre
s
ente
d
for serie
s
-pa
r
all
e
l modula
r
DC-DC co
nverte
rs in [11].
An unbal
an
ced outp
u
t voltage i
s
produ
ced
due
to the intri
n
si
c variatio
ns in th
e
para
m
eters o
f
prop
erly co
n
necte
d
id
enti
c
al co
nver
te
rs. In a
ddition,
this m
a
y cau
s
e th
e n
onlin
ear
behavio
r for
the circuit variabl
es [1
2]. The indi
vid
ual co
nverte
r conn
ecte
d i
n
multi-mo
du
lar
system m
a
y suffer from th
ermal
stre
sse
s
du
e to
the
non-unifo
rm
distrib
u
tion of
output volta
ges
resulting i
n
the un
relia
ble
ope
ration
of the sy
stem.
T
he a
r
chitect
u
re
s
with uni
fied app
ro
ach of
voltage di
stri
bution
control
are avail
able
in [13,
14]. One
comm
on
filter has
bee
n re
comm
en
ded
in [15] for IPOS modula
r
based DC-DC co
nverte
r
with the adva
n
tage
s su
ch
as hig
h
effici
ency,
low co
st and
rapid dyn
a
mi
c re
spo
n
se. The full brid
g
e
DC-DC co
n
v
erters in IPOS configu
r
a
t
ion
with paramet
er differe
nce
has be
en a
nalyze
d
fo
r its perfo
rma
n
ce and the sensitivity of the
output voltag
e error to the
maximum pa
rameter vari
an
ce of ci
rcuit compon
ents i
s
sho
w
n in [16
]
.
This pap
er p
r
opo
se
s th
e
IPOS config
u
r
at
ion
of BHB DC-DC co
nverters
with
stabl
e
control
sch
e
m
e. The m
a
i
n
purpo
se of
the co
ntrol
schem
e is to
maintain e
q
u
a
l ICS an
d O
V
S.
Therefore, th
e rel
a
tion
ship
between I
C
S and
OVS
has be
en d
e
veloped. In
o
r
de
r to ve
rify the
control obje
c
t
i
ve, the IPO
S
configu
r
ati
on of
BHB DC-DC
conve
r
ter is sim
u
lat
ed on MATL
AB
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ISSN: 23
02-4
046
TELKOM
NI
KA
Vol. 12, No. 5, May 2014: 3705 – 37
12
3706
usin
g si
mpo
w
er tool
s. Simulation fo
r t
he conv
e
r
ter
config
uratio
n
has be
en
carri
ed o
u
t for the
different load
condition
s
so that the effe
ctivene
ss and stabilit
y of
control scheme
can
be
observed. Eq
ual ICS and
OVS are obta
i
ned re
ga
rdle
ss of the diffe
rent load
con
d
itions.
This pa
pe
r is org
ani
zed
as follo
ws. T
he IPOS BHB DC-DC co
nverter i
s
sh
own i
n
section II. The mathemat
ical
representation
of ICS
and
OVS is given i
n
S
e
ction III. The
prop
osed co
ntrol strategy
is illustrate
d
in Sect
ion IV. Simulations and results are pre
s
e
n
te
d i
n
Section V. Co
nclu
sio
n
s a
r
e
discusse
d in Section VI.
2.
Proposed IPOS
BHB D
C
-
DC Conv
erter
C
onfigu
r
ation
The B
H
B DC-DC
conve
r
te
r in th
e form
of IPOS co
nfiguratio
n i
s
re
pre
s
ente
d
in
Figure 1
as a g
ene
ral
block dia
g
ra
m. The prop
ose
d
co
nf
igu
r
ation
with schematic
diag
ram i
s
sh
own in
Figure 2. Ide
n
tical B
H
B DC-DC convert
e
rs are
con
n
e
c
ted in
pa
rall
el at the in
put
side
wherea
s at
the outp
u
t sid
e
the
s
e a
r
e
conne
cted
in
serie
s
.
Th
e g
r
een
blocks
shown in
Figu
re 2, a
s
m
odul
e#
01 and mo
du
le# 02, co
nsi
s
ting of a half
bridge tog
e
ther with a
n
in
ducto
r and in
put DC volta
ge;
have bee
n conne
cted at t
he prim
ary
si
de of hi
gh freque
ncy tra
n
s
form
er
while
voltage dou
bler
rectifie
r i
s
co
nne
cted
at seco
nda
ry si
d
e
of hig
h
fre
quen
cy tra
n
sformer.
The
turn
ratio
of h
i
gh
freque
ncy
tra
n
sformer i
s
set to
be
1:
2 for individ
ual m
odule
s
.
The
outp
u
t voltage
will
be
increa
sed
in
the propo
rtio
n a
s
the tu
rn
ratio
s
of
hig
h
freq
uen
cy t
r
an
sform
e
r are select
ed. T
he
prop
osed con
f
iguration h
a
s been de
sign
to operate at
various lo
ad
conditio
n
s.
Compl
e
me
ntary
swit
chin
g sig
nals a
r
e give
n to
Q
1
,
Q
2
o
f
module# 01
and
Q
3
,
Q
4
of module# 02
. The switching
sign
al of individual swit
ch
es is called d
u
ty cy
cle. Same duty cycl
e will be achi
eved in prop
ose
d
conve
r
ter
co
nfiguratio
n d
ue to the identical
convert
e
rs. Mo
reove
r
, equal ICS and OVS ca
n be
achi
eved in
spite of the variou
s loa
d
condition
s.
Th
e config
urati
on of IPOS consi
dered in
this
pape
r co
mpri
sing of only
two BHB DC-DC co
nv
erte
rs but
can b
e
extended t
o
any numb
e
r
c
onverters
.
Figure 1. Block
Diag
ram o
f
IPOS
Figure 2. Pro
posed IPOS
BHB DC-DC
Config
uratio
n
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TELKOM
NIKA
ISSN:
2302-4
046
Input-Current
and Loa
d Voltage Shari
n
g
in
Input-Para
llel… (Am
i
r Mahm
ood Soo
m
ro)
3707
3. Numerical
Repre
sen
tation of ICS an
d OVS
Nume
ri
cal re
pre
s
entatio
n
of ICS and OVS can b
e
achieve
d
for IPOS BHB DC-DC
conve
r
ter
co
nfiguratio
n ta
king i
n
to co
nsid
erat
io
n F
i
gure
1. As
the input of
the co
nvert
e
r
config
uratio
n
is
con
n
e
c
ted i
n
pa
rallel,
the
r
efore
the
voltage
acro
ss e
a
ch
in
p
u
t of
converte
rs mu
st
be equal to total input voltage
V
in
. Similarly, the output side of
the co
nverte
r configu
r
atio
n is
con
n
e
c
ted in
seri
es,
as a
result th
e outp
u
t cu
rr
ent through
ea
ch
co
nverter mu
st
be
same
a
s
t
he
load current
i
0
. Since th
e voltage across ea
ch
converte
r is repre
s
e
n
ted
as
V
in1
and
V
in2
respe
c
tively, whe
r
ea
s the
curre
n
t throu
gh ea
ch
co
nverter
at the o
u
tput sid
e
is
sho
w
n
as
i
01
a
nd
i
02
res
p
ec
tively. Henc
e,
12
0
01
0
2
in
in
in
VV
V
ii
i
(
1
)
The total
inpu
t cu
rre
nt ge
n
e
rated
throug
h inp
u
t voltag
e is
i
in
which i
s
di
strib
u
ted
betwe
en
the two
inp
u
ts of th
e
conv
erter mod
u
le
s a
s
i
in1
an
d
i
in
2
res
p
ec
tively. In the
s
a
me way, the voltage
across the l
o
ad
(
V
0
) i
s
sh
ared
at th
e o
u
tput
si
de of each conve
r
ter as
V
01
and
V
02
res
p
ec
tively.
Thus,
12
00
1
0
2
in
i
n
in
ii
i
VV
V
(
2
)
The eq
ual a
m
ount of the
curre
n
t will b
e
sha
r
e
d
bet
wee
n
the inp
u
ts due to th
e identical
conve
r
ters an
d hen
ce the o
u
tput voltage will be shared
equally.
12
in
in
ii
(
3
)
01
02
VV
(
4
)
Equation (3
) and (4)
rep
r
esents that
equal
ICS a
nd OVS can
be achieve
d
by the
prop
osed IPOS BHB DC-DC
conve
r
ter.
4. Stable Control Schem
e
The sta
b
le
control
schem
e for a
c
hievi
ng eq
ual ICS
and OVS fo
r IPOS BHB
DC-DC
conve
r
ter
co
nfiguratio
n is demon
strate
d in Figur
e 3. It is obvious from Fi
gu
re 3 that ea
ch
converter
module has it
s own
cont
ro
ller. With the
hel
p of individual cont
rollers
each
module
will
detect th
e in
put cu
rrent a
nd the
com
m
on outp
u
t vol
t
age. The
ind
i
vidual contro
ller
con
s
i
s
ts
of
dual loo
p
co
ntrol for e
a
ch
module
so a
s
to obt
ain
e
d
fast dynami
c
re
sp
on
se a
nd stea
dy st
ate
respon
se. T
h
e individual
controlle
rs are
use
d
to
gen
erate the
dut
y cycle
s
for t
he switche
s
of
each mo
dule
with the
h
e
lp of
swit
ching frequ
en
cy. The
dut
y cycle fo
r
Q
1
and
Q
2
are
compl
e
me
nta
r
y, in the sa
me way the
duty cycle
s
f
o
r
Q
3
a
nd
Q
4
are
also co
mpleme
ntary. The
phen
omen
on
of generating
duty cycle
s
for switche
s
Q
1
,
Q
2
,
Q
3
and
Q
4
is illustrated in Figure 4.
A
ssu
ming
i
in1
is greate
r
i
in2
at any instant, then the erro
r
sig
nal
of input currents i
s
obtaine
d for module
#
01.
11
2
in
in
ii
i
(
5
)
Therefore, th
e referen
c
e value of the voltage ca
n be
descri
bed a
s
:
1
1
re
f
r
e
f
VV
K
i
(
6
)
Similarly, we can g
e
t the expressio
n
for
conve
r
ter mo
dule# 0
2
.
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ISSN: 23
02-4
046
TELKOM
NI
KA
Vol. 12, No. 5, May 2014: 3705 – 37
12
3708
22
1
in
i
n
ii
i
(
7
)
Hen
c
e,
2
2
ref
r
e
f
VV
K
i
(
8
)
It can be co
n
c
lud
ed with th
e help of Equ
a
tion (5
) to Equation (8) th
at:
12
ref
r
e
f
VV
(
9
)
As lo
ng
as th
e duty
cycle
i
s
con
c
e
r
ne
d,
c
onve
r
ter mo
dule#
02
will
have the
la
rg
er
duty
cycle
as
com
pare
d
to conv
erter m
odul
e
#
01. It happe
ns d
ue to the
fact that the d
ual loop
co
ntrol
operating i
n
t
he
situation
whe
r
e
V
ref1
is less than
V
ref2
for BHB
DC-DC
c
onverters
. It shows that
i
in2
is increasi
ng while
i
in1
i
s
decreasi
ng
with respect to time
. Thi
s
will continue
until both
currents
are
in equili
brium.
Hen
c
e, equal cu
rre
nt
sha
r
ing
at the input is
obt
ained. O
n
ce the current
s a
r
e
equal at the i
nput, the voltage
s at the output will also
be equal.
2
in
i
34
~
QQ
re
f
V
1
in
i
2
re
f
V
2
o
v
2
in
i
1
in
i
12
~
QQ
re
f
V
2
in
i
1
ref
V
1
o
v
1
in
i
Figure 3. Stable Co
ntrol S
c
hem
e
Figure 4. The
Phenome
n
o
n
of Gene
ra
ting Duty Cycl
es for Swit
ch
es
5. Simulations and Resu
lts
The
pro
p
o
s
e
d
control
sch
e
me, illu
strat
ed in
Fig
u
re
3, togethe
r
with IPOS BHB DC-DC
conve
r
ter hav
e be
en
simul
a
ted u
s
in
g
si
mpower tool
of
MATLAB. The spe
c
ifica
t
ions req
u
ired
to
simulate th
e conve
r
ter
con
f
iguration
hav
e been
sh
own
in Table
1. In ord
e
r to ob
serve th
e ste
ady
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
2302-4
046
Input-Current
and Loa
d Voltage Shari
n
g
in
Input-Para
llel… (Am
i
r Mahm
ood Soo
m
ro)
3709
state an
d dy
namic re
sp
o
n
se
of the
control
sc
hem
e, the IPOS
config
uratio
n
for BHB
DC-DC
conve
r
ter wa
s
simul
a
ted f
o
r
different l
o
ad
con
d
ition
s
. Base
d o
n
l
oad
co
ndition
s, the
sim
u
lat
e
d
results a
r
e cl
assified into three diffe
rent
catego
rie
s
which a
r
e de
scribed a
s
un
de
r:
Table 1. Spe
c
ificatio
ns
Parameters
Val
ue
Parameters
Val
ue
V
in
50V
V
0
200V
L 200µH
C
3
,C
4
,C
7
and
C
8
8µF
C
1
,C
2
,C
5
and
C
6
10µF
R
L
_
fu
l
l
50
Ω
f
s
20KHz
R
L
_
ha
l
f
25
Ω
5.1. At Full Load Condition
The
simulati
on results
at full load
con
d
ition f
o
r IPOS B
H
B DC-DC conve
r
ter
config
uratio
n
are
rep
r
e
s
ent
ed in Fi
gure
5. The
simul
a
tion re
sult fo
r ICS and
OV
S are
de
scrib
e
d
together
with output cu
rren
t sharin
g and
load voltage.
It is obvious from Figu
re 5
that during f
u
ll
load conditio
n
ICS is eq
u
a
l to 8A whe
r
ea
s the OV
S is equal to
100V. Furth
e
rmo
r
e, outp
u
t
curre
n
t is 4A
and the l
oad
voltage is
2
00V.The
re
su
lts obtain
ed t
h
rou
gh
simul
a
tion at full l
oad
con
d
ition are
demo
n
st
rate
d
in Figu
re 6
by
u
s
in
g t
he bl
ock
dia
g
ram
of IPO
S
BHB
DC-DC
conve
r
ter.
1
8
in
iA
2
8
in
iA
1
4
o
i
A
2
4
o
iA
1
10
0
o
vV
2
10
0
o
vV
200
L
VV
Figure 5. Simulation Results at Full Load
Conditio
n
:
(i) ICS, (ii) Outp
ut Cu
rrent, (ii) OVS, (iv)
Load Voltag
e
50
in
VV
1
50
in
VV
2
50
in
VV
1
100
o
VV
2
10
0
o
VV
20
0
L
VV
16
in
iA
1
8
in
iA
2
8
in
iA
1
4
o
iA
2
4
o
iA
4
o
iA
Figure 6. Block
Diag
ram a
t
Full Load Condition
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3710
5.2. Full Load to Half L
o
a
d
Condition
The b
ehavio
r of IPOS BHB DC-DC
co
nverter
confi
guratio
n i
s
sh
own
in Fi
gure 7
whe
n
the load i
s
ch
angin
g
from f
u
ll load to h
a
l
f
load conditi
on. The lo
ad
variation a
nd
the effect on t
h
e
ICS and
OV
S is d
e
scri
be
d in T
able
2. Equal I
C
S a
nd OVS i
s
o
b
se
rved
reg
a
r
dle
s
s of the
load
variation. The
result
s a
c
qui
red by sim
u
la
tion at
half load co
ndition
are de
mon
s
trated in Figu
re
8.
Table 2
Load Condition
Time Range
Load Value
ICS
OVS
Full Load
0 - 0.05 Sec
50 Ohms
8A
100V
Half Load
0.05 - 0.1 Sec
25 Ohms
16A
100V
1
8
in
iA
2
8
in
iA
2
16
in
iA
1
16
in
iA
1
4
o
iA
1
8
o
iA
2
4
o
iA
2
8
o
iA
1
10
0
o
vV
1
10
0
o
vV
2
10
0
o
vV
2
10
0
o
vV
20
0
L
VV
20
0
L
VV
Figure 7. Re
sults for Full L
oad to Half L
oad Conditio
n
: (i) ICS, (ii)
Output Cu
rre
n
t, (ii) OVS, (iv)
Load Voltag
e
50
in
VV
1
50
in
VV
2
50
in
VV
1
10
0
o
VV
2
10
0
o
VV
200
L
VV
32
in
iA
1
16
in
iA
2
16
in
iA
1
8
o
iA
2
8
o
iA
8
o
iA
Figure 8. Block
Diag
ram a
t
Half Load Condition
5.3. Half-full-half Load
Co
ndition
The results f
o
r IPOS BHB
DC-DC
co
nverter
co
nfigu
r
ation a
r
e
rep
r
esented
in F
i
gure
9
whe
n
the
loa
d
is re
peate
d
l
y
cha
ngin
g
from half l
oad
to full lo
ad
co
ndition. Th
e l
oad va
riation
and
the effect on
the ICS and
OVS is expre
s
sed in Ta
bl
e
3. Rega
rdle
ss of the load
variation, equ
al
ICS and OVS
is observed.
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TELKOM
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ISSN:
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046
Input-Current
and Loa
d Voltage Shari
n
g
in
Input-Para
llel… (Am
i
r Mahm
ood Soo
m
ro)
3711
Table 3
Load Condition
Time Range
Load Value
ICS
OVS
Half Load
0 - 0.03 Sec
25 Ohms
16A
100V
Full Load
0.03 - 0.07
Sec
50 Ohms
8A
100V
Half Load
0.07 - 0.1 Sec
25 Ohms
16A
100V
1
8
in
iA
2
8
in
iA
1
16
in
i
A
1
16
in
i
A
2
16
in
iA
2
16
in
iA
1
4
o
iA
2
4
o
iA
2
8
o
iA
2
8
o
iA
1
8
o
iA
1
8
o
iA
1
100
o
vV
1
100
o
vV
1
10
0
o
vV
2
100
o
vV
2
10
0
o
vV
2
100
o
vV
20
0
L
VV
20
0
L
VV
20
0
L
VV
Figure 9. Re
sults for Half-full-half Lo
ad
Con
d
ition:
(i)
ICS, (ii) Outp
ut Cu
rrent, (ii) OVS, (iv) Load
Voltage
6. Conclusio
n
The configu
r
ation propo
sed in thi
s
pa
per
for BHB
DC-DC
c
onv
erter is
IPOS
with the
stable
control
schem
e. Th
e
prim
e p
u
rp
o
s
e
of sta
b
le
control
sche
m
e
is to a
c
hi
eve eq
ual I
C
S a
nd
load voltag
e
sha
r
ing
und
er steady
st
ate
con
d
ition. Th
e main
obje
c
t
i
ve of the con
t
rol sch
e
me
h
a
s
been
a
c
hieve
d
not
only fo
r the full l
oad
but al
so fo
r t
he h
a
lf loa
d
.
The
re
spo
n
se of the
conv
erter
config
uratio
n
at differe
nt lo
ads ha
s
bee
n
ob
se
rved
i
n
simulat
i
o
n
re
sult
s.
S
a
t
i
sf
a
c
t
o
ry
simul
a
t
i
on
results at different loa
d
condition
s hav
e been
fou
n
d
. Therefo
r
e
it can be co
nclu
ded that
the
IPOS BHB
DC-DC
conve
r
ter
config
urat
ion in
c
onju
n
c
tion with
sta
b
le cont
rol scheme
ha
s go
od
dynamic a
n
d
steady state
resp
on
se. T
he two c
onv
erter mo
dule
s
have be
en
focused in this
resea
r
ch wo
rk for IPOS co
nfiguratio
n bu
t can be exte
nded to any n
u
mbe
r
.
Referen
ces
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Ayy
a
nar
,
Ramesh Giri,
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n.
Active Input–V
oltag
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o
ad–
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nt Sharin
g in Input-
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u
tput-Para
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