Indonesi
an
Journa
l
of El
ect
ri
cal Engineer
ing
an
d
Comp
ut
er
Scie
nce
Vo
l.
1
4
,
No.
2
,
Ma
y
201
9
,
pp.
653
~
660
IS
S
N: 25
02
-
4752, DO
I: 10
.11
591/ijeecs
.v1
4
.i
2
.pp
653
-
660
653
Journ
al h
om
e
page
:
http:
//
ia
es
core.c
om/j
ourn
als/i
ndex.
ph
p/ij
eecs
Des
i
gn o
f o
n
-
chip tempe
ra
ture
-
b
ased digit
al signal
processin
g
for custo
mized
wire
l
ess micro
co
nt
rolle
r
S.F.R. Faez
al,
M
.
N. Is
a,
S. T
ak
ing
, S.N
. Mo
hyar,
A.B.
Jambek,
A.
H
arun
School
of
Mi
cro
el
e
ct
roni
c Engi
n
ee
ring
,
Univ
ersiti
Mal
a
y
s
ia Perl
is
,
Mal
a
y
s
ia
Art
ic
le
In
f
o
ABSTR
A
CT
Art
ic
le
history:
Re
cei
ved
A
ug
27
, 201
8
Re
vised
N
ov
25, 2
01
8
Accepte
d
Ja
n
17
,
201
9
Dram
at
ic
rises
i
n
power
density
and
die
size
s
i
nside
s
y
stem
-
on
-
chi
p
(
SoC
)
design
hav
e
l
e
d
to
th
e
th
er
m
al
issue.
Hig
h
te
m
per
a
ture
s
or
unev
en
te
m
per
at
ur
e
dist
ribut
ions
m
a
y
r
esult
not
onl
y
i
n
re
liabilit
y
issues,
al
so
has
bec
om
e
th
e
bigg
est
issue
th
at
can
li
m
it
the
s
y
ste
m
per
form
anc
e.
Thi
s
paper
pre
sents
the
de
sign
and
sim
ula
ti
on
of
a
te
m
per
at
ur
e
-
base
d
di
git
al
signa
l
proc
essing
uni
t
for
m
oder
n
s
y
st
em
-
on
-
chi
p
d
esign
using
th
e
Ve
ril
og
HD
L
.
Thi
s
design
pro
vide
s
cont
inuou
s
m
onit
oring
of
te
m
per
at
ur
e
an
d
re
acts
to
spec
ified
condi
t
ions.
The
sim
ula
ti
on
of
th
e
sy
stem
has
been
done
on
S
y
n
ops
y
s
Software
.
Th
e
re
sult
s
howed
tha
t
te
m
per
at
ur
e
m
onit
oring
proc
ess
is
withi
n
th
e
t
empera
tur
e
ra
ng
e
d
ue
to
the
inc
orpo
ra
ti
on
of
an
int
e
r
rupt
-
base
d
s
y
stem a
nd
with
an
adv
antage
o
f m
ini
m
um
chi
p
a
re
a
r
equi
r
ed.
Ke
yw
or
ds:
Mi
cro
co
ntr
oller
Syst
e
m
-
On
-
Chip
Tem
per
at
ur
e
Mon
it
ori
ng
Copyright
©
201
9
Instit
ut
e
o
f Ad
vanc
ed
Engi
n
ee
r
ing
and
S
cienc
e
.
Al
l
rights re
serv
ed.
Corres
pond
in
g
Aut
h
or
:
Sit
i Farh
a
h
Ra
zanah B
inti
Fa
ezal
,
School
of Mi
cr
oelect
ronic E
nginee
rin
g,
Un
i
ver
sit
i M
al
ay
sia
Per
li
s,
02600, Pe
rlis,
Ma
la
ysi
a.
Em
a
il
:
far
haf
a
ezal
@g
m
ai
l.com
1.
INTROD
U
CTION
The
the
rm
al
is
su
e
bec
om
e
one
of
an
i
nev
it
a
ble
facto
r
in
co
ntem
po
rar
y
syst
e
m
-
on
-
chi
p
(
So
Cs) due
to
the
co
ntin
uous
increase
i
n
th
e
integrati
on
de
ns
it
y
and
po
wer
c
onsu
m
ption
of
S
oC
de
vices.
T
he
dis
sipate
d
powe
r
in
So
C
dev
ic
es
is
m
anifested
in
the
f
or
m
of
heat.
R
ise
in
he
at
de
nsi
ty
creati
ng
va
st
dif
ficult
ie
s
wh
ic
h
can lead
to
the
serio
us
t
her
m
al
pro
blem
ev
en t
hough
i
n
lo
w powe
r
a
pp
li
cat
ion
s
.
To
desc
ribe
th
e
relat
ion
sh
i
p
betwee
n
powe
r
consum
ption
a
nd
ju
nction
tem
per
at
ur
e
,
a
first
-
ord
e
r
expressi
on can
b
e e
xpres
sed
a
s:
T
j
= T
a
+
P
chip
x R
ja
(1)
Wh
e
re
Ta
is
t
he
te
m
per
at
ur
e
of
the
am
bie
nt
en
vir
onm
ent,
Pchi
p
is
t
he
total
powe
r
c
on
s
um
ption
inside
the
chi
p,
Rja
is
t
he
j
un
ct
ion
to
am
bie
nt
therm
al
resist
a
nce
an
d
Tj
i
s
the
der
ive
d
jun
ct
io
n
te
m
perat
ur
e.
Rja
can
be
m
od
el
ed
as
t
he
se
ries
resist
ance
from
j
un
ct
io
n
to
am
bient
in
diff
e
ren
t
par
ts
of
the
chip
.
A
nal
ogous
to elec
tric
al
r
es
ist
ance,
the
rm
a
l resist
ance ca
n be
de
fine
d
as:
R =
(2)
Wh
e
re
k
is
t
he
m
a
te
rial
’s
therm
al
con
du
ct
ivit
y,
L
is
the
le
ng
t
h
an
d
A
is
the
cr
os
s
-
s
ect
ion
al
area
of
t
he
cond
ucting p
at
h.
Substi
tuti
ng E
q
uatio
n
(
2)
i
nt
o
E
q
uation
(
1),
w
e
get:
Evaluation Warning : The document was created with Spire.PDF for Python.
IS
S
N
:
2502
-
4752
Ind
on
esi
a
n
J
E
le
c Eng &
Co
m
p
Sci,
Vo
l.
1
4
, N
o.
2
,
Ma
y
201
9
:
653
–
660
654
T
j
= T
a
+ P
chip
x
(3)
Ther
e
f
or
e,
T
j
is
relat
ed
to
the
rati
o
betwee
n
Pchip
an
d
A
at
wh
ic
h
the
powe
r
de
ns
it
y
of
the
chip
is
de
fine
d
[1
]
.
The
te
m
per
at
ur
e
of
t
he
chip
is
al
so
directl
y
propor
ti
onal
to
the
volt
age
and
cl
oc
k
f
re
quency.
T
he
perpetual
inc
r
ease
of
t
he
operati
ng
f
re
quency
increase
s
the
de
ns
it
y
of
dissipate
d
powe
r
[
2].
As
powe
r
c
onsu
m
ption
,
P is d
i
rectl
y propo
rtion
al
t
o
t
he op
e
rati
onal
fr
e
qu
e
ncy,
f by
the
fo
ll
owin
g equ
at
io
n:
P = c. V
2. f
+
Ps
(4)
Wh
e
re
c
is
scal
ing
co
ns
ta
nt
with
the
dim
ension
of
ca
pacit
ance
(F).
V
is
an
in
pu
t
volt
ag
e
and
Ps
is
the
sta
ti
c
powe
r dissi
pation w
hich
is t
he
pow
e
r
at
a
zer
o
cl
oc
k fr
e
que
ncy [
3].
Fr
om
this
eq
ua
ti
on
,
we
ca
n
i
de
ntify
that
if
w
e
wa
nt
to
dec
r
ease
the
fr
e
que
ncy
or
volt
age,
the
powe
r
into
the
c
hip
a
lso
w
ou
l
d
dec
rease,
as
well
as
the
powe
r
dissipated
as
he
at
.
Me
anwhil
e,
by
looki
ng
at
the
vo
lt
ag
e
int
o
th
e
chi
p,
we
c
an
see
it
has
a
qu
adr
at
ic
relat
ionship
to
t
he
po
wer.
T
hus,
a
ny
dec
reases
i
n
volt
age
hav
e
a
gr
eat
e
r e
ff
ect
on the
pow
e
r
t
han the l
inear
relat
ion
s
hip
of the
cloc
k.
More
ov
e
r,
cl
oc
k
f
re
qu
e
ncy
has
a
li
nea
r
r
el
at
ion
sh
i
p
to
the
po
wer
c
on
s
um
e
d
by
t
he
c
hip
.
By
lowe
rin
g
the
c
lock
fr
e
quenc
y,
the
pro
cess
or
runs
slo
wer,
the
process
or
exec
utin
g
fe
wer
i
ns
tr
uctio
ns
in
a
giv
e
n
ti
m
e p
eriod an
d
t
her
e
for
e d
ec
reasin
g
t
he
pow
e
r
as
n
ee
ded.
Local
ov
e
rheat
ing
i
n
on
e
s
pot
of
a
high
-
de
ns
it
y
ci
rcu
it
as
in
Fi
gure
1
s
uch
as
high
-
spe
ed
m
ixed
-
sign
al
ci
rc
uits,
can
ca
us
e
a
w
ho
le
syst
e
m
to
cras
h
due
to
cl
oc
k
s
ynch
ronizat
ion
pro
blem
s,
par
am
et
er
m
is
m
a
tc
hes
or
oth
e
r
c
oeffici
ent ch
a
nges
due
to
the
une
ve
n heat
-
up on a
sing
le
c
hip [
4,5].
Ov
e
r
heati
ng
ca
n
ha
ve
e
ff
ect
s
on
a
m
ic
ro
proc
essor.
Wh
e
n
tr
ansisto
rs
he
at
up,
m
or
e
cu
rr
e
nt
will
pa
s
s
thr
ough the d
e
vice. H
ig
h
c
urr
ents w
il
l bu
r
n ou
t t
ra
ns
ist
ors in a
process
or
, rui
ning the d
e
vi
ce [6
]
. F
urt
he
r
m
or
e,
transisto
r per
form
ance w
il
l de
cay
w
it
h
inc
rea
sing t
em
per
at
ur
e as i
n
the
gra
ph in
Fig
ur
e
2.
Figure
1
.
H
ots
po
t
of the
h
i
gh
-
de
ns
it
y ci
rcu
it
[1
]
The rapi
d
in
cre
ase in tem
per
at
ur
e
can
af
fect s
ever
al
as
pects
of the circ
uit
de
sign
;
(1)
The
ca
rr
ie
r
m
ob
il
it
y
of
a
tra
ns
ist
or
dec
reas
es
with
i
ncr
ea
sing
te
m
per
at
ure
at
w
hich
ca
n
lo
wer
the
dr
i
ve
c
urren
t a
nd leads
to
i
ncrea
sed dela
ys [
7]
.
(2)
Larg
e
sp
at
ia
l
var
ia
ti
ons
in
powe
r
c
on
s
um
ption
cau
sed
t
he
un
e
ve
nly
di
stribu
te
d
he
at
at
diff
e
ren
t
locat
ion
s
ca
n
m
ake
per
f
orm
ance
analy
sis
diff
ic
ult.
In
c
re
asi
ng
in
te
m
per
at
ur
e
al
s
o
cr
it
ic
al
to
the
desig
n of m
ixe
d
si
gn
al
a
nd a
na
log
ICs as
the
y are m
or
e se
nsi
ti
ve
to tem
per
at
ur
e
[1].
(3)
Higher
ju
nctio
n
te
m
per
at
ur
e
reduces
t
he
m
e
an
ti
m
e
to
fail
ur
e
(MTTF
)
for
the
de
vices,
wh
ic
h
has
a
la
rg
e im
pact on the
r
el
ia
bili
ty
of the
overall
syst
e
m
[
8].
Con
se
quently
,
therm
al
con
sider
at
io
ns
sho
uld
beco
m
e
on
e
of
the
im
po
rta
nt
par
ts
of
the
desig
n
process
.
In
thi
s
researc
h,
we
are
de
velo
ping
a
tem
per
at
ur
e
-
base
d
di
gital
sign
al
proce
ssing
I
P
ci
rcu
it
(
TDS
P
)
that
can
pr
ov
i
de
con
ti
nu
ous
m
on
it
or
ing
of
t
e
m
per
at
ure
in
So
C
a
nd
reacts
to
a
sp
eci
fie
d
conditi
on.
Mo
r
eov
e
r,
this
researc
h
c
ov
e
rs
Ver
il
og
HD
L
an
d
design
of
a
te
m
per
at
ur
e
-
base
d
dig
it
al
sign
al
pr
oc
essing
unit
for
an
on
-
chip
te
m
per
at
ure
m
on
it
or
in
g
syst
e
m
us
ing
Synopsys
s
of
t
war
e
.
T
his
ci
rc
uit
is
optim
iz
e
d
f
or
arc
hitec
ture
a
nd
ci
rcu
it
im
ple
m
enta
ti
on
to
fit
syst
em
-
on
-
c
hip
de
sig
ns.
T
her
e
f
or
e,
an
inter
rupt
-
base
d
syst
em
will
be
Evaluation Warning : The document was created with Spire.PDF for Python.
Ind
on
esi
a
n
J
E
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c Eng &
Co
m
p
Sci
IS
S
N:
25
02
-
4752
Desig
n of
on
-
c
hip
te
mp
e
ra
t
ure
-
base
d digit
al
sig
na
l
process
ing
f
or
c
us
to
mi
zed
wi
rel
ess…
(
S.
F.R
. F
aez
al
)
655
i
m
ple
m
ented.
Give
n
the
a
bove
co
ns
i
der
at
ion
s
,
an
a
rc
hitec
ture
based
on
t
he
previ
ous
resea
rc
h
[
10]
wit
h
sign
ific
a
nt ar
c
hitec
ture
e
nhan
ce
m
ents is pro
po
s
ed
.
Figure
2.
Fr
e
que
ncy
vs Tem
per
at
ur
e
[
9]
2.
RESEA
R
CH MET
HO
DOL
OGY
Fr
om
this
res
earch
,
the
dy
nam
ic
ther
m
al
m
anag
e
m
ent
is
the
best
op
ti
on
t
o
be
us
e
d
in
t
he
dev
el
op
m
ent
of
the
te
m
per
at
ure
-
base
d
di
gital
sign
al
proces
sing
unit
.
H
ow
ever,
the
syst
em
need
s
to
be
al
te
red
to
m
eet
the
s
pecifica
ti
on
ne
eded
in
a
cust
om
iz
ed
In
te
l
wireless
m
ic
rocon
t
ro
ll
er.
Ba
s
ed
on
the
pr
e
vious
researc
h
[
9],
th
e
si
m
ulati
on
is
done
by
us
in
g
the
Alte
ra
Q
ua
rtus
I
I
s
of
t
wa
re
an
d
s
uccessfull
y
i
m
ple
m
ent
ed
on
FPGA
DE2
-
70
bo
a
r
d.
F
or
t
his
pa
per
,
t
he
si
m
ula
ti
on
is
do
ne
usi
ng
the
S
ynopsys
softw
are
an
d
the
Te
chnolo
gy
Libra
ry
that
w
il
l
be
us
e
d
is
Sil
te
rr
a
CM
O
S
0.1
8
µm
Technolo
gy
Lib
r
ary.
I
n
s
umm
a
ry,
the
process
ste
ps
involve
d
in
the
d
e
velo
pm
ent o
f
tem
per
at
ur
e
-
base
d digit
al
s
ign
al
processi
ng
un
it
is
de
picte
d
in
Fig
ure
3
.
Figure
3.
Desi
gn m
et
ho
do
l
ogy
Evaluation Warning : The document was created with Spire.PDF for Python.
IS
S
N
:
2502
-
4752
Ind
on
esi
a
n
J
E
le
c Eng &
Co
m
p
Sci,
Vo
l.
1
4
, N
o.
2
,
Ma
y
201
9
:
653
–
660
656
Firstl
y,
after
finish
e
d
desig
ning
a
n
arc
hi
te
ct
ur
e
an
d
s
ource
c
od
e
s
f
or
TDSP,
t
he
functi
onal
si
m
ulati
on
will
be
done
usi
ng
Syn
op
sys
Ve
r
il
og
C
om
piler
Si
m
ulator
(
VC
S)
.
Lat
er,
to
c
he
ck
the
f
unct
io
nalit
y
and
flexi
bili
ty
of
the
sy
ste
m
,
TDS
P
will
be
i
m
ple
m
ented
to
DE
2
-
70
FP
GA
boar
d.
Ne
xt,
the
lo
gic
synthesis
will
be
done
us
in
g
Syn
op
sy
s
Desi
gn
Com
piler.
Gate
le
ve
l
ver
i
ficat
ion
is
do
ne
t
o
c
heck
f
or
a
ny
tim
ing
vio
la
ti
on.
I
f
no
ti
m
ing
viol
at
ion
s,
co
ntin
ue
with
ph
ysi
cal
design
im
plem
enta
ti
on
us
in
g
Syn
ops
ys
IC
Com
piler.
Af
te
r
finis
hed
with
IC
Com
piler
up
unti
l
routing
ph
a
se,
pr
oceed
with
DRC
an
d
LVS
us
in
g
Ca
li
br
e
to
chec
k
f
or
a
ny
error
s
.
Last
ly
,
pr
ocee
d
with
Sig
n
-
Off
Sta
ge,
c
on
sist
of
Lay
ou
t
Le
vel
Ver
ific
at
io
n
an
d
Post
Lay
ou
t
STA t
o chec
k
the
ti
m
i
ng v
i
olati
on
s
. If no t
i
m
ing
v
i
ol
at
ion
s,
t
he des
ign
is
r
ea
dy to t
ape
-
ou
t.
3.
PROP
OSE
D ARCHITE
CT
UR
E
In this sect
io
n,
the arc
hitec
tur
e of T
DS
P
and
it
s sp
eci
ficat
io
n wil
l be
discu
ssed.
3.1.
Bl
ock Di
ag
r
am
of T
DSP
The
bl
ock
dia
gr
am
of
the
te
m
per
at
ur
e
-
bas
ed
dig
it
al
signa
l
pr
ocessi
ng
ci
rcu
it
is
sh
own
in
Figu
re
4.
The bloc
k diag
ram
co
ns
ist
s of
sev
e
n
s
ub
-
m
od
ules
3.2.
Fu
nctio
n
The fu
nctio
n o
f
eac
h
s
ub
-
m
od
ules
is d
e
scri
bed in
detai
ls i
n
this
sub
-
sect
ion.
a.
In
te
rface
Regi
ste
r
:
This
uni
t
con
tr
ol
the
input
data
r
ecei
ved
a
nd
pro
vid
in
g
a
n
input
inter
fac
e
synch
ron
ously
to
pre
ven
t a
n
e
rror i
n recei
vi
ng
data
b.
Counter
: T
his
un
it
us
e
d
to
coun
t t
o 8 clo
ck
cy
cl
es in ord
e
r t
o
recei
ve
a
n
in
pu
t
from
A
DC.
c.
Volta
ge
to
T
e
mp
er
at
ur
e
M
odule
:
T
his
unit
con
ta
i
ns
a
lo
ok
-
up
ta
ble
to
c
onve
rt
the
in
put
A
DC
w
hich
is
in volt
age
val
ue
into
t
he
c
orre
sp
on
ding tem
per
at
ur
e
v
al
ue
i
n
Ce
lsi
us (
˚C).
d.
Program
mable
Watch
dog
U
ni
t
:
This
unit
use
d
to
m
on
it
or
t
he
te
m
per
at
ur
e
from
the
tem
per
at
ur
e
sen
sor
and react t
o
s
pe
ci
fic tem
per
at
ur
e
r
a
ng
e
s.
e.
In
te
rr
upt
Ge
ne
ra
tor
:
This
uni
t
pro
vid
es
data
outp
uts
t
hat
ar
e
rea
d
by
the
s
yst
e
m
CPU,
li
ke
te
m
per
at
ure
value
a
nd inte
r
rupt ty
pes.
f.
Ou
t
pu
t
C
onve
rte
r
:
This
un
it
co
nv
e
rt
the
ou
t
pu
t
i
nto
[
31:0]
bit
form
(inclu
ding
te
m
per
at
ur
e
val
ue
,
interr
up
t l
ow, i
nterru
pt
hi
gh).
g.
Fu
nction C
ont
ro
ll
er
: This
unit
co
nt
ro
ls t
he
i
nteracti
on
between t
he sy
ste
m
an
d
the
CP
U
.
Figure
4.
Bl
oc
k Diag
ram
o
f TDSP
4.
ARCHITE
CT
UR
E
ON A
M
BA BU
S
The
f
ull
chip
i
nteg
rati
on
for
TDS
P
syst
em
i
s
based
on
APB
Bus
Sp
eci
fic
at
ion
as
in
Fig
ur
e
5.
T
DS
P
will
us
e
the
A
MB
A
bus
prot
oco
l
as
their
bus
inter
face
be
cause
the
m
ic
r
ocontr
oller
wil
l
us
e
the
Adva
nced
Mi
cro
co
ntr
oller
Bus
Ar
c
hitec
ture
(
AMBA
)
bu
s
prot
oco
l.
T
he
T
DS
P
inte
rfac
e
needs
to
m
at
ch
with
Adv
ance
d
Perip
her
al
Bus
(A
PB)
s
pecifi
cat
ion
,
to
easi
ly
int
erf
ace
the
IP
with
the
m
ic
ro
c
on
tr
oller.
AP
B
is
par
t
of
the
AMBA
hiera
rc
hy
of
bu
se
s.
It
is
op
ti
m
iz
ed
to
reduce
t
he
c
om
plexit
y
of
int
erf
aci
ng
a
nd
m
ini
m
al
iz
e
the
po
we
r
consum
ption
.
Evaluation Warning : The document was created with Spire.PDF for Python.
Ind
on
esi
a
n
J
E
le
c Eng &
Co
m
p
Sci
IS
S
N:
25
02
-
4752
Desig
n of
on
-
c
hip
te
mp
e
ra
t
ure
-
base
d digit
al
sig
na
l
process
ing
f
or
c
us
to
mi
zed
wi
rel
ess…
(
S.
F.R
. F
aez
al
)
657
Figure
5.
F
ull Chip
In
te
gr
at
io
n of TD
SP
The
A
DC
will
conve
rt
a
vo
lt
a
ge
f
r
om
tem
pe
ratur
e
se
nsor
i
nto
e
qu
i
valent
8
-
bit
dig
it
al
volt
age.
Thes
e
8
-
bit
in
pu
ts
a
re
a
pp
li
ed
to
TDS
P
wh
e
re
TDS
P
will
m
on
it
or
t
he
i
nput
f
ro
m
A
DC
an
d
al
s
o
refe
ren
c
e
tem
per
at
ur
e
f
r
om
the
host
(i
f
a
vaila
ble)
i
nsi
de
the
syst
em
and
im
ple
ment
the
inter
rupt
-
based
s
yst
e
m
if
the
conditi
on
needed.
Th
e
pro
gra
m
m
ing
in
T
DS
P
is
done
by
Ver
il
og
H
DL
la
ngua
ge
and
that
buil
ds
TDS
P
syst
e
m
m
od
ule.
5.
RESU
LT
&
D
ISCUSS
IO
N
RTL
le
vel
sim
ulati
on
is
ge
ne
rated
by
Ver
il
og
C
om
piler
Sim
ula
tor
(
VCS
)
in
Sy
nops
ys
s
of
t
war
e.
T
he
RTL
is
the
lowe
st
le
vel
repr
esentat
ion
of
c
ircuit
ry
from
S
ynopsys
softw
are.
The
RTL
gen
e
rated
f
or
TDS
P
is
sh
ow
n
in
Fig
ur
e
6.
Me
an
wh
il
e,
the
VCS
sim
ulator
ge
ner
at
e
s
the
ou
t
pu
t
w
aveform
corres
pondin
g
to
the
input
change
of
A
D
C
or
refe
re
nc
e
tem
per
at
ur
e
on
sim
ulati
o
n
to
chec
k
th
e
functi
on
al
it
y
of
the
syst
em
.
This
si
m
ulati
on
is e
xecu
te
d by ra
ndom
v
al
ues
chose
n
in
in
pu
ts.
The wa
vefor
m
si
m
ulati
on
is s
how
n
in
Fig
ure
7
.
Figure
6
.
RTL
Si
m
ulati
on
of
TDS
P
Ba
sed
on
Fig
ure
7,
from
0
ns
–
2000
ns,
TDS
P
will
rec
ei
ve
8
-
bit
inpu
ts
from
AD
C,
wh
ic
h
is
i
n
decim
al
inp
ut
‘1’.
A
fter
m
onit
or
in
g
process
,
no
inter
rupt
i
s
pro
duced
at
PRDATA
is
32’
h000
0_0000.
This
happe
ns
beca
use
the
PRESE
Tn
is i
n
act
ive
low
m
od
e.
Me
anwhil
e,
f
r
om
20
00
ns
–
2500
ns,
the
re
are
sli
gh
tl
y
del
ay
in
the
tem
per
at
ur
e
m
on
it
ori
ng
to
beg
i
n
after
the
syst
e
m
has
been
res
et
.
The
real
m
on
it
or
i
ng
proc
es
s
sta
rts
from
25
00
ns
f
or
the
new
in
pu
t
valu
e
from
Evaluation Warning : The document was created with Spire.PDF for Python.
IS
S
N
:
2502
-
4752
Ind
on
esi
a
n
J
E
le
c Eng &
Co
m
p
Sci,
Vo
l.
1
4
, N
o.
2
,
Ma
y
201
9
:
653
–
660
658
the
A
DC.
Fro
m
43
00 n
s
–
6000 n
s
,
T
DS
P
r
ecei
ve
d
8
-
bit
in
puts from
ADC
,
in
t
he
decim
al
input of
‘37’
.
A
fter
m
on
it
or
the
re
al
value
i
n
the
look
-
up
ta
ble,
the
te
m
per
at
ure
tur
ns
ou
t
t
o
be
in
an
a
ve
ra
ge
-
te
m
per
at
ur
e
range
.
Th
us
,
no
inter
rupt
is
produc
ed
at
PRDA
T
A.
T
DS
P
will
on
ly
sen
d
the
cur
re
nt
te
m
pe
ratur
e
value
to
CPU
thr
ough the
PR
DA
T
A o
utput
sign
al
s.
Fr
om
6000
ns
–
80
00
ns
,
T
D
SP
receive
d
8
-
bit
inputs
from
AD
C,
in
t
he
de
cim
al
inp
ut
of
‘43’.
Af
te
r
m
on
it
or
the
re
al
value
in
the
look
-
up
ta
ble,
the
tem
per
at
ure
tur
ns
ou
t
to
be
in
the
high
-
te
m
per
at
ur
e
range
.
TDS
P
w
il
l t
rig
ger the
8 bit
s i
nterru
pt in PR
DA
T
A.
Last
ly
,
fr
om
80
00
ns
–
1000
0
ns,
TD
SP
will
receive
an
in
pu
t,
ref
e
re
nce
tem
per
at
ure
fro
m
the
ho
st
,
thr
ough
P
WDATA
sig
nal.
T
he
in
pu
ts
pin
f
ro
m
the
AMBA
su
c
h
as
P
E
NA
BL
E,
P
WR
ITE,
a
nd
PSE
L
will
be
trigg
e
red
in
order
f
or
T
DS
P
t
o
receive
an
in
pu
t
f
ro
m
PWDATA
in
put
sig
nal.
The
re
fer
e
nce
tem
per
at
ure
will
be
set
by
the
ho
st
as
the
hig
he
st
tem
per
at
ur
e
.
Th
us
,
a
fter
the
refe
re
nce
tem
per
at
ur
e
is
set
,
the
ref
e
r
enc
e
tem
per
at
ur
e
w
il
l
be
com
pared
t
o
the
real
te
m
per
at
ur
e
r
ecei
ved
f
ro
m
t
he
AD
C.
T
D
SP
ca
n
pro
vide
the
con
ti
nu
ous
te
m
per
at
ur
e
m
on
it
or
in
g
proce
ss
as
long
as
the
data
receive
d
from
AD
C.
Figure
8
s
how
s
the
gate
le
vel sch
em
at
i
c on
on
e
of t
he
sub
-
m
odules i
n
T
DS
P
afte
r v
erifica
ti
on of t
he gate
is c
omplet
ed.
Figure
7.
RTL
Si
m
ulati
on
of
TDS
P
Figure
8.
Gate
Level Sc
hem
atic D
ia
gram
f
or
Lo
ok
-
U
p Tabl
e Sub
-
Mo
du
le
.
Evaluation Warning : The document was created with Spire.PDF for Python.
Ind
on
esi
a
n
J
E
le
c Eng &
Co
m
p
Sci
IS
S
N:
25
02
-
4752
Desig
n of
on
-
c
hip
te
mp
e
ra
t
ure
-
base
d digit
al
sig
na
l
process
ing
f
or
c
us
to
mi
zed
wi
rel
ess…
(
S.
F.R
. F
aez
al
)
659
Me
anwhil
e,
Figure
9
sho
ws
the
final
la
yout
of
TDSP
after
ph
ysi
cal
i
m
pl
e
m
entat
ion
in
IC
Com
piler
is
com
plete
d.
The
process
of
physi
cal
i
m
ple
m
entat
ion
be
gin
s
with
flo
or
pla
nn
i
ng,
place
m
ent
of
sta
nd
a
r
d
cel
ls,
Cl
ock
Tr
ee
Synthesis
(
CTS)
an
d
la
stl
y
the
routing.
Table
1
s
hows
the
com
par
iso
n
of
the
s
pecif
ic
at
ion
of the lay
out
on the
lat
est
arc
hitec
ture
c
om
par
ed
to pre
viou
s ar
c
hitec
ture [
9].
Ba
sed
on
Ta
ble
1,
the
re
are
diff
e
re
nces
in
te
rm
s
of
la
yout
siz
e.
This
is
because
both
a
rch
it
ect
ure
s
us
in
g
the
dif
fe
ren
ce
te
ch
nolo
gy
li
br
ary.
Di
f
fer
e
nt
fou
ndry
has
dif
fer
e
nt
siz
es
of
sta
nda
rd
cel
ls.
More
ov
e
r
,
there
are
sli
gh
tl
y
diff
ere
nt
in
te
rm
s
of
total
power
,
t
he
reason
is,
the
la
yout
of
t
he
la
te
st
arch
it
ect
ur
e
is
op
ti
m
iz
ed
in term
s o
f
P
ower a
nd D
esi
gn fo
r Te
st (
DF
T
).
Ta
bl
e
1
.
L
a
y
out
Speci
fi
ca
t
ions
Sp
ecif
icatio
n
s
L
ATEST
A
RC
HITEC
TURE
Previo
u
s Architect
u
re
[
9
]
Size of
lay
o
u
t (
W
it
h
o
u
t I
O Pad)
1
0
0
µ
m
(w
)
x
96
µ
m
(h)
3
0
0
µ
m
(w
)x3
0
0
µ
m
(h)
Inp
u
t
Vo
ltag
e (
V)
1
.8
1
.8
Clo
ck
Fr
eq
u
en
cy
(
MHz)
16
16
Total Po
wer
(
m
W
)
1
.44
6
e
-
06
6
.49
1
6
e
-
02
Techn
o
lo
g
y
L
ib
rary
Silterr
a
TSM
C
Figure
9.
Fina
l
Layo
ut of a
n 8
-
bit T
DS
P
unit
6.
CONCL
US
I
O
N
A
tem
per
at
ure
-
base
d
dig
it
al
sign
al
pr
ocessin
g
sim
ulatio
n
ha
s b
een
done u
sing
Ver
il
og HDL code fo
r
the
pur
pose
of
si
m
ulati
on
in
S
ynopsys.
S
uch
ty
pe
of
im
ple
m
entat
ion
can
be
us
e
d
wit
h
di
ff
ere
nt
ap
plica
ti
on
s
,
su
c
h
as
tem
per
at
ur
e
c
on
t
ro
l
and
m
on
it
or
i
ng
syst
e
m
.
Thus,
this
desig
n
pro
vid
es
an
in
tric
at
e
con
trol
and
op
ti
m
al
therm
a
l
m
anag
e
m
ent
on
syst
em
-
on
-
chip
(SoC)
devi
ces,
upon
wh
i
ch
a
com
plete
t
her
m
al
m
anage
m
ent
syst
e
m
f
or
m
od
er
n
c
om
pu
te
r desig
ns
ca
n be
i
m
ple
m
ented
with a
n
a
dv
a
nt
age
of m
ini
m
u
m
ch
ip ar
ea
re
qu
i
red.
ACKN
OWLE
DGE
MENTS
This
work
is
s
upporte
d
in
pa
rt
by
Tal
e
ntco
r
p
Ma
la
ysi
a
gr
a
nt
al
so
c
ollab
orat
ed
with
In
te
l
Ma
la
ysi
a
and CED
EC U
SM f
or
3D
(D
e
m
and
, D
rive
n,
and D
e
velo
p)
pro
gr
am
.
REFERE
NCE
S
[
1
]
Li
u.
W
,
Nanna
r
el
li
A,
“
Pow
er
a
nd
The
rm
al
Ma
nage
m
ent
of
S
y
stem
-
on
-
Chip,
”
Te
chn
ic
a
l
Unive
rsit
y
of
Denm
ar
k,
DTU,
2011.
Evaluation Warning : The document was created with Spire.PDF for Python.
IS
S
N
:
2502
-
4752
Ind
on
esi
a
n
J
E
le
c Eng &
Co
m
p
Sci,
Vo
l.
1
4
, N
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2
,
Ma
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201
9
:
653
–
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660
[
2
]
M.
Szer
m
er,
Z.
Kulesz
a
,
M.
Janic
ki
,
and
A.
Napie
r
al
ski,
“
Te
st
AS
IC
for
Rea
l
-
Ti
m
e
Esti
m
at
ion
of
Ch
i
p
Te
m
per
at
ur
e”, T
ec
hni
ca
l
Univer
s
ity
of
Lod
z, T
U
L,
vo
l. 3, p
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9
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[
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]
N.H.E
W
este
,
D.M.
Harri
s,
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d
CMO
S
VLSI
Design
A
Circ
uit
s
and
S
y
stem
Perspec
ti
v
e,
4th
ed.
Boston,
MA
:
Addison W
esley
,
2011
.
[Onlin
e]
Avail
ab
le
:
Safa
r
i
e
-
book.
[
4
]
H.
Chiue
h
,
J.
Drape
r,
L.
Luh,
and
J.
Chom
a
Jr.,
“
A
the
rm
a
l
evalua
t
ion
of
int
eg
r
at
ed
ci
r
cuits:
On
-
chi
p
offs
et
te
m
per
at
ur
e
m
ea
surem
ent
and
m
odel
ing,
”
in
Proc.
2nd
Inte
r
nat
ion
al
W
orkshop
on
Design
of
Mixed
-
Mode
Inte
gra
te
d
Circ
u
i
ts
and
Appl
ications
,
1998,
pp.
1
09
–
113.
[
5
]
V.
Szekel
y
,
M
.
Renc
z
,
and
B.
C
ourtoi
s,
“
The
rm
al
t
esti
ng
m
et
ho
ds
to
in
cr
ea
se
s
y
stem
re
liabilit
y
,
”
in
Proc.
13th
I
E
EE
SEMITHERM Sy
m
posium
,
1997
,
pp
.
210
–
217
.
[
6
]
E.
W
ir
th, “The
r
m
al
Mana
gemen
t
in
Embedde
d
Sy
stems
T
abl
e
of
Conte
nts,
”
2004
.
[
7
]
A.
Ajami,
K.
B
ane
rj
ee,
and
M.
Pedra
m
,
“
Modeli
ng
and
an
aly
s
is
of
nonunifor
m
subs
tra
te
te
m
per
at
ur
e
eff
ects
on
globa
l
ULSI
int
e
rc
onnects,”
IE
E
E
Tra
nsac
ti
ons
on
Com
pute
r
-
Aided
Design
of
Inte
gra
t
ed
Circ
ui
ts
and
S
y
stems
,
vol.
24,
no
.
6
,
pp
.
84
9
–
861,
Jun.
200
5
[
8
]
R.
Visw
ana
th,
V.
W
akha
rka
r,
A.
W
at
we,
and
V.
Le
bonheur
,
“
The
rm
al
Perfor
m
anc
e
Chal
l
eng
es
from
Sili
con
to
S
y
stems
,
”
In
te
l
Te
chno
log
y
Jour
nal
,
(Q3),
2000.
[
9
]
C.
Be
la
d
y
,
“
Cooli
ng
and
Pow
er Cons
ide
ra
ti
ons
f
or
Sem
ic
onduct
o
rs Int
o
th
e
b
ex
t Cent
ur
y
,
”
pp
.
10
0
–
105,
2001
.
[
1
0
]
S.
F.
R.
Fae
za
l
,
M.
N.
Md
Isa
,
A.
Harun
,
S.
N
.
Moh
y
ar,
and
A.
B.
Jam
bek
,
“
On
-
chi
p
t
empera
ture
-
b
ase
d
dig
i
ta
l
signal
pro
ce
ss
in
g
for custom
iz
ed
wire
l
ess m
ic
roc
ontrol
ler,” E
PJ
W
eb
Conf.
,
vol
.
162,
p
.
01071
,
2
017.
BIOGR
AP
HI
ES OF
A
UTH
ORS
Siti
Farha
h
Raz
a
nah
Bint
i
Faezal
is
gra
duat
ed
wit
h
B.
Eng
(Hons
.
)
Microe
lectr
oni
c
Engi
nee
ri
ng
from
Univer
sit
y
Malay
s
ia
Perl
is
(UniMA
P)
in
2
016.
Curre
nt
l
y
,
she
is
cont
inui
n
g
her
M.Sc
i
n
the
sam
e
unive
rsit
y
.
Her
re
sea
r
ch
int
er
est
is
on
designi
ng
a
te
m
per
at
ure
base
d
digi
ta
l
sign
a
l
proc
essing
for
sy
stem
-
on
-
ch
ip.
Dr.
Mohd
Naz
rin
Md
Isa
is
a
se
nior
le
cturer
in
t
he
School
of
Microe
l
ec
tron
ic
En
gine
er
ing
at
Univer
siti
Ma
lay
sia
Perli
s
(Uni
MA
P).
Curre
ntly
,
he
is
a
m
ember
of
Int
egr
a
ted
Circ
ui
ts
and
S
y
stem
Design
(ICAS
e)
group.
His
re
sea
rc
h
i
nte
re
sts
include
re
conf
igur
abl
e
arc
hitec
ture
s
,
bi
oinformatics
a
nd
computat
ion
al
bio
log
y
,
f
ie
ld
progra
m
m
abl
e
gat
e
arr
a
y
(FP
GA
)
and
AS
IC
design.
He
gr
ad
uat
ed
h
is
doct
or
at
e
stud
y
from
t
he
Univer
sit
y
of
Edi
nburgh,
Sco
tl
and
,
UK
in
2013.
His
PhD
the
sis
ent
it
l
ed
“
High
Perform
anc
e
Rec
onf
igura
b
le
Archi
t
ec
tur
es
fo
r
Biol
ogical
Sequenc
e
Align
m
ent
s”.
Evaluation Warning : The document was created with Spire.PDF for Python.