Intern
ati
o
n
a
l
Journ
a
l of
Re
con
f
igur
able
and Embe
dded
Sys
t
ems
(I
JRES)
V
o
l. 3,
N
o
.
2
,
Ju
ly 20
14
, pp
. 62
~75
I
S
SN
: 208
9-4
8
6
4
62
Jo
urn
a
l
h
o
me
pa
ge
: h
ttp
://iaesjo
u
r
na
l.com/
o
n
lin
e/ind
e
x.ph
p
/
IJRES
Design and Development of
ARM
9 E
valu
a
tion Ki
t for
Embedded Applications
Ni
khi
l
Al
e
x
T
h
om
as
*,
Sa
nk
et
Dessai
*
,
S.
G. S
h
i
v
a Pr
as
ad
Y
a
d
a
v
*
*
,
S
h
i
l
p
a
Ch
aud
h
a
ri
*
*Departm
ent of Com
puter
S
c
ien
ce and
Engineering, Facu
lty
of
Engineer
ing an
d
Techno
log
y
, M.S.
Ra
ma
ia
h Sc
hool
of Advanced Stu
d
ies, B
a
ngalore,
India
** Departm
e
n
t
o
f
Telecom
m
unication
Engin
eer
in
g, M.S.
Ram
a
i
a
h
Institut
e
of
T
e
chnolog
y
,
B
a
ngal
o
re,
India
Article Info
A
B
STRAC
T
Article histo
r
y:
Received
Ma
r 4, 2014
Rev
i
sed
May 11
, 20
14
Accepte
d
J
u
n 2, 2014
In contrast with
low end micropr
ocessor,
ARM9 core is qu
ite a s
ophisticated
processor. Th
e Evalu
a
tion k
i
t play
s
an imp
o
rtant ro
le in
the prototy
p
e
development an
d verification of
the s
y
stem
design before tak
i
ng
to its actual
s
y
stem develop
m
ent hence it’s provide
better confidence to the designer.
In
this paper a pro
j
ec
t for the Eva
l
uati
on kit has been designed f
o
r embedded
s
y
stem engineer to impl
em
ent and confirm
the function
a
lit
y of th
eir opera
ting
s
y
s
t
em
s
which
could
lead
to
a
com
f
ortable
d
e
plo
y
ment. The independ
ent
m
odules for the interf
aces of th
e ARM9 processo
r have been d
e
si
gned and the
schematics hav
e
been d
e
velop
e
d
using OrCAD.
From
the tested
schem
a
tics
designed in OrCAD, the rela
ted
PCB is
designed using CADSTAR. An eight-
lay
e
r board is designed for its sig
n
al in
tegr
it
y and
com
p
lexit
y
of t
h
e schem
a
tic
designed.
The d
e
signed PCB layer is then
cal
ibra
ted and Gerb
er f
iles
ar
e then
made and passed on the PCB b
o
ard manuf
actur
er for PCB fabr
ication. Th
e
PCB board m
a
de is th
en t
e
sted
for int
e
rconn
ec
tion con
tinui
t
y
using m
u
lti-
meter as
the com
ponents ar
e
load
ed on
to
the boar
d
.
Keyword:
ARM
9
CADS
TAR
Ev
alu
a
tion
k
it
OrC
A
D
PCB
SDRAM
Copyright ©
201
4 Institut
e
o
f
Ad
vanced
Engin
eer
ing and S
c
i
e
nce.
All rights re
se
rve
d
.
Co
rresp
ond
i
ng
Autho
r
:
Sanket De
ssai,
Depa
rt
em
ent
of C
o
m
put
er
En
gi
nee
r
i
n
g,
M.S.Ram
a
iah
Scho
o
l
of
A
dvan
ced
Stud
ies,
#470-P, Peeny
a
Industrial
Area, Pee
n
ya 4
th
Ph
ase,
Bang
al
u
r
u
-
56
005
8
Karnataka
,
India.
Em
a
il: san
k
e
tdessai@g
m
ail.c
o
m
1.
INTRODUCTION
Ove
r
t
h
e
past
f
e
w deca
des, e
m
bedded sy
st
e
m
s have bec
o
m
e
i
n
creasi
ngl
y
com
m
on i
n
every
d
ay
l
i
f
e.
Tel
e
vi
si
on re
m
o
t
e
s,
al
ar
m
clocks,
cars a
n
d
m
obi
l
e
pho
ne
s cont
ai
n
just
a
m
i
nut
e han
d
f
ul
o
f
t
h
e em
b
e
dde
d
sy
st
em
s peo
p
l
e
enc
o
unt
er
da
i
l
y
. Em
bedde
d
sy
st
em
s are
o
f
t
e
n
re
qui
re
d
t
o
per
f
o
r
m
t
a
sks wi
t
h
i
n
a
b
o
u
nde
d
t
i
m
e
fram
e
. For a sim
p
l
e
dev
i
ce such as a r
e
m
o
t
e
cont
r
o
l
,
t
h
i
s
i
s
not
a part
i
c
ul
arl
y
de
m
a
ndi
n
g
re
qui
rem
e
nt
.
Howe
ver, for
devices t
h
at are require
d
to
proces
s larg
e
vo
lu
m
e
s o
f
d
a
ta, m
u
ch
m
o
re atten
tio
n
need
s
to
b
e
gi
ve
n t
o
pe
rf
o
r
m
a
nce.
Th
e
ARM9 Evalu
a
tio
n
Kit is
a co
m
p
lete syste
m
-o
n
-
ch
ip bu
ilt aroun
d th
e ARM9 Thu
m
b
p
r
o
cesso
r.
It incorporates
a rich set of syste
m
and application peripherals and standa
rd interfaces in orde
r to provide a
si
ngl
e-c
h
i
p
dri
v
en s
o
l
u
t
i
o
n f
o
r a wi
de
ran
g
e of c
o
m
put
e-i
n
t
e
nsi
v
e ap
pl
i
cat
i
ons t
h
at
requi
re m
a
xim
u
m
fun
c
tion
a
lity at
m
i
n
i
m
u
m
p
o
w
er con
s
u
m
p
tio
n at lowest co
st.
Atm
e
l Co
rp
oration h
a
d
an
nou
n
c
ed
th
e
AT
91SAM
9260, the first m
e
m
b
er of a
pin-com
p
atible AR
M9-based m
i
croc
ontroller
fa
m
i
ly that sha
r
es the
sam
e
pro
g
ram
m
i
ng m
odel
as AR
M
7
-
b
ase
d
cont
rol
l
e
rs
,
al
l
o
wi
ng
di
rect
m
i
grat
i
on bet
w
een c
ont
rol
l
e
rs base
d
on
di
ffe
rent
AR
M
cores
.
The AT
9
1
S
A
M
9
2
60 al
s
o
su
ppo
rts d
e
termin
istic, real-ti
m
e
o
p
e
ration, o
f
fers
su
perv
isor
y fun
c
tio
ns, and
h
a
s th
ird
-
p
a
r
t
y R
T
O
S
supp
or
t
co
m
p
arab
le
to
th
o
s
e o
f
8-b
it
co
n
t
ro
llers. Develo
p
e
d
fo
r hi
g
h
l
y
-c
on
nect
ed i
m
age-pr
ocessi
ng a
p
pl
i
cat
i
ons su
c
h
as poi
nt-of-sale ter
m
inals, Ethernet
-base
d
IP
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
089
-48
64
IJR
E
S V
o
l
.
3, No
. 2,
J
u
l
y
20
1
4
:
6
2
– 75
63
c
a
me
r
a
s
,
an
d ba
r
co
d
e
r
e
ad
er
s,
th
e AT
91
SAM9
26
0 in
teg
r
ate
s
a
2
0
0
MI
PS
A
R
M9
26
E
J
-S
c
o
r
e
w
ith
: a
c
a
me
r
a
interface; se
ve
n USARTs; 10/100 Et
he
rnet
MAC; 12 Mbps USB de
vice a
nd
host controller with
on-c
hip
transceive
rs; e
x
ternal bus i
n
terface
supporting SDRA
M, Flash, NAND
Flash
with
built-in ECC, SD,
SDIO,
and M
u
ltim
e
dia Card i
n
terfac
e
(M
M
C
); thre
e sy
nch
r
on
o
u
s
serial con
t
ro
llers (SSC); two
m
a
ster/slav
e
Serial
Peripheral Inte
rfaces (SP
I); a three-
c
h
a
n
nel 16-bit tim
e
r/counte
r
; two-wire
interface (T
WI); and
IEEE
1149.
1
JTAG
Boun
dary Scan
on
all dig
ital p
i
n
s
as sh
own
in Figur
e 1
.
Fi
gu
re 1.
B
l
oc
k Di
ag
ram
of AT
91S
AM
92
6
0
[1]
Th
e in
ter
n
al
bu
s
b
a
ndw
id
th
o
f
t
h
e AT91
SA
M92
6
0
is m
a
x
i
mized
b
y
24
D
M
A
ch
annels an
d a f
i
v
e
-
layer
h
i
gh
-
s
p
e
ed
bu
s m
a
tr
ix
. I
t
co
nn
ect
s all masters an
d
sl
av
es in
th
e
syste
m
in
a p
a
rallel fash
ion
an
d
en
ab
les
dat
a
t
r
ans
f
ers
bet
w
ee
n pe
ri
phe
ral
s
an
d o
n
- a
nd
of
f-c
hi
p m
e
m
o
ri
es
wi
t
h
o
u
t
any
C
P
U i
n
t
e
r
v
e
n
t
i
on.
A
p
r
og
ramm
ab
le
arb
iter m
a
n
a
g
e
s th
e p
r
iorities b
e
tween
th
e b
u
s
m
a
sters. Hig
h
l
y critical i
n
terrup
t rou
tines can
b
e
lo
ck
ed
in th
e
1
6
k
B
yte i
n
stru
ctio
n cach
e
,
gu
aran
teein
g
a
d
e
term
in
i
s
tic respon
se t
i
m
e
to
in
terrup
ts.
A
sy
st
em
cont
r
o
l
l
e
r p
r
ovi
des a
f
u
l
l
com
p
l
e
m
e
nt
of
su
per
v
i
s
ory
f
unct
i
o
ns
t
h
at
i
n
cl
ude
s
an
8
-
l
e
vel
p
r
i
o
ri
t
y
interr
upt
co
ntr
o
ller, RC
-oscil
lator,
PLLs
,
re
al-tim
e peri
od
ic in
terv
al an
d
watchd
og ti
m
e
rs,
reset and
shu
t
do
wn
cont
rol
l
e
rs
, an
d bac
k
up
re
gi
s
t
ers. T
h
e s
hut
d
o
w
n
c
ont
rol
l
e
r
put
s t
h
e p
r
oc
essor
i
n
a
n
ul
t
r
a-l
o
w
po
we
r
m
ode,
typ
i
cally less t
h
an 10
uA.
At
mel
'
s SAM9
micro
c
on
tro
lle
rs a
r
e the
fir
s
t ARM
9
-b
ased
micro
c
on
tro
llers with
Flash
m
e
m
o
r
y
in
tegr
ated
on
th
e sam
e
ch
ip
. Th
e AT91
SAM9
26
0
h
a
s th
i
r
d-
p
a
r
t
y RTOS supp
or
t fr
o
m
G
r
een
Hills So
ftware, Men
t
o
r
Graphics an
d
Micrium
.
Co
m
p
ile
r/d
e
b
ugg
ers are av
ailab
l
e fro
m
Green
Hills Software,
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
RES
I
S
SN
:
208
8-8
7
0
8
Desi
g
n
a
n
d
De
vel
op
ment
of
A
R
M9 Eval
uat
i
o
n
K
i
t
f
o
r Em
be
dde
d Ap
pl
i
c
at
i
ons
(
S
anket De
ssai)
64
A
R
M, K
e
il, IA
R System
s a
n
d
an
y co
m
p
lian
t
A
R
M926
EJ-
S
co
m
p
iler
.
W
i
nd
ow
s CE
an
d
Linu
x
op
er
atin
g
syste
m
support is
also
pr
ov
id
ed
.
The E
v
al
uat
i
o
n ki
t
e
n
abl
e
s
real
t
i
m
e
code
de
vel
o
pm
ent
an
d e
v
al
uat
i
o
n
.
It
s
u
pp
o
r
t
s
t
h
e
AT9
1
S
AM
9
260
Arm
9
Based 32
b
it RISC
Micro
c
on
tro
ller. Th
e ARM
9
Ev
alu
a
tion
B
o
ard will be
b
u
i
lt with
the Atm
e
l AT91SAM9260 ARM9 Microc
ontroller. The e
v
aluation board w
oul
d features interfaces like USB
,
Serial and Et
he
rnet.
2.
REQU
IRE
M
ENT
A
N
A
LY
SIS AN
D DES
I
GN
The
prim
ary goal of t
h
is
pr
o
j
ect
i
s
t
o
de
vel
o
p
a
har
d
ware
pl
at
f
o
rm
pri
m
ari
l
y
t
a
rget
ed
at
ope
rat
i
n
g
syste
m
testin
g
.
Th
e ARM
9
Ev
alu
a
tion
Kit en
ab
les th
e ev
al
u
a
tio
n of and
co
d
e
d
e
v
e
l
o
pmen
t for app
licatio
n
s
ru
n
n
i
n
g o
n
a
n
AT
91S
AM
92
6
0
de
vi
ce. T
h
e
At
m
e
l
AT9
1
S
A
M
9
26
0 i
s
ba
sed
on t
h
e AR
M
9
2
6
EJ
-S
pr
o
cesso
r,
with 8K byte instruction and 8K
byte data cache m
e
m
o
ries
. AT91SAM
9
2
60
operates at 210 MIPS with a 190
M
H
z cl
ock.
F
eat
ures o
f
AT
91
SAM
9
2
6
0
i
n
cl
u
d
e 8
K
by
t
e
s of SR
AM
and
32
K by
t
e
s of R
O
M
wi
t
h
si
ngl
e
cycle access at m
a
xim
u
m processor or
bus
s
p
eed, togethe
r
with a
n
exte
rnal bus i
n
te
rfac
e with c
ont
roll
ers for
SDR
A
M
a
n
d
st
at
i
c
m
e
m
o
ri
es i
n
cl
udi
n
g
NA
N
D
Fl
ash
and C
o
m
p
act
Fl
ash AT
91
S
A
M
9
26
0
pr
oc
essor
’
s
extensi
v
e pe
ripheral set include US
B Full Speed Host and Device interfac
es, a 10/
10
0 B
a
se T Et
her
n
et
M
A
C
,
Im
age Sens
or
Interface, Multim
e
dia Ca
rd Interface (MCI), Synchronous
Se
rial Cont
rolle
rs (SSC),
USARTs,
M
a
st
er/
S
l
a
ve
Seri
al
Peri
ph
e
r
al
I
n
t
e
rfa
ces
(SP
I),
a t
h
ree
-
chan
nel
16
-
b
i
t
Ti
m
e
r C
ount
er (
T
C
)
,
a T
w
o
W
i
re
Interface (T
WI) and four-cha
nnel
10-bit ADC. The
AT91SAM9
260
has a
fully feature
d
syste
m
control
l
er for
effi
ci
ent
sy
st
e
m
m
a
nagem
e
n
t
, i
n
cl
u
d
i
n
g a r
e
set
cont
rol
l
e
r,
sh
ut
d
o
w
n
c
ont
rol
l
e
r,
cl
oc
k m
a
nagem
e
nt
, ad
vanc
e
d
i
n
t
e
rr
upt
c
o
nt
r
o
l
l
e
r (
A
IC
),
de
bu
g
u
n
i
t
(DB
G
U),
pe
ri
o
d
i
c
interv
al tim
er, watch
d
o
g
ti
m
e
r an
d real-tim
e t
i
m
er.
The
AT
91
SA
M
9
2
6
0
i
s
a
v
ai
l
a
bl
e i
n
a
2
1
7
-
b
al
l
LFB
G
A
an
d
20
8
QF
P R
o
HS-c
om
pl
i
a
nt
packa
g
es
.
The
board as
s
h
own in Figure
2 is
desi
gne
d t
o
provide t
h
e followi
ng interfaces
64 MB SDRAM
256 MB Of NAND Flash Memor
y
1 USB Host and
1 USB Device P
o
rt Interface
1 RS232 Serial
communication P
o
rt
1 PHY Ethern
et
100 base
TX with three status LEDs
1 Da
ta
-Fla
sh,
S
D
/MMC Ca
rd Slot
1 External Bus I
n
terface (EBI)
signals
routed thro
ugh
96
Pin Euro Connector
1 Li
thium
Coin
Cell
Bat
t
er
y
Ret
a
iner
for 12m
m
Cell
Size
JTAG /ICE Debug Interface
Fi
gu
re
2.
Eval
uat
i
o
n
Ki
t
B
l
o
c
k
Di
ag
ram
3.
SCHE
M
A
TIC DESIG
N
To
stay co
m
p
etitiv
e in
to
d
a
y's
m
a
rk
et, en
g
i
n
e
ers m
u
st t
a
k
e
a d
e
sign
fro
m
en
g
i
n
eeri
n
g
thro
ugh
m
a
nufact
uri
ng
wi
t
h
s
h
o
r
t
e
r
de
si
gn cy
cl
es a
n
d fa
st
er t
i
m
e t
o
m
a
rket
. OrC
A
D i
s
a s
u
i
t
e
o
f
t
ool
s
fr
om
C
a
dence
fo
r t
h
e desi
gn
and l
a
y
out
o
f
pri
n
t
e
d ci
rcui
t
boar
d
s (
P
C
B
s
). S
o
fo
r t
h
e
desi
g
n
of t
h
e
schem
a
ti
cs for o
u
r
eval
uat
i
o
n ki
t
we use
d
O
r
C
A
D
C
a
pt
ure
.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
089
-48
64
IJR
E
S V
o
l
.
3, No
. 2,
J
u
l
y
20
1
4
:
6
2
– 75
65
a.
Power S
uppl
y
Fi
gu
re
3.
P
o
we
r S
u
p
p
l
y
Sc
he
m
a
t
i
c
s
The P
o
we
r S
u
ppl
y
f
o
r t
h
e ev
al
uat
i
on
ki
t
co
nsi
s
t
s
o
f
1
.
8V
H
i
gh
Eff
i
cien
cy step
-
dow
n
ch
arg
e
pu
m
p
reg
u
l
a
t
o
r a
n
d 3
.
3
V
l
i
n
ear re
g
u
l
at
or wi
t
h
s
hut
do
w
n
co
nt
r
o
l
as sho
w
n i
n
Fi
g
u
re
3. T
h
e TPS
6
0
5
0x
de
vi
ces are
a
fam
i
l
y
of st
ep
-
d
o
w
n c
h
ar
ge
p
u
m
p
s as i
n
Fi
gu
re
3,
t
h
at
ge
nerat
e
a
re
g
u
l
a
t
e
d,
fi
xe
d
1.
8-
V.
O
n
l
y
f
o
u
r
s
m
al
l
ceram
ic capacitors a
r
e
requi
r
ed to
build a
com
p
lete high e
fficiency
dc/dc c
h
arge
pum
p
conve
rter. T
h
e
TPS6
0
5
0x c
h
a
r
ge
pum
ps p
r
o
v
i
d
e a re
g
u
l
a
t
e
d o
u
t
p
ut
v
o
l
t
a
ge i
n
t
h
e
ran
g
e
of
1.
8V
fr
o
m
an i
n
p
u
t
v
o
l
t
a
ge
o
f
5V
. T
h
e
devi
c
e
s use
swi
t
c
he
d ca
paci
t
o
r
f
r
a
c
t
i
onal
co
n
v
ers
i
on t
o
ac
hieve
high efficien
cy
over t
h
e e
n
tire
input
and
o
u
t
p
ut
v
o
l
t
a
ge ra
nge
. R
e
gul
at
i
o
n i
s
ach
i
e
ved
by
sensi
ng t
h
e o
u
t
p
ut
vol
t
a
ge a
n
d en
abl
i
ng t
h
e i
n
t
e
rna
l
switch
e
s as
n
e
ed
ed
t
o
m
a
in
ta
in
th
e selected o
u
t
p
u
t
v
o
ltage. Th
e circu
its co
nsist o
f
an
o
s
cillato
r, a
vo
ltag
e
refe
rence
,
a
n
i
n
ter
n
al resistiv
e fee
dbac
k
cir
c
uit (
f
ix
e
d
vol
t
a
ge versi
o
n
o
n
l
y
),
a
n
error
a
m
p
lifier, an
d two
charge
pum
p
stages
with MOSFET s
w
itc
h
e
s, a sh
u
t
do
wn
/startup
circu
it, an
d a co
n
t
ro
l ci
rcu
it. Th
e
cap
acitor
v
a
lu
es ar
e cl
osely lin
k
e
d to
th
e r
e
qu
ir
ed ou
tpu
t
cur
r
e
n
t
,
o
u
t
p
u
t
no
ise,
an
d r
i
p
p
l
e
r
e
qu
ir
em
en
ts. The input
capaci
t
o
r i
m
prove
s sy
st
em
effi
ci
ency
by
r
e
duci
ng t
h
e i
n
put
i
m
pedance
,
an
d i
t
al
so st
abi
l
i
zes t
h
e i
n
p
u
t
cu
rren
t. Th
e
v
a
lu
e o
f
th
e
ou
tpu
t
cap
acito
r, Co
, influ
e
n
ces th
e stab
ility o
f
th
e vo
ltag
e
regu
lato
r. Th
e m
i
n
i
m
u
m
require
d
capac
itance for C
1
1 is 10 PF. The FB pin m
u
st b
e
co
nn
ected
ex
tern
ally with
th
e ou
tpu
t
. For
m
a
xim
u
m
out
put
cur
r
ent
an
d best
per
f
o
r
m
a
nce, 4 ceram
i
c
capaci
t
o
rs a
r
e re
com
m
e
nded
.
F
o
r l
o
wer cu
rre
nt
s o
r
hi
g
h
er al
l
o
wed
out
p
u
t
v
o
l
t
a
ge
ri
ppl
e,
ot
her c
a
paci
t
o
rs ca
n a
l
so be use
d
. Fl
y
i
ng capaci
t
o
rs
l
o
wer t
h
a
n
1
M
i
cro-
Fara
ds can
be use
d
, but this decreases the maxim
u
m
out
put
po
wer
.
Thi
s
m
eans t
h
at
the device works in
linear
m
ode wi
t
h
l
o
w
e
r
out
put
c
u
r
r
e
n
t
s
. T
o
get
a
n
out
put
o
f
V0
that is 1.8V in this case we
use
the form
ula.
C1
1
22
µ
F
R7
15
0K
+
C1
33
0µ
F
C2
10
V
10
µ
F
DS
1
YE
L
L
O
W
C4
10
µ
F
PO
W
E
R
L
ED
CR
1
5V
Q2
Si15
63ED
H
1
3
2
4
5
6
C1
5
4.
7
µ
F
C3
10
µ
F
R3
10
0K
C5
1µ
F
C1
4
15
PF
C1
2
10PF
Q1
I
R
LM
L24
02
1
3
2
C6
1µ
F
R9
10
K
J3
R1
0
10
K
J1
1
2
3
MN
1
LT
196
3AEQ
-
3
.
3
VI
N
2
GN
D
3
VOU
T
4
GN
D
6
SD
1
FB
5
R1
1
1
20K
R1
12
0R
MN
3
T
PS6
050
0
C1
M
8
GN
D
9
VOU
T
7
EN
1
VI
N
5
C1
P
6
C2
M
3
C2
P
4
FB
10
PG
2
J2
3V
3
R5
0R
R
E
G
U
LATE
D
W
I
TH
N
O
S
O
LD
E
R
M
A
S
K
1
0
S
Q
UA
RE
C
M
C
O
P
P
E
R
A
R
E
A
F
O
R H
E
A
T
S
I
NK
I
N
G
PO
W
E
R
LED
F
O
RCE
PO
W
E
R
ON
5V
O
N
L
Y
3V3 C
U
R
R
E
N
T
M
EASU
R
E
S
HDN
R4
470
K
5V
5V
1V8
3V3
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
RES
I
S
SN
:
208
8-8
7
0
8
Desi
g
n
a
n
d
De
vel
op
ment
of
A
R
M9 Eval
uat
i
o
n
K
i
t
f
o
r Em
be
dde
d Ap
pl
i
c
at
i
ons
(
S
anket De
ssai)
66
V0=
(R
7+R
1
1)
/
R
11
*
VFB
W
h
ere
V
F
B
i
s
V
o
l
t
a
ge at
t
h
e
pi
n FB
w
h
i
c
h
i
s
m
easured
t
o
be
0.
8
V
.
A
n
d
R
7
=
1.
2
5
R
2
s
o
t
h
e
cal
cul
a
t
i
o
ns c
o
m
e
s as R
7
=
1
5
0
K
O
h
m
s
an
d R
11=
1
2
0
K
0
hm
s.
The i
n
p
u
t
v
o
l
t
a
ge f
r
o
m
a singl
e
or
d
u
al
Ni
C
d
,
Ni
M
H
or al
kal
i
n
e cel
l
i
s
bo
ost
e
d
t
o
3.
3
V. T
h
i
s
vol
t
a
ge
i
s
use
d
as sy
st
em
sup
p
l
y
f
o
r
t
h
e
ap
p
l
i
cat
i
on an
d
as
an
i
n
put
v
o
l
t
a
ge
fo
r t
h
e st
e
p
-d
ow
n
cha
r
ge
pum
p
wh
ich
is used
t
o
pro
v
i
d
e
th
e co
re
vo
ltag
e
for a DSP.
A
circu
it for
d
r
iv
i
n
g
a g
a
te of
a MOS transist
or t
o
a non-
co
ndu
ctiv
e state, co
m
p
risin
g
:
a v
o
ltag
e
inpu
t n
o
d
e
for receiv
i
n
g
a
p
o
sitiv
e vo
ltag
e
; a sig
n
a
l inp
u
t
no
d
e
for
receiving a
n
E
NABL
E
signal
; and a
negative voltage
ge
ne
rator,
responsi
ve to an
ENABLE signal from
the
sig
n
a
l inp
u
t
no
d
e
t
o
app
l
y a n
e
g
a
tiv
e
v
o
ltag
e
to
th
e gate o
f
th
e M
O
S tran
sistor to
prev
en
t MOS tran
sistor
cur
r
ent
c
o
n
d
u
c
t
i
on,
whe
r
ei
n t
h
e ne
gat
i
v
e
vol
t
a
ge ge
nerat
o
r
com
p
rises: a capacitor
ha
vi
ng a first electrode and
a second electrode; a first s
w
itching de
vic
e
connected
between
the first
capacito
r el
ectrode and the input
n
o
d
e
; a second sw
itch
i
ng
d
e
vice co
nn
ected
b
e
tw
een
th
e seco
nd
cap
acito
r electr
o
d
e
and
a co
mm
o
n
p
o
t
en
tial;
a t
h
i
r
d s
w
i
t
c
h
i
ng
devi
ce c
o
nnect
e
d
bet
w
e
e
n t
h
e sec
o
nd capacitor ele
c
trode and the gate of t
h
e
MOS
t
r
ansi
st
o
r
;
a f
o
urt
h
swi
t
c
hi
ng
devi
ce c
o
nnect
ed bet
w
een
t
h
e
first capacitor
electrode a
n
d a
current s
o
urce
; and
a m
oni
t
o
ri
ng
c
i
rcui
t
res
p
o
n
si
ve t
o
t
h
e
vol
t
a
ge
of t
h
e fi
rst capacitor electrode
for c
ontrolling the
first t
o
fourt
h
swi
t
c
hi
n
g
de
vi
ces t
o
c
h
ar
ge t
h
e ca
paci
t
o
r
an
d
dri
v
e t
h
e
gat
e
v
o
l
t
a
ge
of
t
h
e M
O
S t
r
an
si
st
or
ne
gat
i
v
e.
b.
MMC/SD Car
d
Interface
Th
e M
u
lti
m
e
d
i
a Card In
terface (MCI) su
ppo
rts t
h
e M
u
ltimed
ia Card (MMC) Sp
eci
ficatio
n
V3.11
,
th
e SDIO
Sp
ecificatio
n
V1
.1 an
d
th
e
SD
Me
m
o
ry
Card
Specification
V1.0. The MC
I includes a command
regi
st
er
, res
p
o
n
se
regi
st
ers
,
dat
a
re
gi
st
ers,
t
i
m
e
out
cou
n
ters and
erro
r d
e
tectio
n logic th
at au
to
m
a
tically
handle the tra
n
smission
of c
o
mmands an
d, whe
n
re
quire
d,
the reception of
the as
sociat
ed
responses a
n
d data
with
a lim
ited
p
r
o
cesso
r ov
erh
ead.
Th
e MCI sup
p
o
r
ts stream
, b
l
o
c
k
and
m
u
lti-b
l
o
c
k
data
read
and
write, an
d
is co
m
p
atib
le with
th
e
Peri
p
h
eral
DM
A C
o
nt
r
o
l
l
e
r
(
P
DC
)
cha
n
nel
s
, m
i
nim
i
zi
ng
pro
cessor in
terven
tio
n fo
r
large buffer transfe
r
s.
The M
C
I
ope
r
a
t
e
s at
a rat
e
of
u
p
t
o
M
a
st
er C
l
oc
k
di
vi
d
e
d
by
2 a
n
d
s
u
p
p
o
rt
s t
h
e i
n
t
e
rfaci
n
g
o
f
2
slo
t
(s). Each
slo
t
m
a
y b
e
u
s
ed
to
in
terface with
a Mu
ltimed
ia Card
bu
s (up
to
3
0
Card
s) or wit
h
a SD
Me
m
o
ry Card
. On
ly on
e slo
t
can
b
e
select
ed
at a ti
m
e
(s
lo
ts are m
u
ltip
lex
e
d). A
b
it field
in
th
e SD Card
Reg
i
ster
p
e
rform
s
th
is selecti
o
n.
The
SD
M
e
m
o
ry
C
a
r
d
c
o
m
m
uni
cat
i
o
n i
s
ba
sed
o
n
a
9
-
pi
n
i
n
t
e
rface
(cl
o
c
k
,
com
m
and,
f
o
u
r
dat
a
a
n
d
three powe
r lines) a
nd the
Multim
e
di
a Card on a 7-pin interface (clock
, comm
and, one data, thre
e power
lin
es and on
e reserv
ed
fo
r
fu
t
u
re u
s
e). Th
e SD Mem
o
ry Card in
terface also supp
orts Mu
ltim
ed
ia
Card
o
p
e
ration
s
.
The m
a
in
d
i
fferences b
e
t
w
een SD an
d Mu
ltim
e
d
ia Card
s are t
h
e in
itializatio
n
p
r
o
cess and
t
h
e
b
u
s
to
po
log
y
.After a p
o
w
er-on
reset; th
e card
s
are in
itiali
zed
b
y
a sp
ecial
m
e
ssag
e
-b
ased
M
u
lti Med
i
a Card
bu
s
pr
ot
oc
ol
. Ea
ch
m
e
ssage i
s
re
p
r
esent
e
d
by
o
n
e
o
f
t
h
e
f
o
l
l
o
wi
ng
t
o
ken
s
:
C
o
m
m
a
nd:
A com
m
a
nd i
s
a t
oke
n t
h
at
st
art
s
an o
p
erat
i
o
n.
A com
m
and is sent
fr
om
t
h
e host
ei
t
h
er t
o
a
si
ngl
e ca
rd
(a
dd
resse
d c
o
m
m
a
nd)
o
r
t
o
al
l
con
n
ect
ed
cards
(broa
d
ca
st comm
and). A c
o
mm
and is
tran
sferred seri
ally o
n
th
e CMD lin
e.
R
e
spo
n
se:
A
r
e
sp
onse i
s
a t
oke
n
whi
c
h i
s
sent
fr
om
an add
r
esse
d car
d o
r
(sy
n
ch
ro
no
usl
y
) f
r
o
m
al
l
connected cards to the
host a
s
an
a
n
s
w
er t
o
a pre
v
i
ously received
c
o
mmand. A res
p
onse is trans
f
erre
d
serially o
n
t
h
e
CMD lin
e.
Data: Data can b
e
t
r
an
sferred
fro
m
th
e card to
th
e ho
st
or vi
ce ve
rsa.
Data
is trans
f
erred via the data
line.
Card
add
r
essi
ng
is im
p
l
e
m
en
t
e
d
using
a sessio
n
add
r
ess assig
n
e
d
d
u
ring
t
h
e in
itializatio
n
ph
ase
b
y
th
e bu
s con
t
ro
ller to
all cu
rrently co
n
n
ected
card
s. Th
eir
un
iq
u
e
CID
n
u
m
b
e
r id
en
tifies ind
i
v
i
du
al cards.
There
are
di
f
f
e
rent
t
y
pes
o
f
op
erat
i
o
ns.
A
d
d
r
esse
d
ope
r
a
t
i
ons al
way
s
cont
ai
n
a com
m
and a
nd a
resp
o
n
se t
o
ken
.
In a
d
di
t
i
on, s
o
m
e
operat
i
o
n
s
have a
dat
a
t
oke
n;
t
h
e
ot
he
r
s
t
r
ans
f
er t
h
ei
r
i
n
fo
rm
at
i
on di
rect
l
y
with
in
th
e co
m
m
an
d
or respon
se stru
ctur
e.
In
th
is case,
no
d
a
ta to
k
e
n
is
present in a
n
operation. The bi
ts on
the DAT
and t
h
e CMD lines
are tra
n
sfe
rre
d
sy
nch
r
o
n
o
u
s
t
o
t
h
e cl
oc
k M
C
I
C
l
ock
.
As pe
r t
h
e ab
ove Fi
gu
re 4
,
AT
45
DB
6
4
2
D
i
s
used w
h
i
c
h i
s
a 2.7
-
vol
t
,
dual
-
i
n
t
e
r
f
ac
e seque
nt
i
a
l
access Flash
me
m
o
ry. The AT
45DB642D is enabled thro
ugh the chi
p
select pin (CS) and accesse
d via a
three-wire inte
rface consisting of the Se
rial Input (SI), Seri
al Output (SO)
, and the Se
rial Clock (SCK).
This
is in
itiated
b
y
th
e ARM
9
Pro
c
esso
r. Th
e SO
p
i
n
is
u
s
ed
to
sh
ift d
a
ta
ou
t fro
m
th
e d
e
v
i
ce. Data on
th
e SO pi
n
i
s
al
way
s
cl
oc
ked
o
u
t
o
n
t
h
e
fal
l
i
ng e
d
ge
of
SC
K.
Wh
e
n
the
WP
pin
is asserted, all sectors
specified for
p
r
o
t
ectio
n b
y
t
h
e Sect
o
r
Pro
t
ectio
n
Reg
i
ster
will b
e
p
r
o
t
ected
ag
ain
s
t
p
r
ogram
an
d
erase
o
p
e
ration
s
reg
a
rd
less
of
w
h
et
he
r t
h
e Ena
b
l
e
Sec
t
or
Pr
ot
ect
i
o
n
com
m
and ha
s bee
n
i
s
s
u
e
d
o
r
not
.
T
h
e
W
P
pi
n
fu
n
c
t
i
ons
i
nde
pen
d
e
n
t
l
y
of t
h
e s
o
ft
ware
cont
r
o
l
l
e
d p
r
o
t
ect
i
on m
e
t
hod
. If a p
r
o
g
ram
or era
s
e com
m
a
nd i
s
i
ssue
d
t
o
t
h
e
device while the
W
P
pi
n is asserted, the de
vice w
ill sim
p
ly ignore the c
o
m
m
a
nd
and perform
no ope
ration.
Th
e
d
e
v
i
ce
will retu
rn
to th
e
id
le state o
n
c
e th
e CS
p
i
n
h
a
s b
e
en
de-asserted
.
Th
e
En
able Secto
r
Pro
t
ection
co
mman
d
and
Secto
r
Lo
ck
down
co
mm
an
d
,
h
o
wev
e
r, will b
e
recog
n
i
zed
b
y
th
e d
e
v
i
ce
wh
en
th
e
WP
p
i
n
is
assert
ed
. T
h
e
WP
pi
n
i
s
i
n
t
e
r
n
al
l
y
pul
l
e
d-
hi
gh
an
d m
a
y
be l
e
ft
fl
oat
i
ng
i
f
ha
rd
ware
co
nt
rol
l
e
d
p
r
ot
ect
i
o
n
wi
l
l
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
089
-48
64
IJR
E
S V
o
l
.
3, No
. 2,
J
u
l
y
20
1
4
:
6
2
– 75
67
not
be
use
d
. T
h
e
AR
M
9
ca
n
reset
t
h
e
seri
a
l
fl
ash
by
se
nd
i
ng a
hi
gh
si
g
n
al
t
o
(R
eset
)
reset
pi
n t
o
re
set
i
t
s
ope
rat
i
o
ns.
Figure
4.
Sc
he
m
a
tics for MM
C/SD Card
Dat
a
Flash
c.
Etherne
t
MAC Interface
Th
e
EMAC m
o
du
le im
p
l
e
m
e
n
ts a
10
/100
Eth
e
rn
et MAC
co
m
p
atib
le with th
e
IEEE
8
0
2
.
3
stan
d
a
rd
using a
n
addre
ss chec
ker, sta
tistics
and cont
rol re
gisters
,
receive and tra
n
sm
it blocks,
and a
DM
A interface.
The address c
h
ecke
r
rec
o
gnizes four s
p
ec
ific 48-bit
address
e
s and c
ontains a 64-bit hash
re
gister for
m
a
t
c
hi
ng m
u
l
t
i
cast
and
uni
cas
t
addre
sses.
It
can rec
o
gni
ze
t
h
e broa
dcast a
d
dress
of all ones, c
opy all fra
m
es,
and act on a
n
e
x
ternal address
m
a
tch signal.
The st
at
i
s
t
i
c
s r
e
gi
st
er bl
oc
k c
ont
ai
n
s
regi
st
e
r
s fo
r co
unt
i
n
g
vari
o
u
s t
y
pes
of eve
n
t
asso
ci
at
ed wi
t
h
transm
it and re
ceive operations. T
h
ese
regis
t
ers, along
w
ith the status
words st
ore
d
in t
h
e receive
buffe
r list,
enable softwa
re
to gene
rate network
m
a
nage
m
e
nt statistics
com
p
atib
le
with IEEE 802.3.
The Et
her
n
et
M
A
C
i
s
t
h
e
h
a
rd
ware
i
m
pl
em
ent
a
t
i
on
of t
h
e M
A
C
s
u
b
-
l
a
y
e
r O
S
I
ref
e
r
e
nce m
ode
l
b
e
tween
th
e ph
ysical layer (PHY) and
the
lo
g
i
cal link
la
y
e
r (
LLC).
It c
o
ntr
o
ls th
e data excha
n
ge between a
host a
n
d a P
H
Y layer acc
ording t
o
Ethe
rnet IEEE
802.3u
data fram
e form
at. The Ethe
rnet MAC c
ont
ains the
required l
ogic
and transm
it a
n
d recei
ve FIFOs
for
DMA
managem
e
nt
. In addition, it is
interfaced through
M
D
I
O
/
M
DC
p
i
ns f
o
r P
H
Y l
a
y
e
r m
a
nagem
e
nt
. T
h
e Et
he
r
n
et
M
A
C
can
t
r
ans
f
er
dat
a
i
n
m
e
di
a-i
nde
p
e
nde
n
t
interface
(MII) or re
duced m
e
dia inde
p
e
nd
ent in
ter
f
ace (
R
MI
I
)
m
o
d
e
s
d
e
p
e
nd
ing
on
th
e p
i
nou
t conf
igur
atio
n.
The m
a
jor feat
ures
of t
h
e EM
AC are:
Com
p
atibility with
IEEE Sta
nda
rd 802.3
1
0
and
10
0 Mbits p
e
r
second
d
a
ta throug
hput cap
ab
ility
Fu
ll- and
h
a
lf-d
up
lex op
eratio
n
MII
or RMII interface t
o
the
physical layer
Register inte
rface to a
d
dress
,
status and c
o
ntrol
registers
DM
A i
n
ter
f
ace
Interrupt
ge
neration to signal
receive a
n
d tra
n
sm
it co
m
p
letion
28-byte transm
it and
28
-byte receive FIFOs
Au
t
o
m
a
t
i
c p
a
d and
CRC
g
e
n
e
ratio
n on
tran
smit
ted
fram
es
Ad
dr
ess c
h
ec
ki
ng
l
o
gi
c t
o
rec
o
g
n
i
ze
fo
ur
4
8
-
bi
t
a
d
d
r
esses
Sup
p
o
r
ts pro
m
iscu
ou
s m
o
d
e
wh
ere all
v
a
lid fram
e
s are co
pied
to
m
e
m
o
ry
Supports physical
layer
m
a
nagem
e
nt
through MDIO i
n
terface control
of
alarm
and update tim
e
/calenda
r
d
a
ta in
.
CS
R4
2
0R
J1
3
F
PS009
8
5
7
6
4
3
2
1
9
S5
R4
3
10K
C8
5
1
00N
F
C8
2
1
00N
F
W
R
I
T
E PR
OT
E
C
T
NO
RM
A
L
L
Y
O
P
E
N
R3
7
4
70K
DA
T
3
MN
9
R
ESET
3
GN
D
7
VC
C
6
CS
4
SC
K
2
SI
1
SO
8
WP
5
R4
0
0R
DA
T
0
3V
3
3V
3
3V3
CM
D
S
E
R
I
A
L
D
A
TA
FLA
S
H
DA
T
1
NRS
T
SC
K
DA
T
2
3V3
CL
K
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
RES
I
S
SN
:
208
8-8
7
0
8
Desi
g
n
a
n
d
De
vel
op
ment
of
A
R
M9 Eval
uat
i
o
n
K
i
t
f
o
r Em
be
dde
d Ap
pl
i
c
at
i
ons
(
S
anket De
ssai)
68
Fi
gu
re
5.
Sche
m
a
t
i
c
s for Et
he
rnet
M
A
C
Th
e EMAC h
a
s an
in
terrup
t lin
e co
nn
ected
to
th
e Ad
v
a
n
c
ed
In
terrup
t Co
n
t
ro
ller (AIC)
as sh
own
in
Fig
u
re
5
.
Handlin
g
th
e EMAC in
terrup
t requ
ires
pr
og
r
a
m
m
in
g
th
e
AI
C
b
e
fo
r
e
conf
igur
ing
th
e EMAC.
The Et
her
n
et
i
s
cl
ocke
d t
h
r
o
u
g
h
t
h
e
Po
we
r
M
a
nagem
e
nt
C
ont
rol
l
e
r
(PM
C
).
R1
2
3
0R
TX
D
3
TX
_
E
N
SP
EED
1
0
0
F
U
LL D
U
P
L
E
X
L
I
NK
&
A
CT
TX
_
C
L
K
R1
2
4
0R
R1
2
5
0R
Y4
25M
H
z
1
2
J1
5
C9
5
100
N
F
MN
1
1
D
M
916
1A
E
P
T
X
_
E
R/
T
X
D4
16
CO
L
/
RM
I
I
36
MD
C
24
RX
-
4
RX
+
3
TX
-
8
TX
+
7
XT
1
43
RE
F_
CL
K
/
X
T
2
42
R
X
_C
LK
/
1
0B
T
S
E
R
34
R
X
_
D
V/
T
EST
M
O
D
E
37
RX
_
E
R/
RX
D4
/
R
P
T
R
38
TX
_
E
N
21
BG
R
E
S
48
AV
D
D
R
1
AV
D
D
R
2
DV
D
D
41
DG
ND
44
DG
ND
15
AG
N
D
5
AG
N
D
6
LE
D
2
/
O
P
2
13
LE
D
1
/
O
P
1
12
LE
D
0
/
O
P
0
11
TX
D
3
17
TX
D
2
18
TX
D
0
20
TX
D
1
19
T
X
_C
L
K
/
I
S
O
LA
T
E
22
RX
D0
/
P
HY
A
D
0
29
RX
D1
/
P
HY
A
D
1
28
RX
D2
/
P
HY
A
D
2
27
RX
D3
/
P
HY
A
D
3
26
CRS
/
P
H
Y
A
D
4
35
MD
I
O
25
MD
I
N
TR
32
P
W
RDWN
10
DG
ND
33
R
E
SET
40
A
V
DDT
9
DI
S
M
DI
X
39
DV
D
D
30
DV
D
D
23
AG
N
D
46
B
G
R
ESG
47
C
A
BL
ES
T
S
/
L
I
N
KS
T
S
14
N.
C
45
LE
D
M
OD
E
31
S7
C9
6
100N
F
DS
4
GR
E
E
N
C9
0
100N
F
C9
8
100N
F
R5
6
10K
R5
9
1K
RX
D
0
C9
7
100N
F
R5
3
49
R
9
1%
C9
1
1
00N
F
C9
4
1
00N
F
C9
3
10V
10µ
F
R6
1
1K
R5
2
49R
9
1%
R6
3
1K
C8
7
1
00N
F
R5
4
49R
9
1%
C9
2
1
00N
F
1
2
3
6
4
5
7
8
75
75
75
75
1nF
TD+
TD-
CT
NC
RD-
CT
TX+
TX-
RX+
RX-
RD+
J1
4
J
00-
0061N
L
1
2
7
8
3
6
5
4
15
16
R5
1
49
R
9
1%
S8
DS
2
YE
L
L
O
W
L3
74279
2093
DS
3
GR
E
E
N
R1
2
6
0R
R5
7
10
K
5
0
MHz
VDD
VS
S
OUT
OE
Y3
S
G
-80
02J
C
-
50.
0
000M
-P
C
B
4
1
3
2
RX
D
1
RX
D
2
RX
D
3
RX
_
C
L
K
RX
_
D
V
C1
0
1
10
V
10
µ
F
RX
_
E
R
R1
1
9
0R
R1
2
0
0R
TX
_
E
R
R5
5
0R
R6
2
0R
CO
L
R4
9
0R
R5
0
0R
CR
S
C
102
100N
F
R
J45 E
T
H
E
R
N
E
T
C
O
N
N
E
C
T
O
R
MD
I
N
TR
R
127
10K
MD
C
G
ND_
E
T
H
MD
I
O
RR6
10K
1
5
2
3
4
6
7
8
3V
3
3V
3
NRS
T
R4
8
10K
GN
D
_
E
T
H
G
ND_
E
T
H
G
ND_
E
T
H
V
CCA
R1
2
1
0R
VC
C
A
V
CCA
3V
3
R5
8
6,
80K
1%
3V
3
3V
3
3V
3
TX
D
0
R1
2
2
0R
C8
8
22P
F
C8
9
22P
F
TX
D
1
TX
D
2
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
089
-48
64
IJR
E
S V
o
l
.
3, No
. 2,
J
u
l
y
20
1
4
:
6
2
– 75
69
Th
e Et
h
e
rn
et
has an in
terrup
t
lin
e con
n
e
cted
to
th
e
Ad
v
a
n
c
ed
In
terru
p
t
C
o
n
t
ro
ller (AIC
).
ETXEN
p
i
n is
u
s
ed
for Tran
smit En
ab
le
ECOL
Sign
al
Pin
is
u
s
ed
C
o
llisio
n
Detect
ETX
0 -
ET
X
3
pi
ns
are use
d
f
o
r
4
-
bi
t
dat
a
t
r
ansm
i
t
ERX0 - ERX3
pins
are
use
d
for 4-bit
da
ta reception
EC
R
S
pi
n
i
s
us
ed fo
r
C
a
r
r
i
e
r Sense
Uses
2 bits for transm
it (ETX0 a
n
d ET
X1) and two
bits
for recei
ve (ERX0 a
n
d ER
X1). T
h
ere is a
Transm
it Enable (ET
X
EN),
a Receive E
r
ror (ER
X
ER),
a Carrie
r
Se
ns
e (ECRS_DV), and a
50 MHz
R
e
fere
nce C
l
o
c
k
(ET
X
C
K
_R
EFC
K
)
f
o
r
10
0
M
b/
s dat
a
rat
e
.
The tra
n
sm
it a
n
d recei
ve
bits are c
o
nve
r
ted
from
a 4-b
it
pa
rallel form
at to
a 2-bit
paralle
l schem
e
that is
clocke
d at twice the rate. The carrier se
nse a
nd
da
ta v
a
lid
sig
n
a
ls are co
m
b
in
ed
in
to
th
e ECRS_
E
CRSDV
si
gnal
.
LED
s f
l
ash
once p
e
r
200
m
s
a
f
ter
po
w
e
r
-
on
reset o
r
software reset b
y
writi
ng P
H
Y re
gi
st
er. Al
l
LED
pi
ns a
r
e d
u
al
f
unct
i
o
n
pi
ns,
whi
c
h can
be c
o
n
f
i
g
ure
d
as ei
t
h
er act
i
v
e hi
g
h
o
r
l
o
w
by
p
u
l
l
i
ng t
h
em
l
o
w or hi
gh
accordingly. If the
pin is
pulled
high, t
h
e L
E
D is active
low afte
r
reset. L
i
kewise, if the
pin is
pulled l
o
w, t
h
e
LED is activ
e
h
i
gh
.
d.
U
S
B In
t
e
rf
a
c
e
A USB 2.0 full-speed
pad is
e
m
bedde
d and contro
lled by the Serial Interface Engine
(SIE
). The
si
gnal
e
x
t
e
r
n
al
_res
um
e i
s
opt
i
onal
but
al
l
o
ws t
h
e
USB
Devi
ce
Po
rt
(
UD
P)
peri
phe
r
a
l
t
o
wa
ke-
u
p
once
i
n
syste
m
m
o
d
e
. Th
e ho
st will th
en
b
e
no
tified th
at th
e d
e
v
i
ce ask
s
fo
r a resu
m
e
. Th
is o
p
tio
n
a
l feat
u
r
e mu
st b
e
also
n
e
go
tiated with
t
h
e
h
o
st
d
u
ring
t
h
e en
um
eration. The
main
feat
ures of
the UDP
a
r
e
:
USB
V2.0 Fu
ll-sp
eed
C
o
m
p
li
an
t,
1
2
Mb
its
per seco
nd
Em
bedded USB V2.0 Full-s
p
eed T
r
ansceive
r
Em
bedded
D
u
al
-p
ort
R
A
M
f
o
r
En
d
poi
nt
s
Sus
p
en
d/
R
e
s
u
m
e
Logi
c
Pi
ng
-
p
o
n
g
M
o
de
(2
M
e
m
o
ry
B
a
nks
)
fo
r
Is
o
c
hr
o
n
o
u
s a
n
d
B
u
l
k
E
n
dp
oi
nt
s
The
Figure
6 s
h
ows
the s
c
he
matics for t
h
e
USB
De
vice Port
(
UD
P)
and
U
S
B
Ho
st Po
r
t
(U
HP)
.
Th
e
UD
P sc
hem
a
t
i
cs i
s
ex
pl
ai
ne
d
as f
o
l
l
o
wi
ng
UDP_
C
N
X is
an
inpu
t sign
al
u
s
ed
to ch
eck
i
f
th
e ho
st is con
n
ected
UD
P_
PU
P i
s
a
n
out
put
si
g
n
al
use
d
t
o
e
n
abl
e
p
u
l
l
-
u
p
o
n
DP
PD
4 i
s
a
n
i
n
p
u
t
si
g
n
al
pi
n
us
ed
to chec
k i
f
t
h
e
host is connected
PD
5 i
s
a
n
o
u
t
p
ut
si
g
n
al
pi
n
us
ed t
o
ena
b
l
e
p
u
l
l
up
o
n
DD
P
DDM
:
USB
D
e
vice P
o
rt
Dat
a
o
n
l
o
w
o
p
e
r
ating s
p
ee
d
DD
P :
USB
De
vice P
o
rt
Data
on
hi
gh
o
p
e
r
ating
sp
eed
A b
u
s-
p
o
we
re
d peri
ph
eral
r
e
qui
res a 3.
3
V
reg
u
l
a
t
o
r, b
o
t
h
t
o
p
o
w
er t
h
e l
ogi
c an
d t
o
su
ppl
y
t
h
e
pr
o
p
er
vol
t
a
ge
t
o
a USB
pi
ns
. Thi
s
pul
l
-
u
p
resi
st
or
si
g
n
al
s t
h
e h
o
st
t
h
at
a
devi
ce i
s
c
o
n
n
ect
ed, a
nd i
ndi
cat
es
the de
vice'
s operating spee
d.
There
are t
w
o
comm
unication c
h
annels
between the
Ho
st
Co
n
t
ro
ller and
th
e Ho
st C
o
n
t
ro
ller Driv
er.
The fi
r
s
t
chan
n
e
l
uses a set
of
ope
rat
i
onal
re
gi
st
ers l
o
cat
e
d
on t
h
e USB
H
o
st
C
o
nt
rol
l
e
r
.
The H
o
st
C
o
nt
rol
l
e
r
is th
e targ
et
for all co
mm
u
n
i
catio
n
s
o
n
th
is ch
an
n
e
l.
The
ope
rat
i
o
nal
re
g
i
st
ers co
nt
ai
n c
ont
rol
,
st
at
us a
n
d
l
i
s
t
poi
nt
er re
gi
st
er
s. They
are m
a
ppe
d i
n
t
h
e A
S
B
m
e
m
o
ry
ma
p
p
e
d
area.
W
ith
in
th
e op
eratio
n
a
l reg
i
ster set th
ere
is a poi
nter t
o
a location in
th
e proce
ssor
address s
p
ace
nam
e
d the
Host Controller
Comm
unicatio
n Area
(HCCA). T
h
e
HCCA is t
h
e s
econd c
o
mm
unication c
h
annel
.
As
d
e
v
i
ce con
n
ection
is auto
m
a
tical
ly detected by the
USB
host
port
lo
g
i
c, a
pu
ll-
do
wn
m
u
st be
co
nn
ected
o
n
DP and
DM
o
n
th
e bo
ard
.
Oth
e
rwise t
h
e USB
ho
st
will p
e
rm
an
en
tly d
e
tect a
d
e
v
i
ce
co
nn
ection
on
th
is
po
rt.
HDM
A :
USB
Host
Po
rt
A
D
a
ta on
a l
o
w
o
p
eratin
g s
p
ee
d
H
D
PA USB Ho
st Po
r
t
A
D
a
t
a
on
a
h
i
gh
op
er
atin
g sp
eed
HDM
B USB Host Po
rt
B Da
ta
on
a
lo
w o
p
e
r
ating
spee
d
HDPB USB
Host Port B
Data
on a
high
operating s
p
ee
d
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
RES
I
S
SN
:
208
8-8
7
0
8
Desi
g
n
a
n
d
De
vel
op
ment
of
A
R
M9 Eval
uat
i
o
n
K
i
t
f
o
r Em
be
dde
d Ap
pl
i
c
at
i
ons
(
S
anket De
ssai)
70
Figure
6. Sc
he
matics for
USB Inte
rface
e.
Serial Interface
The Universal Synchronou
s Async
h
ronous
Receiver
T
r
a
n
s
m
itter
(USAR
T
)
provides
one full duple
x
uni
versal
sy
nc
hr
o
n
o
u
s asy
n
c
hr
o
n
o
u
s se
ri
al
l
i
nk.
Dat
a
fra
m
e
form
at
i
s
wi
del
y
p
r
o
g
ra
m
m
a
bl
e (dat
a l
e
ngt
h
,
pari
t
y
, n
u
m
b
er
of
st
o
p
bi
t
s
)
t
o
s
u
p
p
o
rt
a m
a
xi
m
u
m
of st
an
dar
d
s.
The
US
AR
T i
n
t
e
r
r
upt
l
i
n
e i
s
co
nnect
ed
on
o
n
e
of th
e in
tern
al sou
r
ces of th
e
Ad
va
nced
Inte
rr
u
p
t Co
n
t
roller.
Usi
ng t
h
e
US
ART int
e
rr
upt
re
quire
s
the
AIC to
b
e
p
r
og
ramm
ed
first. No
te th
at it i
s
n
o
t
reco
mmen
d
e
d
to
u
s
e th
e USART in
t
e
rru
p
t
lin
e in
ed
g
e
sensitive m
ode. The recei
ver i
m
ple
m
ents parity error,
fram
i
ng e
r
ror a
n
d overrun erro
r
de
tection. The re
ceiver
ti
m
e
o
u
t
en
ab
les h
a
nd
lin
g v
a
riab
le-leng
t
h
fra
m
es an
d th
e tran
sm
itter ti
me gu
ard
facilitates co
mm
u
n
i
catio
ns
with
sl
o
w
rem
o
te d
e
v
i
ces.
M
u
lti-d
r
op
co
mm
u
n
i
catio
n
s
are also
su
pp
ort
e
d
th
ro
ugh
add
r
ess
b
it h
a
nd
lin
g
in
reception a
n
d t
r
ansm
ission as
shown in Fi
gure 7.
The MAX3241E is selected
as th
e
RS-232 trans
-receiver whic
h
is
a +3.0V
powe
red
E
I
A/T
I
A-232
and
V.28/V.24 comm
unications interface
de
vices feat
ure l
o
w power c
o
nsum
pt
ion,
high
data-rate capa
b
i
lities
,
an
d
enh
a
n
c
ed
electro
static-d
i
s
ch
arg
e
(ESD)
pro
t
ectio
n
.
A prop
rietary l
o
w-d
r
op
ou
t transmitter o
u
t
pu
t
stag
e
3V
3
C
109
100N
F
R7
8
15K
A
B
J1
6
C
C
U
SBA
-
3
2
002-
30
X
A1
A4
A2
A3
1
2
B1
B2
B3
B4
3
4
R7
1
15K
C
119
33PF
R7
0
15
K
C
124
15
PF
C
111
47pF
R8
1
15K
C
110
47pF
R7
6
39R
R6
6
39R
C
123
15P
F
F2
500 m
A
R8
7
1,
5K
R8
9
39R
5V
R7
7
15
K
C
112
47pF
R8
4
22
K
C
113
47pF
C
120
100N
F
C
108
100N
F
J1
9
1
4
2
3
5
6
R6
7
39R
F1
500 m
A
R7
4
39R
R9
0
39R
DD
M
DD
P
US
B
_
C
N
X
USB H
O
ST
I
N
T
E
RF
A
C
E
USB D
E
VI
CE I
N
T
E
RF
A
C
E
N
O
T P
O
P
U
L
A
TE
D
HD
M
A
HD
P
A
R8
2
0R
US
B
C
NX
HD
M
B
HD
P
B
N
O
T
PO
PU
L
A
T
E
D
N
O
T
PO
PU
L
A
T
E
D
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
089
-48
64
IJR
E
S V
o
l
.
3, No
. 2,
J
u
l
y
20
1
4
:
6
2
– 75
71
del
i
v
ers
t
r
ue R
S
-2
3
2
per
f
o
rm
ance
fr
om
a +3
.0
V t
o
+5
.5
V
p
o
we
r s
u
ppl
y
,
u
s
i
n
g
an
i
n
t
e
r
n
a
l
dual
cha
r
ge
p
u
m
p
.
The c
h
a
r
ge
p
u
m
p
req
u
i
r
es
onl
y
fo
ur
sm
al
l
0.1
μ
F capacito
rs
for
operatio
n fro
m
a +3
.3V sup
p
ly. All
tran
sm
it
ters were driv
en
simu
ltan
e
ou
sly at
1
20k
bp
s i
n
to
RS- 232
lo
ad
s in
p
a
rallel with
100
0n
F.
Here 3v
is
ap
p
lied to
Vcc
with
th
e b
y
p
a
ss cap
acitor
o
f
10
0NF.
Figure
7. Sc
he
matics for RS232 Interface
f.
SD
RA
M I
n
ter
f
ace
Th
e
A
T
91
SAM9
26
0 Ev
alu
a
tio
n
k
it h
a
s
b
e
en
incor
por
ated
b
y
64 Mb
ytes
o
f
SD
RA
M m
e
m
o
r
y
. Th
ere
are two
256Mbits m
e
m
o
r
y
connecte
d
s
e
rially to
f
o
r
m
64M
by
t
e
s
of
m
e
m
o
ry
. The
SDR
A
M
uses
t
h
e
SDRAMC (SDRAM Con
t
ro
ller)
wh
ich
is alread
y pr
esen
t in
th
e
pro
cessor. Th
e SDRAM Con
t
ro
ller
(SDR
AMC) exten
d
s
t
h
e m
e
mo
ry cap
a
b
ilities o
f
a ch
i
p
b
y
p
r
ov
id
ing
th
e i
n
terface to
an
ex
tern
al 16
-b
it o
r
32
-
b
it SD
R
A
M
dev
i
ce. Th
e
p
a
ge size supp
or
ts r
a
n
g
e
s fr
o
m
20
48
t
o
8
192
and
th
e nu
m
b
er
o
f
co
l
u
m
n
s f
r
om
2
5
6
to 2048.
It supports byte (8-bit)
,
half-word (16-bit) and word
(32-
bit) accesses. The
SDRAM Controller
su
ppo
r
t
s a read or
w
r
ite
b
u
r
s
t
len
g
t
h of
on
e l
o
catio
n.
I
t
do
es no
t su
ppo
r
t
byte Read
/
W
r
ite bu
r
s
ts or
h
a
lf-w
or
d
write bursts. It
keeps trac
k of th
e active row in each bank,
thus m
a
xi
m
i
z
i
ng SDRAM
pe
rform
a
nce, e.g., the
appl
i
cat
i
o
n m
a
y
be pl
ace
d i
n
o
n
e ba
n
k
a
n
d
dat
a
i
n
t
h
e
ot
her
ba
nk
s. S
o
as t
o
opt
i
m
i
z
e per
f
o
rm
ance,
i
t
i
s
advisa
ble to a
v
oid accessi
ng
diffe
re
nt ro
ws
in the sam
e
bank. As
pe
r fi
gure
8, MT
48L
C
8M16A2 is s
e
lected
for its s a
hi
gh-spee
d
CMOS,
dynam
i
c random
access
m
e
mory
The
A(0-14) is
use
d
as the a
d
dress
bus
for s
p
ecifying
the a
d
dress t
o
the SDRAMs.
D(
0-3
1
)
is used
as th
e
d
a
ta bu
s
b
e
tween
th
e SDRAMs and
th
e ARM9
pro
c
esso
r. SDCS is
us
ed as c
h
ip sel
ect whic
h sele
cts
whi
c
h S
D
R
A
M
nee
d
s t
o
be
enabl
e
d
fo
r
dat
a
passa
ge
bet
w
een t
h
e
p
r
ocess
o
r
an
d t
h
e S
D
R
A
M
SDC
K
pi
n i
s
u
s
ed t
o
pass t
h
e
cl
ock
si
g
n
al
s t
o
S
D
R
A
M
SDC
L
K
pi
n i
s
use
d
c
ont
r
o
l
t
h
e ena
b
l
i
n
g
a
n
d
di
sabl
i
n
g t
h
e cl
ock
si
g
n
al
s t
o
t
h
e S
D
R
A
M
RAS Pi
n t
o
use
d
as
row signal
R9
4
0R
R9
5
0R
3V3
3V3
RX
D
RT
S
CT
S
TX
D
R9
1
100K
DT
R
R9
6
0R
CT
S
0
C1+
V+
VCC
C1-
C2+
C2-
V-
T
T
GND
T
T1OUT
T2OUT
T3OUT
T1IN
T2IN
T3I
N
R
R
R
R
R
R
R
R1IN
R2IN
R3IN
R4IN
R5IN
R1O
UT
R2O
UT
R3O
UT
R4O
UT
R5O
UT
EN
SHDN
MN
1
4
M
A
X
3241E
28
26
24
1
2
25
14
13
12
21
11
10
9
27
3
15
16
17
18
19
20
4
5
6
7
8
22
23
RI
R9
3
100K
C
125
1
00N
F
R9
2
100K
C
121
100N
F
DS
R
DC
D
R
107
100K
C
127
100N
F
3V3
J2
0
M
A
LE R
I
G
H
T
AN
GLED
5
4
3
2
1
9
8
7
6
10
11
C
126
1
00N
F
C
122
100N
F
DS
R
0
RI
0
R9
8
0R
D
CD0
RX
D
0
RS
2
3
2
CO
M
P
O
RT
0
TX
D
0
R
101
0R
R
103
0R
R
104
0R
R
105
0R
RT
S
0
R
106
0R
DT
R
0
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