Intern
ati
o
n
a
l
Journ
a
l of
Re
con
f
igur
able
and Embe
dded
Sys
t
ems
(I
JRES)
V
o
l.
4, N
o
. 3
,
N
o
v
e
m
b
er
2
015
, pp
. 17
8
~
18
4
I
S
SN
: 208
9-4
8
6
4
1
78
Jo
urn
a
l
h
o
me
pa
ge
: h
ttp
://iaesjo
u
r
na
l.com/
o
n
lin
e/ind
e
x.ph
p
/
IJRES
Desi
gn of Low Power Du
al Dyn
a
mic Node Flip-Flop Using Sleep
Transistor with NMOS
Ajees
h Kum
a
r, N. Sar
a
swathi
VLSI Design,
S
R
M Univer
si
ty
, Che
nna
i,
Indi
a
Article Info
A
B
STRAC
T
Article histo
r
y:
Received Apr 15, 2015
Rev
i
sed
Jun
27,
201
5
Accepte
d
J
u
l 20, 2015
This pape
r intro
duces a
Low Power
Dual D
y
namic Node Flip
Flop(DDFF)
using Sleep Transistor with NMOS.
The proposed design retains the logic
leve
l ti
ll th
e end
of evalu
a
t
i
on a
nd
pre-ch
arge mode. Th
e low po
wer DDFF
archi
t
ec
ture tha
t
com
b
ines
the
advant
ages
of dynam
i
c
and s
t
at
ic CM
OS
s
t
ructures
.
The
s
l
eep
trans
i
s
t
ors
approach
i
s
us
ed for le
a
k
age power
reduct
i
on. I
t
red
u
ces
le
akag
e cur
r
ent in
ide
a
l m
ode. Th
e perfo
rm
ance of
th
e
proposed flip f
l
op was compared with th
e conv
ention
a
l dual d
ynamic node
flip flop
(DDFF) in 90nm CMOS t
echnolog
y
with 1.2v supply
vo
ltag
e
at
room
tem
p
eratu
r
es
. Als
o
,
con
v
ention
a
l DDF
F
and DDF
F
us
ing S
l
eep
Trans
i
s
t
or with NM
OS are com
p
ared with othe
r com
p
licat
ed des
i
gns
and
realizes
b
y
a 4-bit
Johnson up
and
down counter
. The
p
e
rformance
improvements indicates th
at
th
e propos
ed d
e
signs are suited
for modern
high-perform
anc
e
CM
OS
circui
ts
where l
eakag
e power and
p
o
wer de
l
a
y
product ov
erhead are of major
concern.
Keyword:
Em
beddi
n
g
l
o
g
i
c
Flip
-fl
o
p
Leaka
g
e power
Lo
w po
wer
Po
wer del
a
y
pr
od
uct
Copyright ©
201
5 Institut
e
o
f
Ad
vanced
Engin
eer
ing and S
c
i
e
nce.
All rights re
se
rve
d
.
Co
rresp
ond
i
ng
Autho
r
:
Ajee
sh
K
u
m
a
r,
M.
Tech
, VLS
I
D
e
sign
, S
R
M Un
i
v
ersity,
C
h
en
n
a
i.
Em
a
il: aj
ish
kumar1
988
@g
mail.co
m
1.
INTRODUCTION
The l
o
w
po
we
r
chi
p
a
n
d sy
st
em
are usi
n
g f
o
r
bot
h i
ndustrial and educational
pu
rp
oses
. T
h
e i
n
du
st
ry
fo
r l
o
w
po
we
r el
ect
roni
c p
r
od
uct
s
are i
n
crea
si
ng ra
pi
dl
y
i
n
m
a
rket
. At
t
h
e sam
e
t
i
m
e
, newl
y
em
ergi
ng
C
M
O
S
pr
ocessi
ng
t
echn
o
l
o
gi
es
pre
s
ent
m
o
re requ
irem
en
ts to
t
h
e
p
o
wer
d
i
ss
ip
atio
n
of
d
i
gital syste
m
d
u
e
to
i
n
crease
d
de
vi
ce cou
n
t
,
s
p
ee
d an
d com
p
l
e
xi
t
y
. Po
wer
di
ssi
pat
i
on
of
V
L
SI c
h
i
p
s
has
been c
o
nt
i
n
u
ousl
y
i
n
creasi
n
g.
F
o
r hi
gh
pe
rf
or
m
a
nce l
o
w
p
o
w
er C
M
OS c
h
ip-desi
g
n the
choice of m
e
th
od
h
a
s a si
gn
ifican
t
effect
,
on t
h
e desi
g
n
t
i
m
e
and cost
. La
r
g
e no
of
gat
e
s are
prese
n
t
i
n
t
h
e
VLSI C
M
OS
sy
st
em
and gat
e
s ar
e
havi
ng
di
ffe
ren
t
param
e
t
e
rs d
u
e t
o
p
r
ocess
v
a
ri
at
i
on.
Po
wer
di
ssi
pat
i
on i
n
C
M
OS
st
ruct
u
r
es c
o
m
e
s fr
om
t
w
o com
pone
nt
s 1
)
St
at
i
c
di
ssi
pat
i
on i
s
d
u
e t
o
t
u
n
n
el
l
i
ng c
u
r
r
e
nt
t
h
r
o
u
g
h
ga
t
e
oxi
de, l
e
a
k
a
g
e cu
rre
nt
t
h
r
o
ug
h re
ver
s
e-
bi
ased di
odes
,
cont
e
n
t
i
on c
u
r
r
e
nt
i
n
rat
i
o
ed
ci
rc
ui
t
s
an
d c
u
r
r
ent
c
o
nd
uct
i
o
n t
h
r
o
u
g
h
O
FF t
r
ansi
s
t
ors.
St
at
i
c
p
o
w
er
co
ns
um
pt
ion
i
s
gi
ve
n
by
[3]
P
static
=
I
static
*
Vd
d
Whe
r
e
I
static
is
th
e curren
t
t
h
at flow in th
e ab
sen
ce
o
f
swit
ch
ing
.
(2
)
Dyna
m
i
c d
i
ssip
a
tion
is
du
e to ch
arg
i
n
g
and
di
sc
har
g
i
n
g o
f
l
o
a
d
ca
pa
ci
t
a
nces. I
f
gat
e
i
s
swi
t
c
he
d
on a
n
d
of
f pe
r
seco
nd t
h
en
p
o
we
r c
ons
um
pt
i
on i
s
gi
ve
n by
[
3
]
P
dynamic
= f*C
*
Vdd
2
Wh
ere
f is t
h
e
clo
c
k
frequ
ency, C is lo
ad
cap
acitan
ce and
Vdd
is
supp
ly v
o
ltag
e
.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
089
-48
64
I
J
RES Vo
l. 4
,
N
o
. 3
,
No
v
e
m
b
er
201
5
:
1
78
–
18
4
17
9
I
n
sy
n
c
hro
nous syste
m
w
e
ar
e u
s
i
n
g
f
lip f
l
op
s.
H
i
gh
sp
eed h
a
s
b
e
en ach
iev
e
d
u
s
i
n
g
p
i
pelin
ed
techniques [1]. In progres
s
ive,
deep-pi
p
elined architecture
s
, pus
hi
ng
the
spee
d excepti
ng dem
a
nds a lowe
r
p
i
p
e
lin
e
ov
erhead
. Th
is
o
v
e
rh
ead
is laten
c
y an
alo
gou
s
with
th
e p
i
p
e
line ele
m
en
ts, similar as flip
-fl
o
p
s
and
latch
e
s. Sub
s
tan
tially, work
has b
e
en
d
e
d
i
cated
to
im
p
r
o
v
e
t
h
e
per
f
o
r
m
a
nce of
t
h
e
fl
i
p
-
f
l
ops i
n
t
h
e
pa
s
t
few
decade
s
. T
h
e
factors
which a
r
e rec
o
mm
endable in latc
hes
and flip-fl
ops
are (1)
Hi
gh s
p
eed, (2) L
o
w
powe
r
co
nsu
m
p
tio
n
,
(3
) Robu
stn
e
ss an
d
no
ise stabilit
y, (4
) Sm
all
area and
less n
u
m
b
e
r of tran
sistors, (5
)
Su
pp
ly
v
o
ltag
e
scalab
i
lity, (6
)
Less i
n
tern
al activ
ity in
id
eal con
d
iti
o
n
.
Hy
bri
d
l
a
t
c
h fl
i
p
-fl
op (
H
L
F
F
)
and sem
i
dynam
i
c fl
i
p
-fl
o
p
(S
DFF
)
are
obs
er
vi
n
g
t
h
e cl
assi
c hi
gh
-
per
f
o
r
m
a
nce of fl
i
p
fl
o
p
s [
1
]
.
Fl
i
p
-fl
op
s can be desi
g
n
e
d
by
t
w
o t
y
pe (1) S
t
at
i
c
l
ogi
c, (
2
)
Dy
nam
i
c
l
ogi
c st
y
l
e.
Dy
nam
i
c l
ogi
c occu
pi
es l
e
ss area and
hi
g
h
spee
d,
on
ot
her
h
a
nd st
at
i
c
l
ogi
c can
not
have c
h
ar
ge s
h
ari
n
g
p
r
ob
lem
.
No
w
we con
s
id
er a
h
ybrid
flip
flop
wh
ich
is
w
o
r
k
i
n
g l
i
k
e dy
na
m
i
c and st
at
i
c
l
ogi
c [
1
]
,
[
3
]
.
Hy
bri
d
desi
g
n
has a
n
i
n
t
e
r
n
al
dy
nam
i
c no
de an
d st
at
i
c
out
p
u
t
no
de,
i
n
fl
i
p
fl
op
de
si
gn
. On
ot
he
r han
d
sem
i
dy
nam
i
c
flip
-flop
(SDFF)
works effi
cien
tly an
d
h
a
v
e
d
i
fferen
t
cap
ab
ilities. It h
e
lps to
redu
ce th
e laten
c
y in
flip flop
design. Powe
r, delay and a
r
ea
are m
a
in conc
erns
.
In rece
nt
y
ear
ot
her ne
w fl
i
p
-
f
l
o
ps we
re i
n
t
r
od
uce
d
l
i
k
e cross cha
r
ge cont
rol
fl
i
p
-fl
o
p
(XC
FF)
,
wh
ich
h
a
s m
a
n
y
adv
a
n
t
ag
es
o
v
e
r
o
t
h
e
r types of flip-fl
op
s in
sp
eed and
p
o
wer [1
]. B
u
t th
is arch
itecture still
has s
o
m
e
draw
back
s bec
a
use
of
re
du
n
d
ant
p
o
we
r
di
ssi
pat
i
o
n a
n
d
l
a
rge
h
o
l
d
t
i
m
e. Hi
gh
p
e
rf
orm
a
nce fl
i
p
-
fl
o
p
will h
a
v
e
a
h
i
gh
clo
c
k
frequ
en
cy to
sp
eed
up
th
e system
.
Du
e to
h
i
gh
cl
o
c
k frequ
e
n
c
y
o
f
system
h
a
v
i
n
g
larg
e
am
ount
p
o
we
r
di
ssi
pat
i
o
n.
To
day
t
h
i
s
i
s
c
h
al
l
e
ngi
n
g
f
o
r el
e
c
t
r
o
n
i
c
en
gi
nee
r
s.
Thi
s
pa
per i
s
di
vi
de
d as f
o
l
l
o
ws:
(
2
) St
ud
y
of exi
s
t
i
ng
f
l
i
p
fl
op
, (3
) P
r
o
p
o
sed l
o
w p
o
we
r D
D
F
F
archi
t
ect
u
r
e
a
n
d o
p
erat
i
o
n of
p
r
o
p
o
se
d fl
i
p
-fl
o
p
,
(
4
)
P
r
op
ose
d
ELM
, (5
)
Si
m
u
l
a
t
i
on
s
e
t
u
p
an
d res
u
l
t
,
(
6
)
concl
u
si
o
n
.
2.
E
X
ISTI
NG F
L
IP-FLOP
S
Dual
dy
nam
i
c
no
de fl
i
p
-fl
op
i
s
a cl
assi
c hi
gh-
per
f
o
rm
ance fl
i
p
-fl
op
. C
o
n
v
ent
i
o
nal
hy
br
i
d
l
a
t
c
h an
d
sem
i
dy
nam
i
c
fl
i
p
fl
o
p
s a
r
e so
m
e
ki
nd o
f
hy
bri
d
fl
i
p
-
f
l
o
ps.
The spee
d o
f
HLFF i
s
sl
o
w
but
i
t
cons
um
es l
e
ss
p
o
wer. Ch
arg
e
sh
ari
n
g
p
r
ob
lem can
b
e
red
u
c
ed
u
s
i
n
g
sp
littin
g
i
n
tern
al capacitan
ce. Sem
i
d
y
n
a
m
i
c flip
-flo
p
i
s
faster,
with
sho
r
ter
ho
ld
time an
d
a
b
e
tter
in
pu
t no
is
e re
j
ect
i
on b
u
t
m
o
re po
wer i
s
c
o
nsum
ed. Ne
w
hy
b
r
i
d
flip
flop
is
g
i
v
e
n
b
e
l
o
w wh
ich is b
e
tter th
an ab
ov
e
o
n
e.
W
h
i
c
h i
s
ope
rat
e
d u
n
d
er t
w
o
m
ode (1
) eval
uat
i
o
n
pha
se
(
2
) pre
-
c
h
ar
ge p
h
ase [1
]
.
A. E
val
ua
ti
on
phase
In
th
is
ph
ase if CLK =1
th
en
it works in
ev
alu
a
tion
s
p
h
ase. An
d
i
n
pu
t
d
a
ta (D) =0
th
an
no
d
e
i
s
d
i
sch
a
rg
ed
thro
ugh
th
e N1
, N2
,
N3. Th
e lo
g
i
c v
a
lu
e
will b
e
0
.
This latch
i
n
g
o
c
cu
rs
d
u
ring
the 1
-
1
o
v
e
rlapp
i
ng
of CLK and
CLKB. Th
e l
o
g
i
c
v
a
lu
e zero
is
main
tain
ed
b
y
th
e in
v
e
rter p
a
ir INV1
and
INV2
till
eval
uat
i
o
n p
h
a
s
e get
s
ove
r.
The n
o
d
e X
1
B
i
s
hi
gh i
n
al
l
proces
s an
d QB
(QB
A
R
)
d
i
schar
g
e t
o
zer
o. T
h
e
o
u
t
p
u
t
m
a
in
tai
n
ed
b
y
inv
e
rter p
a
ir
INV3
an
d
INV4
till n
e
x
t
ev
al
u
a
tio
n p
h
a
se. Th
e
no
d
e
X2
is h
i
gh
wh
en
in
pu
t d
a
ta
(D)
= 1
thro
ugh
ou
t
th
e ev
al
u
a
tion p
h
ase.
If i
n
put d
a
ta (D) =
0
,
Th
en
X1
no
d
e
will b
e
log
i
c
1
an
d
X2 will b
e
at l
o
g
i
c
0
.
QB
wil
l
b
e
ch
arg
e
d
throug
h P2.
X2 re
m
a
in
zero till en
d[1
]
.
Fi
gu
re 1.
D
D
F
F
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
RES I
S
SN
:
208
8-8
7
0
8
Desi
g
n
of
L
o
w
Pow
e
r
D
ual
D
y
na
mi
c N
ode
F
l
i
p
-Fl
o
p
Usi
n
g
Sl
eep
Tr
a
n
si
st
or w
i
t
h
N
M
O
S
(Ajeesh Kumar
)
18
0
B
.
Pre-c
h
ar
ge
phase
In t
h
i
s
C
L
K=
0
and i
n
p
u
t
dat
a
(D
) co
ul
d
be e
i
t
h
er zer
o
or
o
n
e.
It
can al
s
o
be cal
l
e
d as
ho
l
d
i
ng
p
h
ase.
Th
e
X1 nod
e
re
m
a
in
s lo
g
i
c
1 and
X1
B
will b
e
l
o
g
i
c
0
.
N1
tran
sistor stop
s th
e tak
i
n
g
of n
e
x
t
v
a
lu
e of in
pu
t
d
a
ta (D) un
til th
e en
d of
p
r
ech
a
rg
e
p
h
ase [1]. So
t
h
e
p
r
ev
i
o
u
s
v
a
l
u
e
o
f
ou
tpu
t
will b
e
held
. Th
is
d
e
sign
h
a
s
negat
i
v
e set
u
p
t
i
m
e
and posi
t
i
v
e hol
d t
i
m
e. It
has sho
r
t
t
r
ans
p
are
n
cy
per
i
od beca
use
of
1-1
ove
rl
ap
pi
ng
o
f
CLK and CLKB. This eliminates race condition. The
inve
rter pai
r
INV1, INV2
a
nd INV3, INV4
were
d
e
sign
ed
with
static C
M
OS. Du
e to
th
is inverter p
a
ir
larg
e leak
ag
e cu
rren
t is p
r
esen
t in th
e flip
-flop
.
Wh
en
t
echn
o
l
o
gy
sca
l
es d
o
w
n
t
o
90
nm
and
bel
o
w
t
h
en i
t
c
o
n
s
um
e u
nnece
ssary
po
we
r.
3.
PROP
OSE
D
FLIP
FLOP
In t
h
e
pr
o
pose
d
fl
i
p
fl
op
t
h
e
i
nve
rt
er
pai
r
s
are
desi
g
n
e
d
usi
n
g l
e
a
k
age
po
we
r re
d
u
ct
i
o
n
t
ech
ni
q
u
e
known as
sleep transistor a
ppro
ach
with
NM
OS. Th
e static CMOS inv
e
rter
pai
r
i
s
repl
ac
ed by
sl
ee
p t
r
a
n
si
st
o
r
app
r
oach
wi
t
h
NM
OS
.
Whe
n
a st
at
i
c
C
M
O
S
i
n
vert
er
i
s
u
s
ed
bel
o
w
9
0
n
m
t
echnol
ogy
,
t
h
e s
u
p
p
l
y
v
o
l
t
a
ge i
s
redu
ced
wh
ich cau
ses t
h
resho
l
d
vo
ltag
e
redu
ctio
n th
at
will furth
e
r in
creases leak
ag
e curren
t
. Th
is tech
n
i
q
u
e
i
s
a co
m
b
i
n
at
i
on
of t
h
e sl
eep
t
r
ansi
st
or a
nd
NM
OS st
ac
k t
echni
que
. It
us
es t
h
e hi
gh t
h
r
e
sh
ol
d t
r
ansi
st
ors i
.
e.
,
m
u
l
ti-
th
r
e
sho
l
d
techn
i
qu
e
[3
],
[4
].
The sl
eep t
r
a
n
si
st
or ap
pr
oac
h
wi
t
h
NM
OS
i
s
sho
w
n i
n
t
h
e Fi
gure
3 P1
, N2
, are hi
g
h
t
h
res
h
ol
d an
d
N1
, P
2
,
N
3
a
r
e
l
o
w
t
h
resh
ol
d
vol
t
a
ge
t
r
a
n
si
st
ors
.
It
w
o
r
k
s i
n
t
w
o
m
ode (
1
)
Act
i
v
e m
ode,
(
2
)
Sl
eep
m
ode
Fi
gu
re
2.
B
a
si
c I
nve
rt
er
Sl
eep T
r
an
si
st
ors
are
hi
gh
t
h
res
h
ol
d t
r
ansi
st
ors c
onn
ected
in series wi
th
low thresh
old
log
i
c as
sh
own
Figu
re 3
.
Wh
en
th
e main
circu
it consistin
g
of
low thres
hol
d de
vi
ces are ON the
sleep transistors are
also
ON resu
ltin
g
in
no
rm
al
o
p
e
ration
o
f
th
e circu
it.
Figu
re 3.
Sleep
Tra
n
sisto
r
with NM
OS
Whe
n
t
h
e ci
rc
ui
t
i
s
i
n
St
and
b
y
m
ode eve
n
hi
g
h
t
h
res
h
ol
d
t
r
ansi
st
o
r
s are
OFF
.
Si
nce hi
gh t
h
res
hol
d
devices
appea
r
in se
ries
with low
t
h
res
h
o
l
d ci
rc
ui
t
t
h
e
l
eakage
cu
rre
n
t
i
s
det
e
rm
i
n
ed
by
hi
gh
t
h
r
e
sh
ol
d
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
089
-48
64
I
J
RES Vo
l. 4
,
N
o
. 3
,
No
v
e
m
b
er
201
5
:
1
78
–
18
4
18
1
d
e
v
i
ces and
is
v
e
ry l
o
w. So
t
h
e
n
e
t static po
wer
d
i
ssi
p
a
tion
is
redu
ced
.
i
n
add
itio
n on
e l
o
w tran
sisto
r
parallel
is add
e
d in
pu
ll do
wn
n
e
tworks wh
ich in
creases th
e
t
h
res
h
o
l
d
v
o
l
t
a
ge an
d im
pro
v
es the
l
eakage
current.
Th
e pr
opo
sed
f
lip
f
l
op
is sh
ow
n
in
f
i
gu
r
e
3. W
h
en
th
is Sleep
Tran
sistor with
NMOS is u
s
ed
in
t
h
e
flip
flop
, th
en
p
o
wer redu
ction
in
flip
flop
can
b
e
don
e b
y
o
p
e
ratin
g
th
e
flip
flop
in
sleep
m
o
d
e
. Th
e to
tal
po
we
r i
s
al
so r
e
duce
d
i
n
act
i
v
e m
ode. Thi
s
ope
rat
e
s i
n
eva
l
uat
i
on
phase a
nd
pre
-
c
h
ar
ge
pha
se. T
h
e l
a
t
c
hi
n
g
of
dat
a
i
n
p
u
t
o
ccurs
i
n
e
v
al
u
a
t
i
on pha
se
a
n
d
hol
di
n
g
of
t
h
e out
put
dat
a
occ
u
rs
i
n
p
r
e-c
h
ar
ge pha
se.
Fi
gu
re
4.
Pr
o
p
o
se
d D
D
F
F
usi
n
g
Sl
eep
Tra
n
s
i
st
or a
p
p
r
oach
wi
t
h
NM
OS
Fi
gu
re
5.
O
u
t
p
ut
W
a
ve
fo
rm
of P
r
o
p
o
sed
D
D
F
F
4.
PROP
OSE
D
ELM
The p
r
op
ose
d
dual
dy
nam
i
c
hy
b
r
i
d
fl
i
p
fl
o
p
wi
t
h
em
bedd
i
ng l
o
gi
c i
s
sh
ow
n i
n
fi
g
u
re
5. N
o
t
e
t
h
at
i
n
pr
o
pose
d
em
beddi
ng
l
o
gi
c m
odel
,
t
h
e i
n
p
u
t
dat
a
(D
) i
s
repl
ace
d by
p
u
l
l
do
wn
net
w
o
r
k
of
C
M
OS a
nd t
h
e
cl
ocki
n
g
sche
m
e
i
s
char
ge
s
h
ari
n
g
.
C
h
ar
ge
sha
r
i
n
g
pr
o
b
l
e
m
occurrs
i
n
t
h
e m
odel
d
u
e t
o
t
h
e cl
ocki
ng
.
Whi
c
h
becom
e
s i
n
su
b
o
r
d
i
n
at
e as
t
h
e
num
ber
of
NM
OS t
r
ansi
st
or i
n
t
h
e
p
u
l
l
d
o
w
n
net
w
or
k i
n
cr
eases.
Fi
gu
re
6.
Pr
o
p
o
se
d D
D
F
F
E
m
bedded
It
has bee
n
si
m
u
l
a
t
e
d and e
x
am
i
n
ed wi
t
h
di
ffe
re
nt
em
bedde
d l
o
gi
c an
d
t
h
e am
ount
o
f
wo
rst
case
char
ge
s
h
a
r
i
n
g has bee
n
cal
cul
a
t
e
d.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
RES I
S
SN
:
208
8-8
7
0
8
Desi
g
n
of
L
o
w
Pow
e
r
D
ual
D
y
na
mi
c N
ode
F
l
i
p
-Fl
o
p
Usi
n
g
Sl
eep
Tr
a
n
si
st
or w
i
t
h
N
M
O
S
(Ajeesh Kumar
)
18
2
Fi
gu
re 7.
Em
bedde
d Fu
nct
i
o
n (A
) AN
D.
(B
)
OR
.
(C
) 2:
1
M
U
X
Fi
gu
re 8.
O
u
t
p
ut
W
a
ve
fo
rm
of 2
I
n
put
A
N
D
Fi
gu
re
9.
O
u
t
p
ut
W
a
ve
fo
rm
of OR
Fi
gu
re 1
0
. O
u
t
put
Wa
vef
o
rm
of
M
U
X
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
089
-48
64
I
J
RES Vo
l. 4
,
N
o
. 3
,
No
v
e
m
b
er
201
5
:
1
78
–
18
4
18
3
5.
SIMULATION
SET
U
P AND RESULTS
C
a
dence i
s
l
e
a
d
i
n
g p
r
o
v
i
d
er
of PC
base
d e
l
ect
roni
c
desi
g
n
aut
o
m
a
ti
on
soft
ware s
o
l
u
t
i
on
. P
o
we
r
con
s
um
pt
i
on a
n
d
sp
eed
pe
rf
o
r
m
a
nces are e
x
am
i
n
ed f
o
r
exi
s
t
i
ng a
n
d
pr
op
ose
d
m
odel
.
Fig
u
r
e
11
.
4
-
b
i
t Joh
n
s
on
u
p
an
d dow
n coun
ter
The si
m
u
l
a
t
i
o
n we
re pe
rf
or
m
e
d i
n
90
nm
t
echn
o
l
o
gy
. T
h
e su
p
p
l
y
vol
t
a
ge i
s
gi
ve
n a
s
1.
2v
fo
r t
h
e
si
m
u
latio
n
.
The flip
flop
o
p
e
rated
at
2
GHz clo
c
k freq
u
e
n
c
y. It
h
a
s n
e
gativ
e set up
ti
me an
d
po
sitive ho
ld
t
i
m
e
wi
t
h
respect
t
o
C
L
K and C
L
KB
. Fi
n
a
l
l
y
a 4-bi
t
Johns
o
n
u
p
an
d
do
w
n
co
unt
e
r
i
s
desi
gne
d f
o
r t
h
e
per
f
o
r
m
a
nce anal
y
s
i
s
of
D
D
FF
usi
n
g sl
ee
p t
r
a
n
si
st
o
r
a
p
pr
oac
h
wi
t
h
NM
OS
. T
h
e
r
easo
n
o
f
c
h
oo
si
ng a
counter is that
the in
ternal data
activity
at each
bit is known.
Tabl
e
I
.
In
vert
er per
f
o
r
m
a
nce
Inverter
Na
m
e
Leakage Power
Total Power
CM
OS I
nver
t
er
5952.
5
p
W
458nW
Sleep T
r
ansistor
with NM
OS
1863
pW
325nW
Table II. Perform
ance of
DDFF
Flip Flop
Leakage Power
Total Power
Dealy
PDJ
DDFF 5059
nW
55.
86uW
4.
6899
ns
202.
4
f
J
Pr
oposed DDFF
20.
74nW
53.
70uW
3.
008ns
168
fJ
Tabl
e I
I
I
.
T
o
t
a
l
p
o
we
r c
o
nsum
pt
i
o
n
at
d
i
fferen
t
d
a
ta activ
ity b
y
DDFF
Flip Flop/T
o
tal Power
100%
50%
25%
0%
DDFF 78.
23
70.
00
65.
01
13.
13
Pr
oposed DDFF
74.
03
68.
13
60.
00
12.
65
Tabl
e I
V
.
Pe
rf
orm
a
nce o
f
em
bed
d
e
d
fu
nct
i
o
n
Em
bedded Function
L
eakage Po
wer
Total
Power
Delay
PDJ
2 input AND
54.59nW
64.
81uW
88.78ns
.0057
fJ
2 input OR
70.
81nW
108.
75
uW
82.
49ns
.
009fJ
M
ux 110nW
185.
6uW
70.
06ns
.
013fJ
6.
CO
NCL
USI
O
N
The re
sults are
com
p
ared
with th
e e
x
i
s
t
i
ng
t
echni
q
u
es
. T
h
e pr
o
pose
d
D
D
FF
usi
n
g sl
e
e
p t
r
a
n
si
st
o
r
approach with NM
OS elim
inates the
l
eaka
g
e po
we
r. The
o
v
erl
a
p peri
o
d
of
cloc
k t
h
at is re
quired to select
pr
o
p
er
wi
dt
h
has
bee
n
pr
o
v
i
d
e
d
i
n
or
de
r t
o
m
a
ke de
si
gn
si
m
p
l
e
r.
The e
x
peri
m
e
nt
re
sul
t
s
h
o
w
s a
n
im
provem
ent in leaka
g
e
power a
n
d dela
y.
The
better cas
e of internal
data
activ
ity h
a
s b
e
en
foun
d ou
t.
The
i
n
p
u
t
ve
ct
or
s r
e
duce
s
l
eaka
g
e
p
o
we
r.
The efficiency of
DDFF usi
n
g sle
e
p
tran
sistor ap
pro
ach with
NMOS
has bee
n
hi
g
h
l
i
ght
e
d
usi
ng a
4
-
bi
t
Jo
h
n
so
n
u
p
an
d d
o
w
n c
o
unt
e
r
. T
h
e spe
e
d o
f
t
h
e p
r
op
o
s
ed D
D
F
F
i
s
sam
e
as
th
e ex
isting
.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
RES I
S
SN
:
208
8-8
7
0
8
Desi
g
n
of
L
o
w
Pow
e
r
D
ual
D
y
na
mi
c N
ode
F
l
i
p
-Fl
o
p
Usi
n
g
Sl
eep
Tr
a
n
si
st
or w
i
t
h
N
M
O
S
(Ajeesh Kumar
)
18
4
ACKNOWLE
DGE
M
ENTS
I sincerely ac
knowledge
in al
l earne
stness
, t
h
e ca
da
n
ce lab pr
ov
id
ed b
y
Facu
l
t
y
of
E
ngi
neeri
n
g
an
d
Tech
nol
ogy
,
S
R
M
Uni
v
ersi
t
y
, che
n
na
i to
end
eavou
r th
is
p
r
o
j
ect.
REFERE
NC
ES
[1]
Kalarikk
al Abse
l, Li
jo Manuel
,
R.K.
Kavitha,
Low-Power Dual D
y
namic N
ode
Pulsed H
y
bridFlip-Flop Featurin
g
Efficient Embed
d
ed Logic,
IEEE Transactions
on very large sc
ale in
tegration
(
V
LSI)
systems
, vol. 21, no.
9
,
september 2013
[2]
H
.
P
a
trovi, R. B
u
rd, U
.
S
a
lim
, F
.
W
e
ber,
L. Di Gr
egorio, and D. D
r
aper,
Flow thro
ugh latch and ed
ge triggered flip
flop h
y
brid e
l
em
ents
,
in Proc. I
E
EE ISSCC Dig.
Tech
. Pap
e
rs, Feb.1997, pp.138-
139
[3]
J.M. Rabaey
,
A. Chandrak
asan, and
B
.
Niko
lic, Digital In
tegrated C
i
rc
uits: A Design Perspectiv
e, 2nd
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Englewood C
liff
s
, NJ: PrenticeH
all, 2003
.
[4]
J.C. Park and V.J. Mooney
III
,
Sleep
y
stack leakage reduction
,
IEEE T
r
ans. VL
SI Systems
, vol. 14, no. 11, pp.
1250-1263, Nov. 2006.
[5]
O. Sarbishei
an
d M. Ma
y
m
and
i
Neja
d
,
A No
vel Overlap-Bas
e
d Logic Cell:
An Effici
ent
Im
plem
enta
tion of
FlipFlops with
Embedded Logic,
IEEE Trans. Very Large Scale Integr. (
V
LSI) Syst
., vol. 18, no. 2, pp. 222231
,
Feb. 2010
.
[6]
J. Yuan and C. Svensson, New
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