Intern
ati
o
n
a
l
Journ
a
l of
Re
con
f
igur
able
and Embe
dded
Sys
t
ems
(I
JRES)
V
o
l. 4,
N
o
.
2
,
Ju
ly 20
15
, pp
. 63
~70
I
S
SN
: 208
9-4
8
6
4
63
Jo
urn
a
l
h
o
me
pa
ge
: h
ttp
://iaesjo
u
r
na
l.com/
o
n
lin
e/ind
e
x.ph
p
/
IJRES
FPGA Synthesis of Reconfigur
able M
o
dules f
o
r FI
R Filt
er
Sar
a
n
y
a
R
*
,
P
r
adeep
C
*
,
Ne
ena B
a
b
y
*,
R
Ra
dh
akri
shn
a
n*
*
*Departm
ent of Ele
c
troni
cs
an
d
Communication, Saintgits Colleg
e of
Engin
eering
,
India
**Vidh
y
a Mand
hir Institute of
Technol
og
y
,
Peru
ndurai, Tamilnadu, India
Article Info
A
B
STRAC
T
Article histo
r
y:
Received Nov 13, 2014
Rev
i
sed
D
ec 19
, 20
14
Accepte
d
Ja
n 12, 2015
Reconfigur
able
com
puting for
DS
P
rem
a
ins
an act
ive
are
a
to
e
xplore as
the
need for incorpo
r
ation with more convention
a
l DSP technologies turn out to
be obvious. Co
nvention
a
lly
,
th
e majority
of
the work in
th
e ar
ea o
f
reconfigur
able computing is aimed on
fine grain
e
d FPGA devices. Over the
ye
ars, th
e focus
is shifted from
bit le
v
e
l granu
l
arit
y
to a co
ar
s
e
grained
composition. FI
R filter remains
and pers
ist
to be
an im
portan
t
bu
ilding b
l
ock
in various DSP system
s. It com
p
utes
the output b
y
m
u
ltipl
y
i
ng in
put sam
p
les
with a set of coeffic
i
ents follow
e
d b
y
addi
tion.
Here m
u
ltipli
ers and adders
are modeled using the
concept
of di
vide and
conquer. For d
e
veloping
a
reconfigu
a
rbl
e
FIR filter
,
diff
erent
tap f
ilt
ers are d
e
signed
as separa
t
e
reconfigur
able modules. Furthermore,
there
is an additional
concern f
o
r
making the s
y
stem fault toleran
t
. A f
a
ult detection mechanism is introduced
to detect th
e faults based on
the na
tu
re of
op
erands.
The r
e
configurable
modules are structurally
modeled
in Ver
ilog
HDL and simulated and
s
y
nthesi
zed usin
g Xilinx ISE 14.2. A co
m
p
arison of the device ut
iliz
ation of
reconfigur
able modules is also presen
ted
in this
paper b
y
implementing the
design on v
a
riou
s Virt
ex FPGA devices.
Keyword:
Data Path
Fau
lt Detection
Fau
lt In
sertio
n
FIR Filter
FPGA
Reco
nfigu
r
ation
Copyright ©
201
5 Institut
e
o
f
Ad
vanced
Engin
eer
ing and S
c
i
e
nce.
All rights re
se
rve
d
.
Co
rresp
ond
i
ng
Autho
r
:
Sara
nya R,
Depa
rt
em
ent
of El
ect
r
oni
cs
a
n
d
C
o
m
m
uni
cat
i
on,
Sain
tg
its Co
lleg
e
o
f
Eng
i
n
e
erin
g
,
Ko
ttuku
lam
Hi
lls, Path
am
u
tto
m
P.O, Ko
ttaya
m
-
6
865
32
.
Em
a
il: saran
y
a1
811
90@g
m
ai
l.co
m
1.
INTRODUCTION
Owi
n
g
to
t
h
e exp
e
d
itiou
s
ad
v
a
n
ce i
n
algo
rith
m
s
an
d ap
p
lication
s
in Dig
ital Sign
al Pro
c
essing
(DSP), the
r
e
has
bee
n
a
n
e
m
erging
neces
sity for ada
p
t
a
ble arc
h
itectur
es with dyna
mic
reconfiguration
cap
ab
ilities. Th
e area
of reco
nfigu
r
ab
le com
p
u
tin
g
h
a
s
been
in
sp
ired
by th
e con
s
id
erab
le ch
ang
e
s i
n
th
e
application space of
DSP.
FIR filters are
used i
n
m
a
j
o
rity of t
h
e DSP
base
d electronic system
s. The
d
i
sclo
su
re
o
f
ch
allen
g
i
n
g
applicatio
n
s
in
requ
isites o
f
p
o
wer, sp
eed, p
e
rfo
r
man
ce an
d
reusab
ility
m
a
k
e
i
t
v
ital
to
d
e
sign
reconfigu
r
ab
le arch
itectu
r
es.
FIR filters
h
a
s ex
ten
s
i
v
e ap
plicab
ility b
u
t
it
m
a
y re
q
u
i
re a larg
e
nu
m
b
er o
f
co
efficien
ts to
g
e
t t
h
e
pre
f
er
red
re
qui
rem
e
nt
. Hence
i
t
resul
t
s
i
n
t
h
e
l
a
rge
num
ber
of sl
i
ce f
o
r t
h
e
FPG
A
desi
g
n
.
There
f
ore,
dy
n
a
m
i
c
recon
f
i
g
urab
le
d
e
sign
o
f
h
i
gh
er o
r
d
e
r
tap
FIR
filters
u
s
i
n
g
t
r
ad
ition
a
l FPGA d
e
sign
tech
n
i
qu
es h
a
s
certain
d
i
sadv
an
tag
e
s. On
e of t
h
e imp
o
rtan
t
d
i
sadvan
t
ag
es is th
e
co
nfigu
r
ation
t
i
m
e
, wh
ich is
th
e ti
m
e
u
s
ed
u
p
for
reco
nfi
g
u
r
at
i
o
n. Thi
s
rel
i
e
s
on t
h
e rec
o
n
f
i
g
ura
b
l
e
devi
ce and t
h
e t
echni
que
of re
con
f
i
g
urat
i
o
n
.
Part
i
a
l
Reco
nfigu
r
ation
can
b
e
u
s
ed
in
th
is case. Partial reco
nfigu
r
ation
resu
lts in
less
con
f
i
g
u
r
at
i
on t
i
m
e, provi
des
flex
ib
ility an
d
area co
m
p
eten
ce fo
r
h
i
gh
er
ord
e
r FIR
filters.
In
t
h
i
s
pa
per
,
we
pres
ent
t
h
e
sy
nt
hesi
s
o
f
r
econ
f
i
g
ura
b
l
e
m
odul
es (
2
-t
a
p
an
d
3-t
a
p)
f
o
r
b
o
t
h
seri
al
and pi
plined F
I
R filters. Th
e
rec
o
nfigura
b
l
e
m
odules are
m
odelled usi
n
g an area
efficient data
path
with
o
n
lin
e
fau
lt d
e
tectio
n
m
ech
a
n
ism
[2
] b
a
sed o
n
th
e
n
a
ture
o
f
o
p
e
ran
d
s
. Sep
a
rate m
u
ltip
l
i
er an
d
add
e
r
b
l
o
c
ks
are d
e
si
g
n
e
d
based
on
th
e con
cep
t
o
f
d
i
v
i
d
e
an
d
co
nqu
er
[1
] ap
pro
ach
t
o
m
o
d
e
l th
e FIR filter. A
well-kn
own
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
089
-48
64
IJR
E
S V
o
l
.
4, No
. 2,
J
u
l
y
20
1
5
:
6
3
– 70
64
tech
n
i
qu
e to
attain
fau
lt
d
e
tectio
n
is
du
p
licatio
n
with
com
p
ariso
n
wh
ere sim
ilar calc
u
latio
n is p
e
rfo
r
m
e
d
twice and the
out
puts a
r
e c
o
m
p
ared to rec
o
gnize errors
.
In
or
de
r t
o
de
t
ect
a faul
t
[
1
2]
, fa
ul
t
nee
d
s
t
o
be
in
trodu
ced
i
n
to th
e circu
it. For th
e v
e
rificatio
n
o
f
t
h
e fau
lt d
e
tectio
n, fau
lts are in
tro
d
u
c
ed
in
th
e
‘.x
d
l
’
file o
f
t
h
e dat
a
pat
h
[
2
]
.
Desi
gn
of
r
econ
f
i
g
ura
b
l
e
m
odul
es i
s
do
ne i
n
Veri
l
o
g
HDL
. It
i
s
si
m
u
l
a
t
e
d an
d sy
n
t
hesi
zed
u
s
ing
Xilinx
ISE 14
.2
. Th
e d
e
sign
is i
m
p
l
e
m
en
ted
on
variou
s Virtex
FPGA d
e
v
i
ces to
o
b
t
ain
t
h
e b
e
tter
d
e
v
i
ce u
tilizatio
n. Th
e syn
t
h
e
sis resu
lt is u
s
ed
to
ob
tain
the p
e
rform
a
n
ce
o
f
th
e system
i
n
term
s o
f
area and
del
a
y
.
The rest
o
f
t
h
e
pape
r i
s
or
gan
i
zed as fol
l
o
ws
. Sect
i
on
2 gi
v
e
s a bri
e
f de
sc
ri
pt
i
o
n o
f
rel
a
t
e
d w
o
r
k
s i
n
t
h
i
s
area. Sec
t
i
on 3
desc
ri
b
e
s t
h
e arc
h
i
t
ect
ure
of t
h
e
r
econ
f
i
g
ura
b
l
e
m
odul
es. Sect
i
on
4 p
r
ese
n
t
s
t
h
e
eval
uat
i
o
n a
n
d
sy
nt
hesi
s
res
u
l
t
s
. Fi
n
a
l
l
y
t
h
e c
oncl
udi
ng
rem
a
rk
an
d
fut
u
re
wo
rk
i
s
prese
n
t
e
d i
n
sect
i
o
n
5.
2.
RELATED WORKS
Th
e id
ea
o
f
reco
nfigu
r
ab
le com
p
u
tin
g
h
a
s
been
in
ex
isten
c
e for qu
ite someti
me [1
1
]
.
Wang
Lie an
d
Wu
Feng-yan
p
u
b
lish
e
d
a
p
a
p
e
r
on
Dy
n
a
m
i
c Partial Recon
f
i
g
uratio
n (DPR) [4
] in
FPGAs and
illu
strated
th
e
adva
ntage
s
of early
access partial
reconfi
g
uration.
A
rec
o
nfigura
b
le FIR filter [14]
design
usi
n
g dy
nam
i
c
p
a
rtial recon
f
i
g
uration
is p
r
esen
te
d, wh
ich
h
a
s area efficien
cy and
flex
i
b
ility al
lo
wing d
y
n
a
m
i
cal
in
sertio
n
an
d
rem
o
v
a
l of p
a
rtial
m
o
d
u
les u
s
ing
Xilinx
Virtex
-2
XC2
v60
00
FPGA. A
d
i
g
it-reconfigu
r
ab
le FIR
filter
[1
3]
arc
h
i
t
ect
u
r
e
wi
t
h
fi
ne
gra
nul
a
r
i
t
y
i
s
pres
ent
e
d a
n
d i
m
pl
em
ent
e
d u
s
i
n
g
C
M
OS t
ech
n
o
l
ogy
.
The c
o
ncept
o
f
ext
e
nda
bl
e a
n
d
reus
abl
e
a
r
i
t
h
m
e
ti
c uni
t
s
[1
0]
ha
ve
bee
n
p
r
o
p
o
sed
by
sev
e
ral
g
r
ou
p
s
since it affects the perform
a
nce of th
e entire
syste
m
. An are
a
and tim
e
effi
cient reconfi
g
urab
le arith
m
e
ti
c u
n
i
t
[5]
,
a l
o
w
p
o
w
er
l
o
w c
o
st
com
put
at
i
onal
m
odel
f
o
r
m
u
l
t
i
m
e
di
a appl
i
cat
i
ons
[
6
]
,
or
gani
sat
i
o
n
a
n
d
FP
GA
im
pl
em
ent
a
t
i
o
n of M
O
R
A
p
r
oces
so
r core
[
7
]
are pr
op
ose
d
. Per
f
o
rm
ance com
p
ari
s
on
of di
ffe
rent
p
r
evi
o
us
recon
f
i
g
urab
le
d
a
ta p
a
t
h
s
was illu
strated
an
d two n
e
w
p
r
o
c
essin
g
elem
en
t
s
were
p
r
o
p
o
s
ed
an
d its ev
al
uatio
n
i
s
do
ne
[
8
]
.
Ho
we
ver
pre
v
i
o
us a
p
p
r
oa
c
h
es
have m
a
ny
di
sa
dva
nt
a
g
es s
u
ch
as
com
p
l
e
xi
t
y
i
n
t
h
e
in
terconn
ection
n
e
t
w
ork
,
less flex
ib
ility etc an
d
were ov
erco
m
e
in
th
e d
a
ta p
a
th
p
r
op
o
s
ed
b
y
Puroh
it et al
[1]
.
It can perform N-bit add
ition, m
u
ltiplicat
i
o
n, subtraction and accum
u
lation operations.The
propose
d
data
p
a
th
is reco
nfi
g
urab
le and
p
e
rfo
r
m
s
all th
ese op
era
tion
s
b
a
sed
on
th
e con
t
ro
l si
g
n
a
ls of t
h
e m
u
ltip
lex
e
rs.
3.
PROP
OSE
D
AR
CHITE
C
T
URE
Man
y
o
f
t
h
e
ap
p
lication
s
in
vo
lv
e
rep
e
titi
v
e
arith
m
e
tic
o
p
e
ration
s
and
th
erefo
r
e t
h
e d
e
sign
of
arith
m
e
t
i
c d
a
ta p
a
th
is im
p
o
r
tan
t
sin
ce it affects th
e
ove
ral
l
perf
orm
a
nce
of t
h
e
sy
st
em
. The p
e
r
f
o
r
m
a
nce of
th
e system
is g
e
n
e
rally d
e
termin
ed
b
y
t
h
e
m
u
l
tip
lier b
l
oc
k si
n
ce i
t
i
s
t
h
e m
o
st
t
i
m
e
consum
i
ng
o
p
era
t
i
on
[3]
.
Hen
c
e th
e sp
eed
and
area
o
f
th
e m
u
ltip
lier m
u
st b
e
op
timi
zed
and
h
e
re th
e m
u
ltip
lier blo
c
k is op
tim
iz
ed
b
y
usi
n
g
t
h
e
c
o
n
c
ept
of di
vi
de and
c
o
n
q
u
er a
p
p
r
oach
[1]
.
A
not
her
m
a
jor c
h
al
l
e
nge
i
s
t
o
gua
ra
nt
ee fa
ul
t
fre
e
o
p
e
ration
o
f
the circu
it sin
ce it affects th
e reliab
ility
o
f
th
e syste
m
. Th
e b
a
sic id
ea o
f
an
FIR filter is si
m
p
le
:
th
e curren
t
o
u
t
p
u
t
is
ob
tain
ed b
y
m
u
ltip
lyin
g
th
e curren
t
i
n
pu
t v
a
lu
e b
y
a
con
s
tan
t
, and
add
i
ng
th
at resu
lt
to
th
e prev
i
o
us in
pu
t
v
a
lu
e times a co
n
s
tant, and
add
i
ng
th
at resu
lt to
th
e
n
e
x
t
earlier in
pu
t v
a
l
u
e times a
co
nstan
t
,
and
so
o
n
.
C
o
n
s
i
d
er a
3-tap
FIR filter. It
h
a
s
3
filter co
efficien
ts an
d can b
e
d
e
scrib
e
d
as
fo
llo
ws:
1
2
(
1
)
‘
’,‘
’ an
d ‘
’ are th
e filter co
efficien
ts; ‘
’
and ‘
’ are t
h
e i
n
p
u
t
an
d
out
put
s
i
gnal
s
, a
n
d ‘
’ i
s
th
e presen
t ti
me step
. Equ
a
tion
(1
) can
b
e
imp
l
em
en
ted
b
y
u
s
ing
reg
i
sters,
m
u
ltip
liers and
add
e
rs. B
o
th
serial
an
d
p
i
p
e
lin
ed FIR filters are m
o
d
e
lled
usin
g
t
h
e
d
a
ta
p
a
th
sho
w
n
in
Figu
re 2.
Mu
ltip
lier b
l
ock
s
are
i
m
p
l
e
m
en
ted
by u
s
ing
t
h
e con
cep
t
of
d
i
v
i
de and
con
q
u
e
r app
r
o
a
ch
.
Add
itio
n pro
c
ess
is also
im
p
l
e
m
en
ted
si
m
ilarl
y. W
a
llace
tree
m
u
ltiplier
[9]
is use
d
for bot
h processesses.
3.
1.
Seri
al
an
d Pi
pel
i
n
ed F
I
R Fi
l
t
ers
Serial and
p
i
p
e
lin
ed
3
-
tap
FIR filters
[1
5
]
are sh
own
in Fi
g
u
re
1
.
It co
nsists o
f
reg
i
sters, m
u
ltip
liers
and a
dde
rs. R
e
gisters
‘rt
0’,
‘rt1’ a
n
d
‘rt
2’ are
nee
d
e
d
for each tap to hold
,
1
and
2
respectively. For se
rial filter,
the data
m
oves to the ri
ght
on each cloc
k cy
cl
e, so that the
register
‘rt
0’
hol
ds
th
e curren
t
inpu
t sam
p
le, ‘rt1’ ho
ld
s t
h
e prev
iou
s
inpu
t sam
p
le an
d
‘rt
2
’
h
o
l
d
s
th
e sam
p
le b
e
fo
re the prev
iou
s
one
[1
5
]
.
Th
e th
rou
ghp
u
t
o
f
t
h
e serial filter
can
b
e
im
p
r
oved
b
y
u
s
ing
p
i
p
e
lin
ing
.
Pip
e
li
n
i
ng
m
ean
s to
b
r
eak
a
larg
e task
do
wn
in
to
a
sequ
en
ce of
stage
s
s
u
ch t
h
at data
m
oves throug
h these stages a
nd eac
h sta
g
e
produc
e
o
u
t
p
u
t
u
s
ed
b
y
th
e n
e
x
t
stag
e. All th
e stag
es
o
p
e
rate co
n
c
u
r
ren
tly resu
ltin
g in
b
e
tter
p
e
rform
a
n
ce. It in
vo
lves
th
e ad
d
ition
of reg
i
sters between
th
e stag
es
an
d
th
ese re
g
i
sters are kn
own as p
i
p
e
lin
e reg
i
sters.
Here all th
e
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I
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S
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:
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8-8
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8
FPGA S
y
n
t
h
e
si
s o
f
Recon
figu
r
a
b
l
e
Modu
les fo
r FIR
Filter
(Sar
a
n
y
a
R)
65
in
pu
ts are av
ai
lab
l
e at th
e mu
ltip
lier inp
u
t
at th
e sam
e
cl
o
c
k.
All th
e mu
ltip
licatio
n
op
eration
s
are
do
n
e
i
n
p
a
rallel and
the in
d
i
v
i
du
al resu
lts are stored in
p
i
pelin
e reg
i
sters.
We al
so
n
eed
a m
u
ltip
lier for each
tap
to
m
u
l
tip
ly th
e tap
’
s ‘
’ val
u
e by
t
h
e
co
nst
a
nt
‘
’ val
u
e.
T
h
e out
put
‘
’ is the
sum
of each ta
p’s product. T
h
e
2-
tap
FIR filter
h
a
s
2
co
efficien
ts an
d th
e stru
cture is
similar to
Fi
g
u
re
1
b
u
t
h
a
s on
l
y
two
reg
i
sters and
m
u
l
tip
liers and a sing
le ad
d
e
r.
Fig
u
re
1
.
(a) Serial 3
-
tap
f
ilter (b) Pi
p
e
lin
ed
3
-
tap
filter
3.2.
Data P
a
th Archi
t
ecture
The arc
h
i
t
ect
ure of t
h
e dat
a
pat
h
i
s
sho
w
n i
n
Fi
g
u
r
e
2. The dat
a
pat
h
can pe
rf
orm
N-bi
t
m
u
l
tip
licatio
n
an
d add
itio
n op
eration
s
. An
o
n
lin
e log
i
c fau
lt d
e
tectio
n mech
an
ism
[2
] is in
corpor
ated i
n
to t
h
e
dat
a
pat
h
. T
h
e
dat
a
pat
h
s co
nsi
s
t
o
f
t
w
o N
x N/
2
W
a
llace tree m
u
lt
ip
li
ers, co
m
p
ressors, ad
d
e
rs an
d carry
co
m
p
letio
n
lo
g
i
cs. It also
co
n
t
ains an
eq
uality co
m
p
arato
r
, equ
a
lity d
e
tecto
r
s,
AND
g
a
tes and
m
u
lt
ip
lex
e
r
whi
c
h a
r
e u
s
e
d
f
o
r fa
ul
t
det
ect
i
on.
A t
e
c
h
ni
q
u
e
kn
o
w
n
a
s
di
vi
de a
n
d
c
o
n
q
u
er
ap
pr
oa
ch i
s
use
d
.
It
i
n
v
o
l
v
e
s
b
r
eak
i
ng
up
of th
e
m
u
ltip
lier
in
to
two
th
at is, b
r
eak
i
ng
up o
f
th
e larg
e
m
u
l
tip
licatio
n
in
to
two
sm
all
e
r on
es
an
d add
s
up
t
h
e p
a
rtial p
r
od
ucts g
e
n
e
rated
t
o
o
b
t
ain th
e final resu
lt.
Fi
gu
re
2.
Ge
ne
ral
i
zed a
r
chi
t
e
c
t
ure
of
t
h
e
dat
a
pat
h
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
089
-48
64
IJR
E
S V
o
l
.
4, No
. 2,
J
u
l
y
20
1
5
:
6
3
– 70
66
C
onsi
d
er t
w
o
N-
bi
t
num
bers
‘A’ a
nd ‘B
’.
The n
u
m
b
er ‘
A
’ i
s
eq
ual
l
y
di
vi
de
d i
n
t
o
t
w
o
num
bers
n
a
m
e
l
y
A1 [N-1
:
N/2
]
and
A2 [N/2-1
:
0
].
Two
m
u
ltip
lic
atio
n
op
eration
s
are
p
e
rfo
r
m
e
d
sim
u
ltan
e
ou
sly b
y
using t
w
o
W
a
ll
ace tree m
u
ltipliers and t
h
e
re
sult is the
n
c
o
m
p
ressed
using
3:2 com
p
ressors. The i
n
termediate
p
r
od
u
c
ts are then
ad
d
e
d
to obtain
th
e fi
n
a
l resu
lt. Fo
r m
u
ltip
licatio
n
pro
c
ess, th
e t
w
o
m
u
ltip
liers p
e
rform
B
[N
-1:
0
]
x
A
1
[N
-1:
N/
2]
a
n
d B
[N
-1:
0
]
x
A
2
[
N
/
2
-
1
:
0
]
.
The
i
n
t
e
rm
edi
a
t
e
pr
od
uct
s
are a
dde
d
usi
n
g
3:
2
co
m
p
ressors an
d
‘0’ is th
e th
ird
inpu
t to
th
e co
m
p
re
sso
r. Th
e inp
u
t
to
ad
d
e
r1
is ‘0
’. Th
e ‘N/
2
’ least
sig
n
i
fican
t
b
its o
f
B [N-1
:0
]
x
A2
[N/
2
-1
:0
]
fo
rm
s th
e LSB b
its o
f
th
e fin
a
l resu
lt. Th
e ‘N’ m
o
st sig
n
i
fican
t
b
its o
f
B [N
-1
:0
] x
A2
[N
/2
-1:0
] ar
e
ad
d
e
d
with
th
e ‘N’ LSB b
its o
f
B [N
-1
:0
] x
A1
[N-1
:N/
2
] to
o
b
tain
th
e
‘N’ in
term
ed
ia
te b
its of th
e fi
n
a
l resu
lt and
t
h
e ‘N/
2
’ MSB
b
its of B
[N-1
:
0
] x
A1
[N-1
:
N
/2
] fo
rm
s th
e MSB
o
f
th
e fi
n
a
l resu
lt. Fo
r ad
d
ition
op
eration
,
B [N-1
:
0
] g
i
v
e
n
to
th
e left
m
u
lti
p
lier and
A2
[N/2-1
:
0
] g
i
v
e
n to
th
e
righ
t
m
u
ltip
lie
r is ‘1’. Th
e
m
u
l
tip
lier o
n
th
e left and
righ
t p
e
rfo
rm
s A1
[N-1
:N/
2
] x 1
and
B [N-1:0
] x
1
respectively. T
h
e output
of the com
p
ressor i
s
added al
o
n
g
with
A2
[N/
2
-1
:0
] to
o
b
t
ain
t
h
e fi
n
a
l co
m
p
utatio
n
A+B.
In the
data pa
th two N
x N/2
m
u
ltipliers are use
d
. By expl
oiting this
f
eature of Dual Modular
Red
und
an
cy (DMR), an
on
lin
e fau
lt d
e
tectio
n
m
ech
an
ism
[2
] is in
tro
d
u
c
ed
in
to
t
h
e d
a
ta
p
a
th
.
DMR u
s
es t
w
o
eq
u
i
v
a
len
t
fu
nctio
n
a
l
u
n
its an
d pro
v
i
d
e
s
fau
lt d
e
tection
wh
en th
e un
its t
h
at sh
ou
ld
g
i
ve th
e
sam
e
resu
lts g
i
v
e
di
ffe
re
nt
res
u
l
t
s
. I
f
t
h
e
ope
ra
nds
A
1
[
N
-
1
:
N/
2]
a
n
d
A
2
[N/2-1:
0
] are i
d
entical then
a fault
ca
n be de
tected.
In
itially b
y
u
s
in
g
an
eq
u
a
lity co
m
p
arato
r
t
h
at co
n
s
ists
o
f
an
array of XNOR g
a
tes it is v
e
rified
th
at wh
eth
e
r
A1
[N-1
: N/
2
]
an
d
A2
[N/2-1
:0
] are id
en
ti
cal o
r
n
o
t
. Th
e o
u
t
pu
t o
f
th
e
eq
u
a
lity co
m
p
arato
r
along
with
th
e
out
put
of ca
rry
com
p
l
e
t
i
on l
o
gi
c i
s
gi
ve
n as
t
h
e i
n
p
u
t
s
t
o
a
n
A
N
D
gat
e
.
T
h
e o
u
t
p
ut
o
f
t
h
e AN
D
gat
e
i
s
gi
ve
n
to the ena
b
le pin of a tri state buffe
r. T
h
e output of th
e two W
a
llace tree
m
u
ltipliers is
given as the inputs of
th
e tri state
bu
ffers. Th
e
ou
tpu
t
s
o
f
th
e t
r
i st
ate bu
ffers are
th
en g
i
v
e
n to an
equ
a
lity d
e
tecto
r
t
h
at co
n
t
ai
n
s
an
array of
XNOR g
a
tes. Th
e ou
tpu
t
of th
e equ
a
lity d
e
tect
o
r
s are ANDed
t
o
g
e
t
h
er and
it is g
i
v
e
n
to
th
e
en
ab
le
p
i
n
of th
e m
u
ltip
lex
e
r.
If
bo
th
t
h
e i
n
pu
ts of th
e e
q
u
a
li
ty co
m
p
arato
r
are
sam
e
an
d
th
e
o
upu
t of carry
co
m
p
letio
n
log
i
cs is ‘1
’, t
h
e two
tri state
b
u
ffers are
enabled.
The
n
the out
puts
of the tri state buffers are
available at the inputs of the equality
detector. The out
put of the equality de
tector is given as the input of a
n
AND
g
a
te and if its
o
u
t
p
u
t
is ‘0
’, th
e circu
it is fau
lt free
o
t
h
e
rwise it is
fau
lty.
If t
h
e i
n
pu
ts
o
f
th
e eq
u
a
lity
com
p
arat
or a
r
e
di
ffe
re
nt
t
h
en
i
t
s
oup
ut
i
s
‘
0
’
and e
v
e
n
i
f
t
h
e
out
put
of t
h
e c
a
rry
com
p
l
e
t
i
on l
o
gi
c i
s
‘1
’, t
h
e t
r
i
state b
u
f
fers get d
i
sab
l
ed
and
no
fau
lt d
e
tectio
n
m
ech
an
ism is p
e
rfo
r
m
e
d
.
Th
is is an
on
lin
e fau
lt d
e
t
ectio
n
mechanism
since it donot re
qu
ire t
h
e system to s
h
ut down to
detect the
fault
[2]
.
Carry co
m
p
leti
o
n
d
e
tectio
n
log
i
c is u
s
ed
to
reco
gn
ize th
e co
m
p
letio
n
o
f
m
u
l
tip
licatio
n
o
p
e
ration
.
It
is n
ecessary si
n
ce th
e fau
lt detectio
n
is p
e
rfo
rm
ed
af
ter the
m
u
ltip
licat
io
n
op
eration
.
Fig
u
re 3(a) shows th
e
l
ogi
c ci
rcui
t
of
carry
com
p
l
e
ti
on det
ect
i
o
n l
ogi
c. It
co
nsi
s
t
s
of C
a
rry
Tra
n
sm
i
ssi
on (C
T) uni
t
s
, F
u
l
l
Adde
r
s
(FA
s
),
OR
gat
e
s an
d a car
ry
com
p
l
e
t
i
on gat
e
whi
c
h i
s
th
e
n
-
i
n
pu
t AND
g
a
te.
Here, th
e in
pu
ts (A0
to
An-1
and B
0
t
o
B
n
-
1
) a
r
e gi
ven t
o
bot
h t
h
e F
A
s
and t
h
e C
T
u
n
i
t
s. The s
u
m
out
put
s are
o
b
t
a
i
n
ed
fr
om
t
h
e FAs an
d
the carry outs
and their c
o
m
p
lim
e
nts
are ob
tain
ed
fro
m
th
e CT un
its. Th
e ou
tpu
t
of each CT un
it is g
i
ven
to
an OR gate. T
h
e outputs of
all the OR gates are then
gi
v
e
n t
o
a carry
com
p
l
e
t
i
on gat
e
. The val
u
e of
carry
com
p
letion signal signi
fies the com
p
le
tio
n o
f
th
e
op
erati
o
n. If th
e carry co
m
p
let
i
o
n
sig
n
a
l is ‘1
’ t
h
en
it
in
d
i
cates th
at th
e fin
a
l carry is o
b
t
ain
e
d
and th
e
m
u
ltip
lica
tio
n
op
eration
is co
m
p
lete. Fi
g
u
re 3(b) shows th
e
CT un
it and
is
u
s
ed
to g
e
n
e
rat
e
th
e carry si
g
n
al an
d its co
m
p
li
m
e
n
t
.
Fi
gu
re
3.
(a
) C
a
rry
c
o
m
p
l
e
t
i
on l
o
gi
c
(b
) C
a
r
r
y
Tra
n
sm
i
ssi
on
uni
t
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
RES I
S
SN
:
208
8-8
7
0
8
FPGA S
y
n
t
h
e
si
s o
f
Recon
figu
r
a
b
l
e
Modu
les fo
r FIR
Filter
(Sar
a
n
y
a
R)
67
In ord
e
r to
d
e
t
ect fau
lt, fau
lt
n
eeds to
b
e
in
t
r
odu
ced in
to the circu
it. Th
is
can
b
e
do
n
e
b
y
conv
erting
th
e Nativ
e Circu
it Descrip
tion
(NC
D
) file (n
on
read
ab
le) o
f
th
e fau
lt free circu
it wh
ich is o
b
t
ain
e
d
aft
e
r the
place a
n
d rout
e process int
o
Xilinx
De
si
gn Langua
ge (XDL) by
using
a t
ool
–XDL and this
rea
d
a
b
le XDL
file h
a
s to
b
e
ed
ited
to
in
trod
u
ce
fau
lt. Th
i
s
file is
th
en
co
nv
erted
b
a
ck
to
NCD and
th
e NCD
file b
ack
to
Verilog
n
e
tlist file and
is sim
u
lated
b
y
ap
p
l
yi
n
g
th
e test
v
ect
o
r
s u
s
i
n
g test ben
c
h and
is v
e
rified
[2
].
By u
s
in
g
th
e ab
ov
e d
a
ta path, 2
-
tap
and
3
-
t
a
p
serial and
pip
e
lin
ed
FIR filters are
m
o
d
e
lled
.
Th
ese
are th
e recon
f
ig
urab
le m
o
d
u
les fo
r m
a
k
i
ng
th
e FIR
filter p
a
rtially reco
nfigu
r
ab
le. Fig
u
re
4
shows
th
e
reconfi
g
ura
b
le
m
odules for the FIR
f
ilter. T
h
ese m
o
dules
are the
n
sy
nthe
si
zed se
paratel
y
to obatin t
h
e
netlist
an
d im
p
l
e
m
en
t
e
d
o
n
v
a
riou
s
Virtex FPGAs
to
d
e
term
in
e th
e b
e
tter
d
e
v
i
ce
u
tilizatio
n
.
Figure
4. Reconfi
g
urable m
o
dules for FIR fil
t
er
4.
RESULT A
N
D
AN
ALY
S
IS
Ino
r
d
e
r to
ev
alu
a
te th
e feasib
ility o
f
b
o
t
h
serial
an
d
p
i
pelin
ed
FIR filt
ers, it is d
e
sig
n
e
d
using
Verilog
HDL
an
d
sy
n
t
h
e
sized
u
s
i
n
g
Xilinx
ISE 14
.2
. Th
e inp
u
t
an
d
co
efficien
ts of b
o
t
h
th
e
filters are
assu
m
e
d
to
b
e
8
-
b
it.
W
e
imp
l
em
en
ted
8
-
b
it (N=8) m
u
ltip
licatio
n
and
16
-b
it (N=16
)
ad
d
ition
fo
r
d
e
sig
n
i
ng
th
e filter. A
h
a
l
f
ad
d
e
r is also
u
s
ed
to add
t
h
e fin
a
l t
w
o b
its.
First, th
e fun
c
tio
n
a
l sim
u
latio
n
o
f
bo
th serial an
d
p
i
p
e
lin
ed
FIR filter
is d
o
n
e
b
y
u
s
ing
ISim
with
exha
ustive test
bench. Successful sim
u
lation is then
fo
ll
owed by t
h
e synt
hesis process
with
various
Xilinx
FPGA’s to ob
t
a
in
th
e m
a
x
i
mu
m
co
m
b
in
ation
a
l p
a
t
h
d
e
lay
an
d d
e
v
i
ce
u
tilizatio
n
fo
r FPGA im
p
l
e
m
en
tatio
n
.
Fig
u
re
5
an
d Fig
u
re 6 shows
th
e sim
u
latio
n
wav
e
fo
rm
fo
r
serial and
p
i
p
e
lin
ed
FIR filter b
e
fore an
d
after fau
lt in
jectio
n
.
Here
‘k
’ is th
e in
pu
t,
‘c0
’
, ‘c1
’
a
n
d ‘c2’ a
r
e the c
o
e
fficients a
nd
‘y’ is the output. ‘i1’,
‘i2
’
and
‘i3’ are th
e
ou
tpu
t
o
f
equ
a
lity d
e
tecto
r
s. ‘f1’,
‘f2
’
and
‘f3
’
is th
e
ou
tpu
t
o
f
fau
lt
d
e
tection
circu
it.
Wh
en
th
e
v
a
lue o
f
eith
er of c0
[7
:4
] and
c0
[3
:
0
], c1
[
7
:4
] an
d
c1
[
3
:0
],
c2
[7
:4
] and
c2
[
3
:0
] ar
e sam
e
,
th
e
co
rresp
ond
ing
eq
u
a
lity d
e
tecto
r
b
e
co
m
e
s act
iv
e an
d
b
e
fo
re
fau
lt in
j
ection
th
e o
u
t
p
u
t
of fau
lt d
e
tectio
n
circu
it
is ‘0
’.
Wh
en
t
h
e v
a
lu
es are
d
i
fferen
t
, th
en
th
e eq
u
a
lity d
e
tecto
r
b
e
co
m
e
s
in
activ
e an
d
fau
lt d
e
tectio
n
is n
o
t
per
f
o
r
m
e
d as sho
w
n i
n
Fi
gu
r
e
5.
Aft
e
r
fa
ul
t
i
n
ject
i
o
n, t
h
e
out
put
of t
h
e c
o
r
r
es
po
n
d
i
n
g f
a
ul
t
det
ect
i
on
ci
rcui
t
b
eco
m
e
s ‘1’ as sho
w
n
i
n
Fi
g
u
re
6
.
Tab
l
e
1
an
d
Tab
l
e
2 sho
w
t
h
e com
p
ariso
n
o
f
dev
i
ce u
tilizatio
n
an
d
co
m
b
in
atio
n
a
l p
a
th
d
e
lay o
f
2
-
tap
an
d 3
-
tap
serial
and
p
i
p
e
lin
ed
FIR filter
on
v
a
riou
s FPGA d
e
v
i
ces.
Th
e
p
r
op
o
s
ed
d
a
ta
p
a
th
u
tilizes less n
u
m
b
e
r of slices, LUTs
and
IOBs
wh
en
it is
i
m
p
l
e
m
e
t
e
d
on
Virtex-5
. Bu
t
wh
en
it is im
p
l
e
m
en
ted
on
Virtex
-4
and
Virtex
-6
, t
h
e
d
e
v
i
ce u
tilizatio
n
i
s
m
o
re. So
it i
s
clear t
h
at Vi
rtex
-5
h
a
s b
e
tter
d
e
v
i
ce
u
tilizatio
n
.
Th
e d
e
sign
s hav
e
d
i
fferen
t
delays wh
en
imp
l
em
en
ted
o
n
v
a
ri
o
u
s
d
e
v
i
ces. It is
clear th
at th
e
p
i
p
e
lin
ed
FIR filter h
a
s less d
e
lay as
com
p
ared
to
serial FIR filter. Fig
u
re 7
shows th
e
co
m
p
ariso
n
of
2
-
tap
an
d 3-tap serial and
p
i
p
e
lin
ed
FIR
filters on
v
a
ri
o
u
s FPGA
d
e
v
i
ces.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
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:
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64
IJR
E
S V
o
l
.
4, No
. 2,
J
u
l
y
20
1
5
:
6
3
– 70
68
Fig
u
re
5
.
Sim
u
latio
n
wav
e
form
s fo
r
FIR filter
b
e
fo
re fau
lt
in
j
ection
Fig
u
re
6
.
Sim
u
latio
n
wav
e
form
s fo
r FIR filter after fau
lt inj
ectio
n
Tab
l
e
1
.
C
o
m
p
arison
o
f
d
e
v
i
ce u
tilizatio
n
and
co
m
b
in
a
tio
nal p
a
th
d
e
lay
of
2
-
tap serial an
d p
i
p
e
lin
ed
FIR
filter
Device
Architecture
No.
of occupied
Slices (%
)
No
. o
f
LU
Ts
(%)
No
. o
f
IOBs
(%)
M
a
x
i
mu
m
co
m
b
inational
path delay
(
n
s)
Virtex
-4
(XC4VFX12)
Serial F
I
R filter
4
3
18
22.924
Pipelined FIR filte
r 4
3
18
20.284
Virtex
-5
(
X
C5VL
X110T
)
Serial F
I
R filter
1
1
7
16.841
Pipelined FIR filter
1
1
7
14.268
Virtex
-6
(XC6VCX75T)
Serial F
I
R filter
1
1
18
12.024
Pipelined FIR filter
1
1
18
9.898
Tab
l
e
2
.
C
o
m
p
arison
o
f
d
e
v
i
ce u
tilizatio
n
and
co
m
b
in
a
tio
nal p
a
th
d
e
lay
of
3
-
tap serial an
d p
i
p
e
lin
ed
FIR
filter
Device
Architecture
No.
of occupied
Slices (%
)
No
. o
f
LU
Ts
(%)
No
. o
f
IOBs
(%)
M
a
x
i
mu
m
co
m
b
inational
path delay
(
n
s)
Virtex
-4
(XC4VFX12)
Serial F
I
R filter
6
6
22
24.648
Pipelined FIR filte
r 6
6
22
22.012
Virtex
-5
(
X
C5VL
X110T
)
Serial F
I
R filter
1
1
8
18.696
Pipelined FIR filter
1
1
8
15.928
Virtex
-6
(XC6VCX75T)
Serial F
I
R filter
1
1
22
17.411
Pipelined FIR filte
r 1
1
22
15.456
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
RES I
S
SN
:
208
8-8
7
0
8
FPGA S
y
n
t
h
e
si
s o
f
Recon
figu
r
a
b
l
e
Modu
les fo
r FIR
Filter
(Sar
a
n
y
a
R)
69
5.
CO
NCL
USI
O
N
AN
D F
U
T
U
RE W
O
R
K
In t
h
i
s
pa
pe
r,
we
prese
n
t
e
d t
h
e
desi
g
n
a
nd
sy
nt
hesi
s
of
re
con
f
i
g
ura
b
l
e
m
o
d
u
l
e
s
(2
-t
ap a
n
d
3
-
t
a
p
)
f
o
r
d
e
v
e
l
o
p
i
n
g
a
p
a
rtially reconfigu
r
ab
le
FIR
filter. Th
e
d
a
t
a
p
a
th was
b
a
sed
on
th
e
con
cep
t of d
i
v
i
de
and
co
nqu
er ap
proach
. By u
s
ing th
is co
n
c
ep
t, th
e n
u
m
b
e
r
o
f
g
a
tes was
redu
ced
and
th
u
s
t
h
e FIR
filter
i
m
p
l
e
m
en
ted
u
s
ing
th
is
d
a
t
a
p
a
th
was area efficien
t.
An
on
lin
e fau
lt d
e
tectio
n
tech
n
i
qu
e
was also
in
corpo
r
ated
in
to
th
e
d
a
ta path
and
a fau
l
t
in
sertion
techn
i
qu
e was
d
e
scrib
e
d
to
in
sert th
e fau
lts so
th
at b
y
using t
h
e test
vectors the fa
ults can be
de
tected. T
h
e imp
l
em
en
tatio
n
resu
lt shows t
h
at th
e recon
f
i
g
u
r
ab
le
m
odules ha
ve l
o
we
r
de
vice ut
iliza
tion when
im
plem
ented on
Virtex
-5 (XC
5
VLX110T
-
1F
F1136T
) F
P
GA.
Our
fu
t
u
re effo
rt is to
d
e
si
g
n
a recon
f
i
g
urab
le FIR
filter t
h
at aim
s
to
attain
all th
e
obj
ectiv
es on
t
h
e
FPGA,
wh
ich
are set b
y
Dyna
m
i
c Partial
R
eco
nfigu
r
ati
o
n (DPR
) b
y
u
s
i
n
g
a
2
-
tap
and two
3-tap
filters as
reco
nfi
g
u
r
a
b
l
e
m
odul
es i
n
Pl
anA
h
ea
d
1
4
.
2
on
Vi
rt
ex
-5
(
X
C
5
VL
X1
1
0
T
-
1F
F1
1
3
6
T
)
F
P
G
A
whi
c
h s
u
pp
o
r
t
s
Partial Recon
f
i
g
uration
.
Parti
a
l Reco
nfigu
r
atio
n
is t
h
e
ab
ility to
reconfigu
r
e select
ed
areas of an
FPGA an
y
ti
m
e
after its in
itial co
n
f
iguratio
n
[4
].
Fig
u
re
7
.
Co
mp
ariso
n
of seri
al an
d p
i
p
e
lin
ed
FIR filters on v
a
riou
s
d
e
v
i
ces (a)
2
-
tap (b
)
3
-
tap
ACKNOWLE
DGE
M
ENT
The a
u
thor woul
d like t
o
acknowledge
the supp
o
r
t
o
f
t
h
e De
part
m
e
nt
of El
ect
ro
ni
cs
an
d
Co
mm
u
n
i
catio
n
,
Sain
tg
its C
o
lleg
e
of En
g
i
n
e
ering
,
Ko
ttayam
fo
r techn
i
cal assistan
ce i
n
si
m
u
latio
n
s
.
REFERE
NC
ES
[1]
Sohan S. Purohit, Sai Rahu
l Chalamal
as
et
ti,
M
a
rt
i
n
M
a
rgal
a,
W
i
m
A. Vand
erbauw
hede, “Design and Evaluation of
High-P
e
rform
ance P
r
oces
s
i
ng E
l
em
ents
for Rec
onfigurabl
e
S
y
s
t
em
s
”
,
IEEE T
r
a
n
sactions on Ve
ry L
a
rge Scale
Integration
(
V
LSI)
Systems,
Vol.
21, No. 10, Octo
ber 2013.
[2]
Pradeep C, Rad
h
akrishnan R, Saran
y
a R, Philip
Sam
u
el., “
S
y
n
t
h
esis of Data Path Archite
cture
with Online Fault
Detec
tion M
e
ch
anis
m
for Re
con
f
igurabl
e
S
y
s
t
em
s
”
,
Aust.
J. Basic
&
Appl. Sci
., 8(
10): 239-245, 20
14.
[3]
Rong Lin, “Reconfigurable Parallel In
n
e
r Product Processor Architectur
es”,
I
E
EE Transaction
s
on Very Larg
e
Scale Integratio
n (
V
LSI)
Systems
, Vol. 9, No. 2
,
April 2001.
[4]
Wang Lie, Wu Feng-
y
a
n
,
“
Dynamic partial reconfiguration in
FPGAs
”, 2009
Third Intern
atio
nal S
y
mposium on
Intelligen
t Infor
m
ation
Technolo
g
y
Application
.
[5]
Sotiris X
y
dis, G
e
orge Economakos, Kiam
al Pekmestzi, “Flexibili
ty
n
i
ming into
Arithmetic Data-
p
aths Exploiting
a
Regular
Intercon
nection Scheme”,
IEEE
2007.
[6]
S
.
Chalam
alas
e
t
t
i
, W
.
Vanderbau
whede, S
.
P
u
rohit, and M
.
M
a
rg
ala
,
“
A low cost reconfigurable soft processor for
multimedia appl
ications: Design
synthesis and
programming model
”, in Proc.
Int. Conf
. Field
Program. Logic
Devices, 2009, p
p
. 534–538
.
[7]
S
.
Chal
am
alas
et
t
i
, S
.
P
u
rohit,
M
.
M
a
rgala
,
W
.
V
a
nderbauwhede
,
“
MORA-an architecture and prog
ramming model
for a resource effic
ient
coarse
grained reconfigu
r
able processor
”,
in Proc.
4th
NASA/ESA
Co
nf.
Adapt.
Hardw.
S
y
st., San
Francisco, CA, 2009, p
p
. 389-396
.
[8]
S
.
P
u
rohit, S
.
Chalam
al
as
ett
i
,
M
.
M
a
rgala
,
P
.
Cors
onello, "
Power-Efficient
High Throughp
ut Recon
figurab
le
Datapath Design for Portable
Multimedia D
evi
ces
", in Proceedings of Internatio
nal Confer
ence
on Reconfigur
ab
le
Computing and
FPGAs, pp.
217-
222, December
2008.
[9]
C.S. Wallace, “
A
suggestion for
a fast m
u
ltiplier
”
,
IEEE Trans.
Electron. Comput
, vol. 13, no
. 1, pp. 14–17, Feb
.
1964.
[10]
Yunan Xiang,
R
y
an Pettibon
, Martin Margala, “
A Versatile
Module for Ad
aptable Mul
tim
edia Processors
”,
Circuits
and S
y
s
t
em
s, 2006, ISCAS Proceedings.
IEE
E
In
terna
tio
nal S
y
m
posium
on 21-24 Ma
y
2
006.
[11]
Katherin
e Compton, “Reconfigur
able Computi
ng: A Survey
of S
y
st
ems and Software”,
ACM Com
puting Sur
veys
,
vol.34, no.2
.
pp
.
171-210, June 2
002.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
089
-48
64
IJR
E
S V
o
l
.
4, No
. 2,
J
u
l
y
20
1
5
:
6
3
– 70
70
[12]
Rajamani Doraiswami, Chri
s P. Diduch,
and Jiong Tang,
"A N
e
w Diagnostic
Model fo
r Identif
y
ing Parametr
ic
Faults",
IEEE Transactions on C
ont
rol Systems Technolog
y
, vol.
18, no
. 3
,
May
2
010.pp 533-544
.
[13]
Yeong-Jae Oh et al., “A Reconfigurabl
e
FIR F
ilter Design Using Dy
n
a
m
i
c Part
ial Reco
nfgurat
i
on”,
School of
Information
and Communication Eng.
, Inha Univ., Inch
eon, Korea.
[14]
Kuan-Hung Chen and Tzi-Dar C
h
iueh, “A Low-Po
wer Digit-Based Reconfigu
r
ab
le FIR Filter”,
I
EEE T
r
ansactio
ns
on Circuits
and
Systems—II
: Ex
press Briefs, vol.
53, no. 8, August 2006.
[15]
F. Vahad
,
“Register-Trans
fer
Level (R
TL)
Desig
n
”,
Dig
ital
Desi
gn with
RTL
Design, Verilog
an
d VHDL
,
USA,
2010, ch
.r, sec 5.3.
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