Intern
ati
o
n
a
l
Journ
a
l of
Re
con
f
igur
able
and Embe
dded
Sys
t
ems
(I
JRES)
V
o
l.
3, N
o
. 3
,
N
o
v
e
m
b
er
2
014
, pp
. 11
4
~
11
8
I
S
SN
: 208
9-4
8
6
4
1
14
Jo
urn
a
l
h
o
me
pa
ge
: h
ttp
://iaesjo
u
r
na
l.com/
o
n
lin
e/ind
e
x.ph
p
/
IJRES
Desi
gn of AES Pi
pelined Architecture for Image
Encryption/Decryption Module
Pravin V. Kin
g
e
1
, S.
J. Honale
2
, Prof.
C.
M.
Bob
a
de
3
1
Department of Electronics
and
Telecomm
unication Eng
i
neer
ing, G.H.
R
a
isoni Colleg
e
of
Engi
n
e
ering, Amravati, India
2,3
F
acult
y
of
Ele
c
troni
cs
and
Te
l
ecom
m
unication
Engin
eering
,
G
.
H. R
a
isoni Co
llege of
En
g
i
neering, Amravati, In
dia
Article Info
A
B
STRAC
T
Article histo
r
y:
Received
May 9, 2014
Rev
i
sed
Ju
l 23
,
20
14
Accepted Aug 12, 2014
The relentless growth of Internet a
nd communication technologies has made
the ex
tens
ive u
s
e of im
ages
unavoidab
l
e.
The
s
p
ecifi
c cha
r
ac
teris
t
i
c
s
o
f
image like h
i
gh
transmission rate with
limited b
a
ndwidth, redun
dancy
,
bulk
capacity
and cor
r
elation among
pixels
ma
kes stan
dard algo
rithms not suitab
l
e
for image
encr
yption. In ord
e
r to overc
om
e
the
s
e lim
it
ations fo
r rea
l
t
i
m
e
applications, des
i
gn of new algor
ithms
that r
e
quir
e
less computational power
while pr
es
erving
a s
u
ffic
i
en
t l
e
v
e
l of s
e
curity
has alway
s
been a subject of
inter
e
st. Here A
dvanced
Encr
y
p
tion Standa
rd (A
ES), as the most widely
used
encr
ypt
i
on algo
rithm
in m
a
n
y
s
ecurit
y
appli
cat
ions
. AES
s
t
andard h
a
s
differen
t
key
size variants, wh
ere l
onger b
it
key
s
provid
e
more secure
cipher
e
d text ou
tput.
The
available AES al
gorithm is used for data
and it is
als
o
s
u
itabl
e for
im
age encr
ypt
i
on and decr
ypt
i
on to protec
t the
confident
i
al
image from an u
n
authorized access. Th
is project
proposes a method in which
the imag
e data
is an inpu
t to
Pipe
lin
ed AES
algorithm through
Tex
tio, to
obtain
the en
cr
ypted im
age
and t
h
e encr
yp
ted
im
age is
th
e inpu
t t
o
P
i
pelin
ed
AES Decr
y
p
tio
n
to get the
original
image. This pr
oject proposed to
implement th
e
128,192 & 256
bit Pip
e
lin
ed
AES algorithm
for image
encr
ypt
i
on
and decr
ypt
i
on, als
o
to
com
p
are the l
a
ten
c
y, effi
cien
c
y
,
s
ecur
i
t
y
,
frequency
& t
h
roughput. The proposed wor
k
will be sy
n
t
hesized and
simulated on
FPGA family
of Xili
nk ISE 13.2 and Modelsim tool
respect
ivel
y
in
Ver
y
high sp
ee
d integr
ated
cir
c
uit Hardwar
e
Description
Languag
e
.
Keyword:
AES
C
i
phert
e
x
t
FPGA
Plaintext
VH
DL
Copyright ©
201
4 Institut
e
o
f
Ad
vanced
Engin
eer
ing and S
c
i
e
nce.
All rights re
se
rve
d
.
Co
rresp
ond
i
ng
Autho
r
:
Pra
v
in V.
Ki
ng
e
PG
St
u
d
ent
,
D
e
part
m
e
nt
of
E
l
ect
roni
cs
an
d t
e
l
ecom
m
uni
cati
on
En
gi
nee
r
i
n
g,
G. H.
Raison
i Co
lleg
e
o
f
Engin
eering
,
Am
rav
a
ti
Em
a
il: Kin
g
e
.p.v@g
m
a
il.co
m
1.
INTRODUCTION
In c
o
m
m
uni
cati
on t
h
e
dat
a
se
curi
t
y
i
s
t
h
e bi
g i
ssue i
n
va
ri
o
u
s fi
el
d s
o
us g
ove
r
n
m
e
nt
i
nvi
t
e
d t
h
e ne
w
cry
p
t
o
gra
p
hy
c
once
p
t
,
i
e
AE
S al
go
ri
t
h
m
y
h
e basi
c o
f
AE
S Rijndael are
in a m
a
the
m
a
t
ical conce
p
t called as
Galo
is field
theo
ry. Sim
ilar t
o
th
e way DES fun
c
tion
,
Rijn
d
ael also
u
s
ed
th
e b
a
sic tech
n
i
q
u
e
s of substitu
tio
n
and t
r
a
n
s
p
osi
t
i
on
(i
.e.
perm
ut
at
i
on)
. The
key
si
ze and t
h
e
pl
ai
n t
e
xt
bl
oc
k
si
ze deci
de h
o
w
m
a
ny
rou
n
d
s
need
t
o
be
e
x
ecut
e
d.
O
n
e key
di
f
f
e
r
ent
i
a
t
o
r
bet
w
e
e
n DES
a
n
d
p
r
ovi
des f
o
r
m
o
re
o
p
t
i
m
i
zed
ha
rd
ware
a
n
d
s
o
f
t
ware
im
pl
em
ent
a
t
i
o
n
of
t
h
e al
go
ri
t
h
m
.
AES al
go
r
i
t
h
m
has fi
x
bl
ock
si
ze
12
8
bi
t
and
key
si
ze
12
8,
1
92a
n
d
25
6
bi
t
.
AES al
g
o
ri
t
h
m
im
p
l
em
ent
e
d by
usi
n
g h
a
rd
ware a
nd s
o
ft
ware by
us
i
ng so
ft
wa
re i
t
i
s
easy
t
o
im
ple
m
ented the AE
S algorit
h
m
and it is ea
sy low cost
b
u
t
it is n
o
t
fu
lly secu
red
m
o
st secure
. AE
S algorithm
is applied
data
as well as image eve
r
y im
a
g
e de
fine
i
n
p
i
xel
conc
o
r
n i
n
t
e
nsi
t
y
val
u
e
(
di
gi
t
e
l
num
ber
)
an
d
l
o
cat
i
on a
d
dre
ss i
n
t
h
e
f
o
r
m
of ro
w a
n
d
col
u
m
n
. T
h
e
ap
pl
i
cat
i
ons
of t
h
e i
m
age pr
ocessi
ng
ha
ve
bee
n
co
mm
o
n
l
y fo
un
d
in
th
e Military co
mm
u
n
i
c
a
tio
n
,
Fo
ren
s
ics, Ro
bo
tics, In
tellig
en
t syste
m
s etc. In
th
is p
r
o
j
ect,
th
e Pip
e
li
n
e
d
AES algo
rithm
is p
r
o
p
o
s
ed wh
ich
is an
efficient sc
he
m
e
for
b
o
t
h
h
a
rd
ware
an
d
s
o
ft
ware
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
089
-48
64
I
J
RES Vo
l. 3
,
N
o
. 3
,
No
v
e
m
b
er
201
4
:
1
14
–
11
8
11
5
i
m
p
l
e
m
en
tatio
n
.
AES algorithm
An
enc
r
y
p
t
i
o
n
al
go
ri
t
h
m
conve
rt
s a
pl
ai
n
t
e
xt
m
e
ssage i
n
t
o
ci
p
h
er
t
e
xt
m
e
ssage
whi
c
h ca
n
b
e
recovere
d
only by a
u
thorize
d
receive
r
using a dec
r
yp
tion t
echni
que
. T
h
e
AES-Rijndael
algorithm
[4] is a
n
iterative pri
v
ate key symmetric bloc
k ci
pher. T
h
e inpu
t
and output for the AES
algorithm
each consist of
sequ
en
ces
of
1
2
8
b
its (
b
l
o
ck
leng
th)
.
H
e
n
ce Nb
= Block
leng
th
/32
= 4
.
Th
e Ciph
er
K
e
y fo
r
t
h
e A
E
S
al
go
ri
t
h
m
i
s
a
seq
u
ence
of 1
2
8
, 1
9
2
or
25
6
bi
t
s
(Key
l
e
ngt
h)
. In t
h
i
s
i
m
p
l
em
ent
a
t
i
on t
h
e key
l
e
ngt
h t
o
12
8.
Hence
N
k
=
K
e
y
l
e
ngt
h/
3
2
=
4
in
itia
liza
tio
n
pro
cesses
Ex
pan
d
t
h
e
16
-
b
y
t
e key
t
o
g
e
t
t
h
e act
u
a
l
key
bl
oc
k t
o
be
u
s
e
d
.
Do on
e tim
e in
itializa
tio
n
of t
h
e
1
6
-b
yte p
l
ain
tex
t
b
l
o
c
k(called
as state).
XOR t
h
e state
with the
key
bl
ock.
Apply s-box to each
of the
pla
i
n text
bytes.
R
o
t
a
t
e
ro
w
k
o
f
t
h
e
pl
ai
n
t
e
xt
bl
oc
k(i
.
e
.
st
at
e
)
by
k
by
t
e
s.
Perform
a
m
i
x colum
n
s operat
ion.
XOR t
h
e state
with the
key
bl
ock.
Encry
p
tion Pr
ocess
The Enc
r
y
p
t
i
o
n an
d dec
r
y
p
t
i
on
pr
ocess c
o
nsi
s
t
s
of a n
u
m
ber of di
f
f
er
ent
t
r
ans
f
o
r
m
a
t
i
ons ap
pl
i
e
d
co
nsecu
tiv
ely
o
v
e
r
th
e
d
a
ta blo
c
k
b
its, in
a
f
i
x
e
d
nu
m
b
er
o
f
iter
a
tion
s
, called
r
oun
d
s
. Th
e nu
m
b
er
of
ro
unds
depe
n
d
s
on t
h
e
l
e
ngt
h o
f
t
h
e
key
use
d
fo
r t
h
e e
n
cry
p
t
i
o
n
pr
ocess
.
F
o
r
k
e
y
l
e
ngt
h
o
f
1
28
bi
t
s
, t
h
e
n
u
m
ber of
iteration re
qui
red are
10. (Nr = 10).
As s
h
own in Figure 1, each of th
e first Nr-1 rounds consists
of 4
tr
an
sf
or
m
a
t
i
o
n
s:
Sub
B
ytes(
)
, Sh
if
tRow
s(
), Mix
C
o
l
u
m
n
s
(
)
& A
d
d
R
o
undK
ey(
)
.
Fi
gu
re
1.
AE
S
R
i
jn
dael
Des
c
r
i
be st
ep
There
are
f
o
u
r
di
ffe
re
nt
t
r
a
n
sf
orm
a
t
i
ons are
descri
bed
i
n
de
t
a
i
l
bel
o
w.
a)
S
u
b
Bytes
Transfo
rma
tion
:
It is a non
-lin
ear su
b
s
titu
tion
o
f
b
y
tes th
at
op
erates i
n
d
e
p
e
n
d
e
n
tly on
each
b
y
te o
f
t
h
e State u
s
in
g a
su
bstitu
tio
n tab
l
e (S
b
ox). Th
is S-box
wh
i
c
h
is i
n
v
e
rtib
l
e
is con
s
tru
c
ted
b
y
fi
rst tak
i
n
g
th
e m
u
ltip
l
i
cativ
e
in
v
e
rse in
th
e fin
ite field
GF (2
8
) wi
t
h
i
r
red
u
c
i
b
l
e
pol
y
n
o
m
i
al
m
(
x) = x8 +
x4+ x
3
+ x + 1. T
h
e el
em
ent
{00}
is m
a
p
p
e
d
to itself. Th
en
affine tran
sfo
r
m
a
tio
n
is app
lied
(ov
e
r GF (2
)).
b)
S
h
ift Ro
ws Tran
sfo
r
ma
tio
n:
Cyclical
ly sh
ifts th
e rows
o
f
t
h
e
State ove
r d
i
ffere
nt of
fset
s. Th
e
op
eration is al
m
o
st th
e sa
m
e
in
th
e
decry
p
tion process exce
pt
for
t
h
e
fact
t
h
at
t
h
e shi
f
t
i
n
g
o
ffse
t
s ha
ve
di
ffe
re
nt
val
u
es.
c)
Mix
Co
lumns Tran
sfo
r
ma
tion
:
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
RES I
S
SN
:
208
8-8
7
0
8
Design of
AE
S Pipelined
Arc
hitecture
fo
r
Ima
g
e
En
cryp
ti
o
n
/Decryp
tion
Mo
du
le
(Pravi
n V.
Kinge)
11
6
Th
is tran
sformatio
n
op
erat
es
o
n
th
e State co
lu
m
n
-b
y-co
lum
n
, tr
eating e
ach c
o
lum
n
as
a four-term
polynom
i
al. The c
o
lum
n
s are
conside
r
ed as
polynom
i
als over GF (2
8
) and m
u
ltiplied by
m
odul
o
x4 +
1
with
a fi
xe
d
p
o
l
y
no
m
i
al
a(x) =
{0
3}
x3+
{0
1}
x
2
+ {
02}
x
.
d)
Ad
d R
o
u
n
d
K
e
y Tra
n
sf
orm
a
t
i
on
:
In th
is tran
sformatio
n
,
a R
o
un
d Key is add
e
d
to th
e State
b
y
a sim
p
le b
itwise
XOR
op
eratio
n. Each
R
o
u
n
d
Key
co
nsi
s
t
s
of
N
b
w
o
r
d
s f
r
om
t
h
e key
ex
pans
i
o
n. Those Nb words are eac
h ad
ded i
n
t
o
t
h
e c
o
l
u
m
n
s
o
f
th
e
State. Key Add
itio
n is
th
e sam
e
fo
r the d
e
cryp
tion
p
r
o
cess.
Key Expa
nsion:
Each r
o
u
n
d
ke
y
i
s
a 4-w
o
r
d
(1
2
8
-
b
i
t
)
array
gene
rat
e
d as a pro
d
u
ct
of t
h
e pr
evi
ous
ro
un
d key
,
a
constant that c
h
anges
each round, and a
se
ries of S-
Box l
o
okups
for eac
h 32-bit wo
rd of the
key. T
h
e
Key
sche
dul
e
E
x
pa
nsi
o
n ge
nerat
e
s
a
t
o
t
a
l
of N
b
(N
r
+ 1)
w
o
rds
.
The
decry
p
tion process is
dire
ct i
nverse of the encry
p
tion process.
A
ll th
e t
r
an
sfo
r
m
a
tio
n
s
ap
p
lied
i
n
encry
p
t
i
o
n
p
r
o
cess are
i
n
vers
el
y
appl
i
e
d
t
o
t
h
i
s
pr
ocess.
He
nce t
h
e l
a
st
r
o
un
d
val
u
e
s
of
bot
h t
h
e
dat
a
a
n
d
key
are fi
rst rou
n
d
in
pu
ts for th
e decryp
tion
pr
oc
ess an
d
f
o
l
l
o
w
s
i
n
decrea
si
n
g
o
r
de
r.
2.
RELATED WORK
The sy
st
em
m
a
kes
AES
key
ex
pansi
o
n
w
h
i
c
h i
s
use
d
t
o
gene
rat
e
m
u
l
t
i
pl
e n
o
n
-l
i
n
ea
r
key
s
f
o
r
t
h
e
en
cry
p
tio
n process. Th
is
alg
o
rith
m
is
suitable for im
age en
cryp
tion
in
real ti
me ap
p
li
cations [1]. The
da
ta can
be e
n
cry
p
t
e
d
by
1
2
8
bi
t
ci
p
h
er
key
,
t
h
ro
u
g
h
t
h
e
use
of
ci
phe
r
key
wi
t
h
l
e
ngt
h
12
8,
An
ef
fi
ci
ent
F
P
G
A
im
pl
em
ent
a
t
i
o
n o
f
12
8
bi
t
bl
ock a
n
d 1
2
8
bi
t
key
AES al
go
ri
t
h
m
has been
prese
n
t
e
d
[
2
]
.
They
p
r
ese
n
t
e
d
a l
o
w
cost e
ffective
area ciphe
r
for en
cryp
tion
/
d
ecryp
tion
u
s
ing 12
8
b
it ite
rative a
r
chitecture
,
af
ter foun
d th
at th
e
am
ount
o
f
ha
r
d
ware
res
o
u
r
ces
has
bee
n
opt
i
m
i
ze, One
of
t
h
e i
m
port
a
nt
I
m
pl
em
ent
a
t
i
on of
AE
S al
g
o
r
i
t
h
m
has
been
p
r
ese
n
t
e
d
by
R
a
nees
ha
K, R
e
m
a
Vel
l
ody
an
d R
na
n
d
a
Kum
a
r They
com
p
ared t
w
o
t
y
pe of al
go
ri
t
h
m
for
spee
d of
o
p
era
t
i
on an
d o
b
se
r
v
ed t
h
at
c
ont
r
o
l
l
e
r base ap
pr
o
ach [
4
]
.
M
g
S
u
res
h
,
Nat
a
ra
j.
K.R
,
co
ncl
u
de
d t
h
at
the conce
p
t of Pipeline
d
AE
S arc
h
itecture
can be
practi
cal
l
y
im
pl
em
ent
e
d. It
has
bee
n
o
b
se
rve
d
t
h
at
t
h
e
i
m
p
l
e
m
en
tatio
n
of
AES En
cryp
tio
n
o
n
th
e
FPGA is su
ccessfu
l
and
sev
e
ral d
a
ta in
pu
t.
Th
e
AES al
g
o
rith
m
is
an i
t
e
rat
i
v
e p
r
i
v
at
e key
sy
m
m
e
t
r
i
c
bl
ock c
i
phe
r t
h
at
can
pr
ocess
dat
a
bl
ock
of
1
2
8
-
bi
t
s
t
h
ro
u
gh t
h
e
use o
f
ci
phe
r key
s
wi
t
h
key
l
e
ngt
h
12
8,
1
92 a
nd 2
56
bi
t
s
. An ef
f
i
ci
ent
FPGA i
m
pl
em
ent
a
t
i
on of 1
28 bi
t
bl
o
c
k a
n
d
key
s
12
8,
1
9
2
and
2
5
6
bi
t
s
o
f
AES
–R
i
j
i
n
da
el
al
go
ri
t
h
m
has bee
n
pre
s
ent
e
d
[5]
.
3.
WORKI
N
G
In
itially th
e imag
e is cap
tured
and
t
h
en
co
nv
erted
in
t
o
th
e tex
t
file
b
y
u
s
ing
th
e M
A
TLAB. Th
is
con
v
e
r
t
e
d t
e
xt
fi
l
e
i
s
used as a i
nput
t
h
ro
u
gh A
E
S Text
i
o
an
d gene
rat
e
i
nput
.t
xt
fi
l
e
, whi
c
h i
s
i
nput
t
o
t
h
e
VH
DL c
ode
. The o
b
t
a
i
n
e
d
f
i
l
e
i
s
encry
p
t
e
d by
usi
ng t
h
e
Ad
van
ced E
n
cry
p
t
i
o
n st
an
d
a
rd
whi
c
h i
s
n
a
m
e
d as
Cip
h
e
rtex
t.tx
t t
h
is is ag
ain
con
v
e
rted in
to
i
m
ag
e in
MAT
L
AB. T
h
e
res
u
ltant im
age is Encry
p
ted im
a
g
e. T
h
e
Cip
h
e
rtex
t.tx
t
is n
o
w inp
u
t
t
o
th
e
AES
Decryp
tion
to
ge
t origi
n
al im
a
g
e. T
h
e AES
is a symmetric key
algorithm
,
in
whic
h
both t
h
e send
e
r
a
n
d t
h
e
receive
r
us
e a single
ke
y
for enc
r
yption a
n
d
decry
p
tion.
AES
defi
nes t
h
e
da
t
a
bl
oc
k l
e
n
g
t
h
t
o
1
28/
19
2/
25
6
bi
t
s
. T
h
e
im
age encry
p
t
i
on a
n
d
dec
r
y
p
t
i
on
o
f
sy
st
em
i
s
as
sho
w
n i
n
Fi
gu
r
e
1.
2.
Fi
gu
re
1.
2.
Sy
s
t
em
m
odel
fo
r
Im
age Encry
p
t
i
on/
Dec
r
y
p
t
i
o
n
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
089
-48
64
I
J
RES Vo
l. 3
,
N
o
. 3
,
No
v
e
m
b
er
201
4
:
1
14
–
11
8
11
7
The receive
r decrypts
t
h
e
e
n
crypte
d im
age and
gets the
or
iginal im
age.
At th
e
recei
ver side
im
age
decry
p
t
i
on i
s
carri
ed
out
by
u
s
i
ng A
E
S i
t
s
el
f .The key
use
d
for e
n
cry
p
t
i
o
n
and dec
r
y
p
t
i
o
n m
u
st
be t
h
e
sam
e
.
If t
h
ey are
d
i
fferen
t im
ag
e will b
e
l
o
st.
In
d
ecry
p
tio
n
rev
e
rse
o
f
en
cryp
tio
n is carri
ed
ou
t. Th
e i
n
p
u
t
fo
r
d
ecry
p
tio
n
is th
e cip
h
e
r tex
t
wh
ich
is th
e o
u
t
pu
t o
f
AES en
cry
p
tio
n. Th
i
s
is th
en
d
ecry
p
ted
to
g
e
t th
e o
u
t
pu
t
pl
ai
n t
e
xt
. T
h
e
out
put
pl
ai
n
t
e
xt
i
s
t
h
e
n
c
o
nv
ert
e
d t
o
t
h
e
o
r
i
g
i
n
al
i
m
age by
usi
n
g
M
A
TL
AB
.
4.
E
X
PERI
MEN
T
AL RES
U
L
T
In
itially th
e i
m
ag
e is cap
tu
red
and
th
en
co
nv
erted
in
to
t
h
e tex
t
file b
y
u
s
ing
th
e MATLAB. The
co
nv
erted
tex
t
file is u
s
ed as t
h
e inpu
t to
AES Tex
tio
an
d
gen
e
rate ci
p
h
e
rt
ex
t.tx
t
file
.
Th
is file is t
h
en inp
u
t
t
o
MATLAB
fo
r sh
owing
En
cry
p
ted
im
ag
e.
Ori
g
inal
E
n
cry
p
ted
Decry
p
ted
Im
age
Im
age
Im
age
Fo
r g
e
tting
Orig
in
al im
ag
e d
ecryp
ts th
e encryp
te
d im
ag
e
th
ro
ugh
AES d
e
cryp
tion
Tex
tio
to get
ori
g
i
n
al
i
m
age. At
o
u
t
p
ut
si
de i
m
age decr
y
p
t
i
on i
s
car
ri
ed
out
by
usi
n
g
A
E
S i
t
s
el
f.
The
key
use
d
fo
r
en
cr
y
p
tio
n and d
e
cr
yp
tion
m
u
st b
e
t
h
e sam
e
.
5.
RESULT AND DIS
C
USSI
ON
Th
e
d
e
scri
b
e
d arch
itecture
was im
p
l
e
m
en
ted
in
VHDL u
s
ing
th
e Mo
d
e
l tech
no
log
y
Mod
e
lsim
si
m
u
lator and synthesized,
placed an
d routed usi
ng a target de
vice
of Xilinx (xilinx virte
x
XCV600E-
6B
G
5
6
0
,
S
p
art
a
n
6(
XC
6
S
L
X
25
) a
n
d S
p
a
r
t
a
n
3E
st
art
e
r
ki
t
FPG
A
)
.
Fo
ur
pe
rf
orm
a
nces
m
e
t
r
i
c
s such
a
s
t
h
e
clo
c
k
i
ng
f
r
e
quen
c
y (
M
H
z
)
,
t
h
e thr
oug
hpu
t (
M
bp
s), th
e area (
s
lices)
an
d th
e to
tal po
wer
con
s
u
m
p
tio
n
are
co
m
p
u
t
ed
.
Th
e resu
lts of th
e
FPGA im
p
l
e
m
en
tatio
n
are illu
strated in
fo
llo
wi
n
g
tab
l
e
Fro
m
th
e ab
ove tab
l
e it
is sh
o
w
th
at our d
e
sig
n
is b
e
tter th
an
p
r
ev
iou
s
resu
lt. Th
e m
a
i
n
ai
m
is
to
increase t
h
e t
h
roughput a
n
d
decrease the latency of t
h
e
AES so t
o
i
n
crease
th
e d
a
ta
rate and
secu
rity.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
RES I
S
SN
:
208
8-8
7
0
8
Desi
g
n
of
AE
S Pi
pel
i
n
ed
Arc
h
i
t
ect
ure
fo
r
Ima
g
e
En
cryp
ti
o
n
/Decryp
tion
Mo
du
le
(Pravi
n V.
Kinge)
11
8
6.
CO
NCL
USI
O
N
An
efficien
t su
bp
ip
elin
ed
arch
itectu
r
e
o
f
AES al
g
o
rithm
with
its k
e
y exp
a
n
s
i
o
n un
i
t
is p
r
esen
ted.
The
key
ex
pa
nsi
o
n a
r
chi
t
ect
ure i
s
s
u
i
t
a
bl
e
fo
r
6 s
ubst
a
g
e
s su
b
pi
pel
i
n
ed
AES a
r
chi
t
ect
ure
Agai
nst
pri
o
r
i
m
p
l
e
m
en
tatio
n
s
, th
is arch
itectu
r
e uses com
p
o
s
ite field
arith
m
e
t
i
c in
n
o
r
m
a
l b
a
ses rep
r
esen
tatio
n
t
o
redu
ce
t
h
e re
qui
re
d
ha
rd
ware
. Im
age Encry
p
t
i
on a
n
d Dec
r
y
p
t
i
o
n
u
s
i
ng
AES i
s
de
si
gne
d a
nd i
m
pl
em
ent
e
d t
o
p
r
ot
ect
the confi
d
entia
l im
age data from
an una
uthorized acces
s
.
A Successful i
m
ple
m
enta
tion of
AES al
gori
thm
is
one
o
f
t
h
e
be
st
encry
p
t
i
o
n
and
dec
r
y
p
t
i
o
n st
a
nda
rd
a
v
ai
l
a
bl
e i
n
m
a
rket
.
It
hel
p
s t
o
e
xpl
ore
t
h
e
pat
h
t
o
im
pl
em
ent
such a
n
al
go
ri
t
h
m
usi
ng
VH
D
L
co
de t
h
at
i
s
sy
nt
hesi
ze
d a
n
d
si
m
u
l
a
t
e
d usi
n
g t
h
e
ISE
13
.1
i
n
Xi
l
i
nx Fam
i
ly
Spa
r
t
a
n-
6 (
X
C
6
SL
X2
5
)
, Ve
rt
ex-
6
&
S
p
art
a
n 3E.
The
M
a
x
i
m
u
m
Freq
uen
c
y
achi
e
ve
d fr
om
t
h
e
d
e
sign
is
3
8
5
.
2
3
9
,
181
.2
58
& 224
.7
70
M
H
z an
d
t
h
e thro
ugh
pu
t r
eaches th
e
v
a
lu
e
of
123
2.736
,
580
.0
2 &
7
1
9
.
26
4
M
b
it/sec fo
r
En
cryp
ti
o
n
and
Decryptio
n
.
Th
e resu
lt sh
ows th
at th
e d
e
sig
n
with
th
e p
i
p
e
lin
ing
tech
no
log
y
an
d
sp
ecial d
a
ta tran
s
m
issio
n
m
o
d
e
can optimize the chip a
r
ea ef
fectiv
ely. Mean
wh
ile, th
is d
e
sig
n
redu
ces po
wer con
s
u
m
p
tio
n
to
so
m
e
e
x
ten
t
,
for th
e po
wer co
nsu
m
p
tio
n
is d
i
rectly relate
d
to
th
e
chip a
r
ea. The
r
efore the en
cry
p
t
i
on devi
ce
i
m
pl
em
ent
e
d
in
th
is m
e
th
o
d
can
m
eet so
m
e
practi
cal Appl
ications like i
m
age enc
r
yption.
REFERE
NC
ES
[1]
B. Subraman
y
a
n
,
Vivek. M. Chhabr
ia, T.G. Sankar Babu, “Image Encr
y
p
tion Based On AES
Key
Expansio
n
”
,
Second In
tern
ational Con
f
erence on
Emerging A
pplications of I
n
formation Technology, DO
I
10.1.109/EAIT.2
011.60, IEEE20
11
.
[2]
Hoang Trang,
Nguy
en Van
Loi,
“A
n efficient FPGA imple
m
entation of
th
e advan
ced
En
cr
y
p
tion standar
d
algorithm”,
978-
1-4673-0309-5/1
2
, IEEE 2012.
[3]
A. Amaar, I.
Ashour and M Shiple, “Design and im
plementation
a compact AES Architectur
e for FPGA
Techno
log
y
”,
W
o
rld Acad
emy o
f
Science, Engin
e
ering and Techn
o
logy 59
, 2011
.
[4]
Ranees
ha
K, R
e
m
a
Vellod
y
an
d R nanda Ku
m
a
r, “
H
ardware
effi
cien
c
y
com
p
arion of AES
im
plem
entat
i
on”
,
International C
onference on
C
o
mmunication S
y
stem
and N
e
twork Technolog
y. DOI 10
.1109
/CSNT.2012.187
,
IEEE 2012.
[5]
M
g
S
u
res
h
, Dr.
Nataraj
.
K.R,
“
A
rea Optim
ized and P
i
pelined
F
P
GA Im
plementa
tion of AES
Encr
y
p
t
i
on a
n
d
Decr
yption
”
,
International Journ
a
l of Com
putatio
nal Eng
i
neering
Research
, Vol. 2
Issue. 7
,
nov
20
12
[6]
Nationa
l Institu
t
e
of Standards a
nd Techno
log
y
(
U
.S.), "Data
Enc
r
y
p
t
i
on Standa
rd
(DES),"
FIPS Publica
tion
46-3
,
NIST, 1999. Ava
ilable at
http:
/
/
c
src.nist.
gov/publ
ications/
fips/f
i
ps46-3/fips46-3.pd
f
[7]
J.
Yang, J.
Ding, N.
Li
and Y.
X.
Guo,
“FPGA-ba
se
d design
and implementation
o
f
reduced AES
algorithm”,
IE
EE
Inter. Con
f
. Cha
l
En
vir S
c
i Com
Engin (
C
ESCE)
., Vo
l. 02, Issue 5
-
6, pp
. 67-70
,
Ju
n 2010.
[8]
National institut
e
of standard and technolog
y
,
“Fed
eral inform
ati
on Procesing standaed publicat
io
n 197,
the AES
”,
Nov 2001.
Evaluation Warning : The document was created with Spire.PDF for Python.