Intern
ati
o
n
a
l
Journ
a
l of
Re
con
f
igur
able
and Embe
dded
Sys
t
ems
(I
JRES)
V
o
l. 3,
N
o
.
2
,
Ju
ly 20
14
, pp
. 76
~84
I
S
SN
: 208
9-4
8
6
4
76
Jo
urn
a
l
h
o
me
pa
ge
: h
ttp
://iaesjo
u
r
na
l.com/
o
n
lin
e/ind
e
x.ph
p
/
IJRES
FPGA Based Multichannel Bit
Error Rate Tes
t
er f
o
r
Spacecraft Data Acquisition System
Ma
no
j Kum
a
r
A
1
,
R.
V.
N
a
da
go
ud
a
2
, R. Jegan
3
1
Department of
Electronics and
I
n
strumentation
Engineering,
Karun
y
a
Universi
t
y
, Coim
bator
e
,
In
dia
2
Spacecr
aft
Che
c
kout Group
, IS
RO Satel
lit
e C
e
n
t
re, Bang
alore
,
I
ndia
3
Department of Electronics
and
I
n
strumentation
Engineering,
Karun
y
a
Universi
t
y
, Coim
bator
e
,
In
dia
Article Info
A
B
STRAC
T
Article histo
r
y:
Received Feb 10, 2014
Rev
i
sed
Ap
r
24
, 20
14
Accepted
May 10, 2014
Bit Erro
r Ra
te
(BER) is
a pr
incipl
e m
easure
of da
ta
trans
m
ission link
performance. B
E
R tester (B
ER
T) consists of
a Pattern Gener
a
tor and
an
Anal
yzer th
at ca
n be set to the sam
e
pattern. T
h
e pa
yload dat
a
transm
itted
from
the s
p
acec
raft cons
is
ts
of one, two or thre
e channe
ls
per c
a
rrier bas
e
d
on the modulation scheme. Th
e
traditi
onal equ
i
p
m
ents can
do B
E
R an
aly
s
is
for onl
y
one channel at a tim
e. In order to support m
u
ltichannel BE
R
anal
ys
is
,
a P
e
rs
onal Com
puter (P
C)
based
s
y
stem is d
e
signed an
d
implemented in
Altera Stratix
II (E
P2S130F15
08C5N) FPGA. Ethern
et
is
configured
using WIZnet 5300
(Ethern
e
t Con
t
roller)
and it is used for
com
m
unication
between
FPGA and PC with
an
appl
ica
tion
.
Ap
plic
ation
is
used to transm
it the Pattern Ge
nerator’s conf
ig
urations from
PC to FPGA
and to
re
ceiv
e
Anal
yz
er’s
s
t
atus
. P
a
cket pr
ocessing is do
ne for
this
communication
using User Datagram
proto
c
ol (UDP). On the whole,
tradit
iona
l equip
m
ents
are repl
a
ced
b
y
the d
e
signed and implemented bit
error r
a
te tester.
Keyword:
Altera Strati
x
II FPGA
Bit Erro
r Rate
Tester
Packet Process
i
ng
PCI-X Card
WIZ
net 53
0
0
Copyright ©
201
4 Institut
e
o
f
Ad
vanced
Engin
eer
ing and S
c
i
e
nce.
All rights re
se
rve
d
.
Co
rresp
ond
i
ng
Autho
r
:
Man
o
j
Ku
m
a
r
A
,
Depa
rt
m
e
nt
of
El
ect
roni
cs
an
d
Inst
rum
e
nt
at
ion
E
ngi
neeri
n
g
,
Ka
r
uny
a
U
n
i
v
ersi
t
y
,
C
o
i
m
bat
o
re, I
n
di
a,
64
1
1
1
4
,
and
Si
un
g
To
w
n
shi
p
, C
h
i
a
y
i
C
o
u
n
t
y
62
10
2,
Tai
w
an
Em
a
il: man
o
j
ku
m
a
ra@k
arunya.ed
u
.in
1.
INTRODUCTION
Bit error
rate (BER) of a transmissio
n
link
i
s
calcu
lated
as
fo
llows.
BER = No
of bit errors/ T
o
tal
no of
bits recei
ved
Exam
ple:
N
o
of
b
it err
o
rs = 1
To
tal no
o
f
b
its tran
sm
itted
= 1
0
6
BER = 1 x 10
-6
In a
noisy cha
nnel, BER is e
x
presse
d as a
functio
n of normalized
carrier-t
o-
n
o
i
s
e m
easure
de
not
e
d
b
y
Eb
/N0
,
(energ
y
p
e
r b
it to no
ise power
sp
ectral
d
e
ns
ity ratio
). BER
cu
rv
es are
p
l
otted
to
d
e
scri
be th
e
functionality of a digital comm
unica
tion syste
m
. In digital comm
unicati
on, BER vs. Received Power (dBm
)
is u
s
u
a
lly u
s
ed; wh
ile in wi
reless co
mm
u
n
i
catio
n
,
BER
v
s
. SN
R
(d
B)
is
u
s
ed
[4
].
Su
ch a p
l
o
t
is sh
ow
n in
Fi
gu
re 1.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
089
-48
64
IJR
E
S V
o
l
.
3, No
. 2,
J
u
l
y
20
1
4
:
7
6
– 84
77
1
.
1
.
Bit Error Ra
te Tester
(BERT)
B
E
R
T
s use p
r
e
d
et
erm
i
ned dat
a
pat
t
e
rns c
o
n
s
i
s
t
i
ng o
f
a seq
u
e
nce o
f
l
ogi
cal
ones a
nd ze
ro
s gene
rat
e
d
by
a t
e
st
pat
t
e
rn ge
ne
rat
o
r t
o
t
e
st
di
gi
t
a
l
com
m
uni
cat
i
on ci
rcui
t
s
. Gene
rat
o
r a
nd
Anal
y
zer can be us
ed i
n
pai
r
s,
wi
t
h
o
n
e
at
ei
t
h
er end
of a t
r
a
n
sm
i
ssion l
i
n
k,
or si
n
gul
a
r
l
y
at
one end
wi
t
h
a
l
o
o
pbac
k
at
t
h
e
re
m
o
t
e
end
.
C
o
m
m
on t
y
pes o
f
B
E
R
T
pat
t
e
r
n
s a
r
e
pse
u
d
o
ra
n
dom
bi
na
ry
se
que
n
ce (PR
B
S
),
Q
u
asi
R
a
n
d
o
m
Si
gnal
Sou
r
ce (QRSS), B
r
idg
e
tap
,
Mu
ltip
at etc. In
th
is proj
ect PRBS is u
s
ed
[2] [3
].
Fig
u
r
e
1
.
Bit-
er
ro
r r
a
te cu
rv
es fo
r
BP
SK,
QP
SK,
8-PS
K a
nd 16-P
SK,
AWGN cha
n
nel
1.
2.
PRB
S
P
a
t
t
ern
Gener
a
tor
Pseu
do
ra
nd
om
B
i
nary
Seq
u
e
n
ce Pat
t
e
rn
Ge
nerat
o
r i
s
use
d
for t
h
e dat
a
g
e
nerat
i
o
n. Li
ne
ar Feed
bac
k
Shift Re
gisters
(LFSR) a
r
e
us
ed to
create th
i
s
p
a
ttern
. Vario
u
s
in
tern
ati
onal standa
rds
[1] are used to c
r
eate
th
is p
a
ttern
as
sh
own
in tab
l
e
1
.
Tabl
e 1. PN
Se
que
nces
n L
a
bel
Poly
no
m
i
al
Refer
e
nce
St
andard
T
a
ps
Sequence L
e
ngth (2
n
– 1 bits)
7 PN7
x
7
+x
6
+1
Not
Standar
d
6,
7
127
15
PN15
x
15
+x
14
+1
I
T
U-
T
O.
150
14,
15
3276
7
17
PN17
x
17
+x
14
+1
OI
F-
C
E
I
-
P-
02.
0
14,
17
1310
71
20
PN20
x
20
+x
3
+
1
I
T
U-
T
O.
150
3,
20
1048
575
23
PN23
x
23
+x
18
+1
I
T
U-
T
O.
150
18,
23
8388
607
1.
3
P
N
7 Se
q
u
ence
The dat
a
f
o
r P
N
7 i
s
ge
nerat
e
d by
d
o
i
n
g XO
R
operat
i
o
n o
f
6
th
and
7
th
b
its an
d
th
e
XOR ou
tpu
t
is fed
back to t
h
e
1
st
bi
t
[
1
]
w
h
i
c
h i
s
sh
ow
n i
n
fi
g
u
r
e
2.
Fi
gu
re 2.
P
N
7
Seq
u
ence
Th
e seed
wo
rd
an
d th
e
d
a
ta
for PN7 is as
fo
llo
ws.
PN7
Seed
wo
rd
=
11
111
11
PN7
d
a
ta
= 1
1
1
1
111
0
000
0 0
100
0
001
1
000
0
111
....
(b
inar
y)
F
E
0
4
1
8
7 …
(
h
e
x
)
Sim
i
l
a
rl
y
for
o
t
her
Pseu
d
o
ra
n
dom
Num
b
er
(
P
N)
se
que
nces
, t
h
e
dat
a
ca
n
b
e
ge
nerat
e
d.
Out
put
XOR
1
2
3
4
5
6
7
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
RES
I
S
SN
:
208
8-8
7
0
8
FPGA b
a
sed
Mu
ltich
a
nn
el Bit
Error
Rate Test
er for Sp
acecraft
Data Acq
u
i
sition
System
(
M
anoj
K
u
m
a
r A)
78
2.
R
E
SEARC
H M
ETHOD
2.
1.
B
l
oc
k
Di
agr
am
Fo
r
g
e
n
e
rat
o
r,
th
e in
pu
ts are
fro
m
th
e PC
with
ap
pl
i
cat
i
on. F
o
r t
h
ree c
h
an
nel
s
nam
e
l
y
C
H
1, C
H
2
and C
H
3
,
t
h
e
v
a
ri
o
u
s i
n
put
c
o
nfi
g
u
r
at
i
on
pa
r
a
m
e
t
e
rs are cl
o
c
k, re
set
,
P
N
s
e
l
ect
i
on (P
N
7
,
PN
15
, PN
1
7
,
PN
2
0
and P
N
23
), er
r
o
r rat
e
i
n
ject
i
o
n an
d m
a
nual
err
o
r
.
The
o
u
t
put
o
f
ge
nerat
o
r i
s
cl
ock a
n
d
t
h
e PR
B
S
dat
a
. The
out
puts a
r
e a
v
ailable in the
LVDS
O/P int
e
rface. For a
n
alyzer, the i
n
puts are
cloc
k a
n
d PRBS
data
of the
three channels. The outputs are clock
prese
n
ce, BER lock,
PN detected,
no
o
f
bi
t
s
el
apse
d d
u
ri
ng l
o
ck
,
no
of
b
its elap
sed d
u
r
i
ng
un
lock for eac
h channel.
Th
e PCI-X card
co
nsists o
f
Altera
Stratix
II
(EP2S130F1508C5N) FP
GA, WIZnet 5300 (Ethernet
Controller), LAN Port, LV
DS I/O interfaces. A PC
with
a
GUI is co
nn
ected to
t
h
e PCI-X Card
throug
h
LA
N
p
o
r
t
.
T
h
e
bl
oc
k
d
i
agram
i
s
sho
w
n i
n
fi
gu
re
3.
Fi
gu
re 3.
B
l
oc
k Di
ag
ram
2.
2.
H
a
rdw
a
re
2.
2.
1.
Cus
t
o
m
i
z
ed
PCI-
X
Car
d
Peri
p
h
eral
C
o
m
ponent
I
n
t
e
r
c
on
nect
eXt
e
n
d
ed
(PC
I
-X
) i
s
a
6
4
bi
t
co
m
put
er bus
a
n
d
e
xpa
nsi
o
n
card
st
an
dar
d
t
h
at
en
ha
nces
t
h
e
3
2
-
b
i
t
PC
I L
o
cal
B
u
s
f
o
r
hi
ghe
r
ba
n
d
wi
dt
h
dem
a
nded
by
ser
v
er
s
.
T
h
e
cu
sto
m
ized
card
(64
b
it/
10
0 MHz)
is of
th
e typ
e
as
sh
own
in
fi
g
u
re
4
.
94
p
i
n
s
are t
h
ere in
th
e card
.
Fi
gu
re
4.
U
n
i
v
ersal
(
3
.
3
V &
5V
)
64
-
b
i
t
PC
I
C
a
rd
Table 2. Features
Features
Quantity
Adaptive logic
m
o
dules (
A
L
M
s
)
53,
016
Adaptive look-
up t
a
bles (
A
LUT
s
)
106,
03
2
E
quivalent logic elem
ents
132,
54
0
M
512 RAM
blocks
699
M
4
K RAM
blocks
609
M
-
RAM
blocks
6
T
o
tal RAM bits
6,
747,
84
0
DSP blocks
63
18-bit × 18-bit
m
u
l
tipliers
252
E
nhanced PL
L
s
4
Fast PL
Ls
8
T
o
tal pins
1,
126
C
u
st
o
m
ize
d
PC
I
-
X
Da
ta
A
c
q
u
i
s
i
t
i
o
n
Ca
rd
Al
t
e
ra St
rat
i
x I
I
(
E
P
2
S1
3
0
F
1
50
8C
5N
)
FPGA
LAN P
o
rt
WIZ
n
et
5300
(Eth
ern
e
t
C
ont
r
o
l
l
e
r)
LVDS
O/P
Interface
LVDS
I/P
Interface
PC with
GUI
Channel 1
Channel 3
Channel 2
Gene
rato
r
Analyzer
Channel 1
Channel 3
Channel 2
Channel 1
Channel 3
Channel 2
Channel 1
Channel 3
Channel 2
Reset
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
089
-48
64
IJR
E
S V
o
l
.
3, No
. 2,
J
u
l
y
20
1
4
:
7
6
– 84
79
2.
2.
2.
Al
ter
a
Str
a
ti
x II
(E
P
2
S
1
3
0
F
1
50
8
C
5N
) F
P
G
A
The cl
ock
f
r
eq
uency
o
f
t
h
i
s
F
P
G
A
i
s
64
0 M
H
z.
The
features are
show
n in
th
e Tab
l
e 2 [5
].
2.
2.
3.
WIZ
n
et
53
0
0
(E
ther
net
Co
ntr
o
l
l
er)
In t
h
is Ethe
rne
t
controller m
e
m
o
ry is extended to
128Kbyte and 16
bit bus
interface
is s
u
pporte
d
. It
con
s
i
s
t
s
of ei
g
h
t
har
d
wa
re s
o
cket
s w
h
i
c
h can be use
d
s
i
m
u
l
t
a
neousl
y
.
In t
h
i
s
pr
o
j
e
c
t
onl
y
one i
s
used.
C
o
m
m
uni
cat
i
o
n can be est
a
bl
i
s
he
d usi
n
g
Prot
oc
ol
s suc
h
as Transm
i
s
si
on C
o
nt
r
o
l
Prot
ocol
(TC
P
),
Use
r
Dat
a
g
r
am
Prot
ocol
(U
DP
),
I
P
R
A
W an
d
M
A
C
R
A
W. T
C
P i
s
a c
o
n
n
ect
i
on-
ori
e
nt
ed
pr
ot
o
c
ol
.
U
D
P
i
s
a
con
n
ect
i
o
n-l
e
s
s
p
r
ot
ocol
.
U
D
P s
u
pp
o
r
t
s
uni
cast
,
b
r
oa
d
cast
an
d m
u
l
t
i
cast
m
e
t
hods
.
In
t
h
i
s
pr
o
j
e
c
t
UD
P
(unicast m
e
thod) is
use
d
[6].
Soc
k
et status t
r
ansitio
n for
UDP
(Unicast m
e
thod) a
n
d UDP
operation flow
are
sho
w
n i
n
fi
gu
r
e
5 a
n
d
6
respe
c
t
i
v
el
y
.
Di
rect
ad
d
r
essi
ng
m
ode i
s
i
m
pl
em
ent
e
d. Fo
r
1
6bi
t
dat
a
b
u
s
wi
dt
h,
AD
DR
[9:
1
]
i
s
use
d
a
n
d
A
DDR
0
is co
nn
ected
to
groun
d
o
r
fl
o
a
ted
.
'BIT16EN' is in
tern
ally p
u
lled
-
u
p
, so
it is n
o
p
r
oble
m
if
it is
all
o
wed
to
f
l
o
a
t. Th
e
connectio
n
s
ar
e show
n in
f
i
gu
r
e
7.
Fi
gu
re
5.
S
o
ck
et
St
at
us T
r
ans
i
t
i
on f
o
r
U
D
P
Prot
oc
ol
(U
ni
cast
m
e
t
hod)
Tabl
e 3.
E
r
r
o
r R
a
t
e
In
ject
i
o
n
Rate Selection
BER
2 1x10
-2
3 1x10
-3
4 1x10
-4
5 1x10
-5
6 1x10
-6
7 1x10
-7
Fi
gu
re 6.
U
D
P Ope
r
at
i
o
n
fl
ow
Fig
u
r
e
7
.
D
i
r
e
ct A
ddr
ess M
o
de w
ith
16
b
it data b
u
s
width
2.
3.
S
o
f
t
w
a
r
e
Al
t
e
ra
Qua
r
t
u
s
II
1
3
.
0
i
s
use
d
f
o
r F
P
G
A
pr
og
ram
m
i
ng [
7
]
.
Ve
ri
l
o
g c
odi
ng
i
s
do
ne
fo
r
t
h
i
s
p
r
o
j
ect
.
Micros
oft Vis
u
al Basic (VB
)
is used
fo
r
Graphical
User Interface (GUI).
P
acket proce
ssing is done in VB.
0
1
0
Ed
ito
r is used
to
conv
ert
b
y
tes o
f
d
a
ta i
n
to
ch
aracters
in
o
r
d
e
r t
o
transmit
th
e d
a
ta fro
m
PC to
FPGA in
VB
base
d
GU
I
.
W
i
res
h
a
r
k
(N
et
wo
rk
Pr
ot
oc
ol
A
n
al
y
zer) i
s
use
d
t
o
a
n
al
y
ze t
h
e dat
a
t
r
a
n
s
m
i
t
t
e
d an
d rec
e
i
v
e
d
/CS
/RD
/WR
/INT
ADDR
DATA
BIT1
6
E
N
/CS
/RD
/WR
/INT
ADDR [
9
:3]
ADDR [
2
:1]
ADDR0
DAT
A [15:8]
Ho
st Co
n
t
ro
ller
(FPGA
)
WI
Zn
et
5300
(Ethernet
Co
n
t
ro
ller)
X
X
VVV
VCC
OPEN
Received Data ?
Receiving
Process
Yes
No
Send Data ?
Sending Pr
ocess
Yes
No
Finished ?
Yes
Co
m
p
lete
Sending ?
T
i
m
e
out ?
No
Yes
No
No
CLOSE
Yes
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8-8
7
0
8
FPGA b
a
sed
Mu
ltich
a
nn
el Bit
Error
Rate Test
er for Sp
acecraft
Data Acq
u
i
sition
System
(
M
anoj
K
u
m
a
r A)
80
with
inform
ation suc
h
as IP addre
sses
of the sender a
n
d receiver,
num
b
er of
bytes, communication prot
ocol
use
d
, etc.
2
.
4
.
V
erilog Prog
ra
mming
Fo
r th
e three ch
ann
e
ls, clo
c
k
,
reset, PN typ
e
selec
tio
n
,
th
e
erro
r rate i
n
j
ectio
n
,
m
a
n
u
a
l error i
n
j
ection
are take
n ca
re
in the
program
m
ing. T
h
e e
r
ror rate i
n
jec
tio
n is m
e
n
tio
n
e
d
in
tab
l
e
3
.
In
ord
e
r to an
alyze th
e
seri
al
i
nput
o
f
t
h
e anal
y
zer, a
n
al
go
ri
t
h
m
i
s
use
d
an
d t
h
e sam
e
i
s
used i
n
veri
l
o
g p
r
o
g
r
a
m
m
i
ng. Fl
ow c
h
art
o
f
th
e algo
rith
m
is shown in
t
h
e
figu
re
8
.
Fi
gu
re 8.
P
N
7
Dat
a
A
n
al
y
zer Fl
ow
C
h
a
r
t
Start
1
2
3
4
5
6
7
Inc
o
m
i
ng
serial data
to Analyzer
2
3
4
5
6
7
XOR
Loa
d
i
n
g 6 bi
t
s
in a
register
XOR
If
Bit Er
ro
r =
=1
?
I
n
cr
e
m
ent T
h
r
e
sho
l
d Counte
r
Yes
I
f
T
h
r
e
shold Count
er
<=20 ?
Yes
BER Lock = 1
Incre
m
ent the no.
of bits
elapsed dur
ing loc
k
BER Lock = 0
Incre
m
ent the no.
of bits
elapsed dur
ing unl
ock
No
If
Bit Er
ro
r =
=1
&
&
BER Lock =
= 1?
Yes
In
cre
m
en
t n
o
.
o
f
b
it erro
rs
End
BER = No
.
o
f
b
it erro
rs
/
No. of bits e
l
a
p
sed dur
in
g
loc
k
Fr
ee r
unnin
g
count
e
r
I
n
cr
e
m
ent fr
ee
r
unning
counter
I
f
Fr
ee
r
unning co
unter
= = 98?
Yes
No
No
No
Evaluation Warning : The document was created with Spire.PDF for Python.
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64
IJR
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S V
o
l
.
3, No
. 2,
J
u
l
y
20
1
4
:
7
6
– 84
81
3.
R
E
SU
LTS AN
D ANA
LY
SIS
Th
e sim
u
latio
n resu
lt of three
ch
ann
e
l PRBS
g
e
n
e
rator is sho
w
n
i
n
Fi
g
u
re
9
.
CH
1_
GEN_DA
TA - PN
7 d
a
ta w
itho
u
t
er
ror
CH
2_
GEN_DA
TA - PN
7 d
a
ta w
ith
10
1
error rate i
n
jectio
n
CH
3_
GEN_DA
TA - PN
7 d
a
ta w
ith
m
a
n
u
a
l
er
ro
r
Fi
gu
re
9.
PR
B
S
Ge
ne
rat
o
r
Si
m
u
l
a
t
i
on R
e
s
u
l
t
3.1.
P
a
cket Processing and
Impleme
ntatio
n
in A
l
t
era St
ra
t
i
x
II (
E
P2
S1
30
F15
08C5
N
)
FPGA
Th
e d
a
ta p
a
cket sen
t
fro
m
P
C
to
FPGA is o
f
14
b
y
tes. B
u
t alo
n
g
with
th
e UDP d
a
ta fo
rm
at
it
is o
f
22
by
t
e
s (4
b
y
t
es-Dest
i
n
at
i
o
n IP a
d
d
r
ess
,
2 by
t
e
s-
Dest
i
n
at
i
on p
o
rt
nu
m
b
er, 2 by
t
e
s-
B
y
t
e
si
ze of the dat
a
packet and 14
bytes-data pa
c
k
et).
T
h
e UDP data form
at is
shown in fi
gure 10. T
h
e data
receive
d from
FPGA
to
PC is
of
7
2
b
y
tes co
m
p
risin
g
of all th
e t
h
ree ch
ann
e
l
s
i
n
f
o
rm
at
i
on su
ch as
n
o
.
o
f
bi
t
err
o
rs
,
no
.
of
bi
t
s
elapsed
during lock,
no. of bi
ts elap
sed during unloc
k
,
etc.
The
recei
ved da
ta pac
k
ets are shown in fi
gure
11.
The
PC
ba
sed
appl
i
cat
i
o
n
use
d
fo
r t
h
i
s
p
r
o
j
e
c
t
i
s
sh
ow
n i
n
f
i
gu
re
12
.
Fi
gu
re 1
0
. U
D
P
dat
a
f
o
rm
at
Destination
I
P
Addr
ess
Destination
Port
Nu
m
b
e
r
Byte Si
ze
of Data
Packet
Real Data
4
Bytes
2
Bytes
2
Bytes
Size sp
ecif
i
ed
in
PACKE
T
-I
NFO
Evaluation Warning : The document was created with Spire.PDF for Python.
I
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RES
I
S
SN
:
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8-8
7
0
8
FPGA b
a
sed
Mu
ltich
a
nn
el Bit
Error
Rate Test
er for Sp
acecraft
Data Acq
u
i
sition
System
(
M
anoj
K
u
m
a
r A)
82
Fi
gu
re 1
1
. G
U
I
use
d
fo
r pac
k
e
t
di
spl
a
y
Fig
u
re
12
. BER Tester
GUI
3
.
2
.
Testing with Tektronix
Giga
BERT
TM
7
0
0
Genera
to
r a
n
d
ANALY
Z
ER
Th
e
d
e
sign
ed
an
d im
p
l
e
m
en
ted
BERT is test
ed
with
th
e stan
d
a
rd
eq
u
i
p
m
e
n
ts and
it is
fou
n
d
t
h
at th
e
desi
g
n
e
d
B
E
R
T
res
u
l
t
s
an
d t
h
e st
an
da
rd
eq
ui
pm
ent
s
res
u
l
t
s
are m
a
t
c
hi
ng. T
h
e s
e
t
u
p i
s
sh
ow
n i
n
fi
gu
re 1
3
an
d Figur
e
1
4
.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
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:
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64
IJR
E
S V
o
l
.
3, No
. 2,
J
u
l
y
20
1
4
:
7
6
– 84
83
Fi
gu
re 1
3
.
Te
st
i
ng desi
gne
d G
e
nerat
o
r wi
t
h
Tekt
r
oni
x gi
ga
B
E
R
T
TM
700
Analyzer
Fi
gu
re 1
4
.
Te
st
i
ng desi
gne
d A
n
al
y
zer wi
t
h
T
e
kt
r
oni
x gi
gaB
E
R
T
TM
70
0
Ge
nerat
o
r
4.
CO
NCL
USI
O
N
A cust
om
B
E
R
t
e
st
er i
s
desi
gne
d a
nd i
m
pl
em
ent
e
d
to characterize and
valid
ate a transmission link.
Th
e
h
a
rdw
a
r
e
p
l
atf
o
r
m
s ar
e th
e cu
sto
m
ized
PCI
-
X
car
d
con
s
istin
g of
A
lter
a
Str
a
ti
x
II
(EP2
S130
F1508
C5N)
FPG
A,
WIZ
ne
t
530
0 (
E
t
h
er
n
e
t
C
ont
rol
l
e
r
)
,
LAN
p
o
rt
an
d
LVD
S
i
n
t
e
r
f
ac
es. The sy
st
em
ope
rat
e
s u
p
t
o
20
0
MHz.
User i
n
t
e
rface is im
ple
m
ented for
data acquisiti
on and test anal
ysis. UDP tra
n
sm
ission prot
ocol is
expe
ri
m
e
nt
ed.
These
ex
peri
e
n
ce s
h
ow
t
h
e
bene
fi
t
s
of
FP
GA
ba
sed
B
E
R
t
e
st
er i
n
sy
s
t
em
prot
ot
y
p
i
n
g a
n
d
cust
om
i
zat
i
on.
ACKNOWLE
DGE
M
ENTS
The a
u
thors
woul
d like
to t
h
an
k Spacecra
f
t
Chec
kout
Group, ISRO
Sa
tellite Centre, Bangal
o
re,
Ind
i
a,
for
p
r
ov
id
ing
lab facilities and
sup
portin
g th
e
proj
ect.
REFERE
NC
ES
[1]
Daniele Riccard
i
, Paolo Novellin
i, “An Attribute-
Programmable
P
RBS
Generator
and Check
er”
,
XAPP884 (
v
1.0)
,
Januar
y
10
, 201
1.
[2]
Annie Xiang
,
D
a
tao
Gong, Suen
Hou, Chongh
an
Liu
,
Fu
tian Liang, Tianku
an Li
u, Da-Shung Su,
Ping-kun Teng,
Jingbo Ye, “Design and
ver
i
fication of
an
FPGA based bit
error r
a
te
tester
”,
E
l
s
evi
er
, Ph
ys
ics
Pr
oc
edia
, 2011.
[3]
Ł
ukasz ´
S
liwczy
´
nski, Przem
y
s
ł
aw Krehlik
, “
B
it Error
Rat
e
T
e
ster for 10 Gb/s
Fibre Optic
Li
nk”,
Ad
vances in
Electronics and
Telecommunica
tions
, vol. 1
,
no
.
2, pp
. 70-73
, No
vember 2010.
[4]
Manas Singhal,
Pankaj Bhardw
aj, Manish Trikh
a
, “Comparison o
f
BER
for Advance Modulation
Techn
i
que using
Bit Error R
a
te
Tester”,
MIT Inter
national Journal of Elect
ronics and Communica
tion Engineering
,
vol. 2, no
. 1
,
pp
.
16-19, Janu
ar
y
2
012.
[5]
Stratix
II Dev
i
ce Handbook,
Al
te
ra Corporation
,
Vol. 1
,
May
200
7.
[6]
High-Performance In
tern
et Conn
ectivity
So
lution
W5300, Versio
n 1.1
.
1, 2008.
[7]
Anshuman Shar
ma, Abdul Hafeez S
y
ed, Midhu
n M, M
R Raghavendra, “Realizati
on of Progr
ammable BPSK
Dem
odulator-Bi
t
S
y
nchron
izer
using Multirate Processing”,
International
Journal of Reconfigurable a
nd
Embedded S
y
stems,
vol. 3, no. 1, pp.
18-24, March 2014.
BIOGRAP
HI
ES OF
AUTH
ORS
Manoj Kumar A is an M.Tech student at Karun
y
a
Universit
y
,
Co
im
batore.
He h
a
s carr
i
ed ou
t his
full semester pr
oject in Spacecr
aft Checkout Gr
oup at ISRO Satellite Centr
e
, B
a
ngalor
e
under
the guid
a
nce of
Mr. R V Nadagouda and Mr.
R Jega
n. His r
e
search in
ter
e
st includes Digital
Signal Processing and
Embedded
S
y
stems.
T
e
ktr
onix
gigaBE
RT
TM
700
Generator
Designed
BERT
Application
GUI
T
e
ktr
onix
gigaBE
RT
TM
700
Analyze
r
Designed
BERT
Application
GUI
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
RES
I
S
SN
:
208
8-8
7
0
8
FPGA b
a
sed
Mu
ltich
a
nn
el Bit
Error
Rate Test
er for Sp
acecraft
Data Acq
u
i
sition
System
(
M
anoj
K
u
m
a
r A)
84
R V Nadagouda is a Scientist
an
d Head of Geos
at Checkou
t Div
i
sion at ISRO Satellit
e Cent
re,
Bangalor
e
. He
joined ISRO in
the
y
e
ar 1989.
He has completed B.E.
(E & C)
and
M.Tech
(Industrial Electronics) in Karnatak
a Regional
Engineering College (KREC), S
u
rathkal. His
res
earch
int
e
res
t
includ
es
Develo
pm
ent of Bas
e
b
a
nd Interf
ac
e &
T
e
s
t
S
y
s
t
em
s
and
High Bit R
a
t
e
Data Acqu
isition
S
y
stem
s.
R Je
ga
n is
a
n
A
ssista
n
t Profe
ssor a
t
Karuny
a
Un
iversity
, Coimbatore. He is
currently
pursuing
Ph.D in Wireless Technolog
y
at Anna Univers
ity
. He was awar
ded First Rank in P.G Degree
Course in Embedded S
y
stems and currently
guidi
ng many
Embed
d
ed projects. He has published
3 international journals and atte
nded 8 international confer
ences.
His
res
earch i
n
teres
t
in
clude
s
Embedded Contr
o
l S
y
stem and
Signal Processing.
Evaluation Warning : The document was created with Spire.PDF for Python.