Intern
ati
o
n
a
l
Journ
a
l of
Re
con
f
igur
able
and Embe
dded
Sys
t
ems
(I
JRES)
V
o
l. 3,
N
o
.
2
,
Ju
ly 20
14
, pp
. 39
~48
I
S
SN
: 208
9-4
8
6
4
39
Jo
urn
a
l
h
o
me
pa
ge
: h
ttp
://iaesjo
u
r
na
l.com/
o
n
lin
e/ind
e
x.ph
p
/
IJRES
FPGA E
valu
a
tion of Reconfig
urable Modules with Fault
Detection and Repair Technique
Pradee
p C*, Radh
akrishn
a
n
R**
*Departm
ent
of
ECE,
SAINTGITS Colleg
e
of
Engineer
ing, Kottay
am, Ker
a
la, In
dia
** Sri Shakth
i In
stitute of
Engin
e
ering
&Technol
og
y
,
Coim
bator
e
, T
a
m
ilnadu
,
Ind
i
a
Article Info
A
B
STRAC
T
Article histo
r
y:
Received
Ja
n 22, 2014
Rev
i
sed
Ap
r 5, 20
14
Accepted Apr 22, 2014
This pap
e
r prop
oses a fau
l
t detection
and r
e
pa
ir
algorithm
whi
c
h
is suit
able
for fault fr
ee re
configurab
le s
y
s
t
em
s. In recen
t
ye
ars Built
in S
e
lf Repa
ir
digital s
y
s
t
ems have got ver
y
important
role
i
n
the
appli
cat
io
ns
s
u
ch as
nucle
ar s
y
s
t
em
s
,
s
p
ac
e m
i
s
s
i
ons
and com
m
unicat
ion s
y
s
t
em
s
etc
wher
e
s
y
stem
rel
i
abi
lit
y is v
e
r
y
cr
iti
c
a
l. S
y
stem
s des
i
gned to op
era
t
e in c
r
iti
ca
l
conditions will collapse due
to ev
en a
single f
a
ult
occurren
c
e. To avoid these
situations m
a
n
y
m
e
thods have de
velope
d in r
ecen
t
y
ears. Th
is work proposes
an are
a
effi
ci
en
t and fas
t
fau
l
t
de
tection
and repair
algorithm. For the
evalu
a
tion of the new approach a
nd older
methods a sy
stem with a
standalon
e
module and four
add
on modul
es were designed
and evaluated for
resource utilization using XUPV5 board
. The
en
tire FPGA is di
vided in to
tiles
and each
m
odule is im
plem
ented
in d
i
fferen
t
t
iles u
s
ing parti
a
l
reconfigur
ation
m
e
thod using Xilinx Plan
Ahead 14.2
with partial
reconfigur
ation
f
aci
lit
y.
Keyword:
CLB
Fau
lt Detection
FPGA
Partial Recon
f
i
g
uration
Self Repai
r
Copyright ©
201
4 Institut
e
o
f
Ad
vanced
Engin
eer
ing and S
c
i
e
nce.
All rights re
se
rve
d
.
Co
rresp
ond
i
ng
Autho
r
:
Pra
d
eep C,
Depa
rt
m
e
nt
of
EC
E, S
A
I
N
T
G
ITS C
o
l
l
e
ge
of
En
gi
nee
r
i
n
g,
Kot
t
a
y
a
m
,
Ker
a
l
a
, I
ndi
a
0
944
766
135
5
Em
a
il: pradee
pcee@gm
ail.com
1.
INTRODUCTION
In a
n
y syste
m
s
,
system failure
occu
rs w
h
e
n
t
h
e sy
st
em
devi
at
es from
i
t
s
requi
rem
e
nt
s, whi
c
h m
a
y
be
catastro
p
h
i
c for sp
ecific critical ap
p
licatio
n
s
[1
]. Su
ch
syst
e
m
s h
a
v
e
red
u
n
d
a
n
t
h
a
rd
ware so
th
at op
eratio
n
a
l
reliab
ility is u
n
c
o
m
p
r
o
m
ised
b
y
iso
l
ated failu
re [2
].
Reco
nfigu
r
ab
le sy
ste
m
s u
s
e run
t
i
m
e reco
nfigu
r
ation
techniques t
o
adapt t
h
e syste
m
operation
to cha
n
ges in
its ex
tern
al
param
e
ters an
d also
to
i
n
crease th
e
lifetim
e of application. T
h
e l
a
ter can be
ac
hieve
d
if th
e
s
y
ste
m
is capable to
detect, di
agnose
and
re
pair the
fau
lts th
at
o
c
cur
d
u
ring
th
e run
tim
e.
In a Sel
f
R
e
p
a
i
r
i
ng Sy
st
em
vari
o
u
s t
ech
n
i
ques are
used
t
o
fi
nd t
h
e d
e
vi
at
i
on f
r
om
i
t
s
norm
a
l
ope
rat
i
o
n.
Fo
r
an
o
p
t
i
m
al
de
si
gn
o
f
t
h
ese t
echni
que
s,
t
r
a
d
eoffs in area
and tim
e
are consi
d
ere
d
. Repairing
al
go
ri
t
h
m
s
are
m
a
de t
o
perf
or
m
l
ogi
cal corre
ctness and te
mporal correctne
ss
[3
]. A system is
called
lo
g
i
cally
co
rrect if it satisfies all th
e
fun
c
tion
a
lity an
d th
e syst
em is tem
p
o
r
ally
co
rrect if all th
ese
fun
c
tion
s
are
co
m
p
leted
with
in
a sp
ecific t
i
m
e
. So
th
e logical correctne
ss of a fa
ult tolera
nt syste
m
is the recovery
of the
o
r
i
g
in
al
fun
c
tio
n if a fau
lt
occu
rs an
d temp
oral co
rr
ectness is th
e recov
e
ry
of th
e orig
in
al fun
c
tion in
a
sp
ecific tim
e b
o
und
.
In
real time fau
lt to
leran
t
syste
m
s fau
l
t d
e
tectio
n
an
d rep
a
ir m
u
st b
e
d
o
n
e
in a ti
m
e
li
m
i
t.
Pop
u
l
ar app
licatio
n
s
o
f
reco
nfigu
r
ab
le sy
ste
m
s ar
e mi
crowav
e filters for ce
llu
lar
ph
on
es [4
], p
o
wer
m
a
nagem
e
nt
sy
st
em
s and s
p
a
ce craft
.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
089
-48
64
IJR
E
S V
o
l
.
3, No
. 2,
J
u
l
y
20
1
4
:
3
9
– 48
40
Fi
gu
re
1.
Desi
gn
C
y
cl
e fo
r
S
e
l
f
R
e
pai
r
R
e
c
o
n
f
i
g
ura
b
l
e
Sy
st
em
s
In Dy
n
a
m
i
ca
ll
y recon
f
i
g
u
r
ab
le Field Prog
ramm
ab
le Gate Arrays
(FPG
A) a p
a
rtitio
n
can
be
con
f
ig
ure
d
fo
r
fast
fa
ult
rec
o
very
[5]
.
T
h
e desig
n
of se
lf rep
a
irab
le
syst
e
m
co
n
s
ists o
f
fau
lt d
e
tectio
n
,
fau
l
t
d
i
agn
o
sis and
self rep
a
ir
wh
i
l
e syste
m
co
n
tin
u
e
s its
o
p
e
ratio
n
with
fu
ll o
r
p
a
rtial fun
c
tio
n
a
lity. Th
is
p
a
p
e
r
prese
n
t
s
a
n
al
g
o
ri
t
h
m
and i
t
s
eval
uat
i
o
n
fo
r
fast
fa
ul
t
rec
o
v
e
ry
. T
h
e al
g
o
r
i
t
h
m
i
s
useful
i
n
ac
hi
evi
n
g
hi
gh
fa
ul
t
cove
ra
ge i
f
i
t
i
s
used wi
t
h
i
n
crease
d
num
ber
of s
p
are
m
odul
es. The
faul
t
y
m
odul
e
un
de
rg
oes a s
e
l
f
faul
t
det
ect
i
o
n
p
r
oce
ss an
d i
f
t
h
e
fa
ul
t
i
s
t
r
an
si
ent
t
h
e fa
ul
t
y
m
odul
e bec
o
m
e
s t
h
e w
o
r
k
i
n
g m
o
d
u
l
e
agai
n.
2.
STRU
CT
UR
E OF
REC
O
NFIG
U
RABL
E
HA
RD
WA
RE
Field Programmable Gate Arrays are use
d
as the
reconfi
g
urable ha
rdwa
re
.
FPGA de
vice
s are widely
u
s
ed
to
i
m
p
l
e
m
en
t co
m
p
lex
syste
m
s
also
in
ap
p
licatio
ns th
at in
creasing
l
y req
u
i
re cap
acity o
f
au
ton
o
m
o
u
s
sel
f-c
hecki
ng
and
pos
si
bl
y
of s
u
r
v
i
v
al
t
o
faul
t
s
, oft
e
n
wi
t
h
i
n
cost
l
i
m
i
t
a
t
i
ons t
h
at
excl
ude m
a
ssi
ve
red
u
nda
ncy
.
The rec
o
nfi
g
u
r
abl
e
FP
GA c
o
nsi
s
t
s
o
f
an a
r
ray
of c
o
nfi
g
u
r
abl
e
l
o
gi
c bl
o
c
ks (C
LB
s
)
w
h
i
c
h ca
n be
p
r
og
ramm
ed
with
con
f
i
g
uratio
n
cell d
a
ta t
o
g
e
n
e
rate lo
g
i
cal fu
n
c
tion
s
. Th
e set o
f
all co
nfigu
r
ation
cell d
a
ta
makes up an
FPGA confi
g
uration. Each
CLB can be co
nnected to the other CLBs
via the interconnect
n
e
two
r
k
s
. Th
e in
pu
t–ou
tpu
t
sig
n
a
ls can b
e
tran
sm
itted
to
/fro
m
o
u
t
si
d
e
th
e FPGA
u
s
i
n
g th
e inp
u
t
–
o
u
t
pu
t
bl
oc
ks.
A switchi
ng
block is progra
m
m
a
ble conne
cting el
em
ent
receiving lines
on eac
h side.
The lines
con
n
ect
swi
t
c
h
i
ng bl
oc
k pi
ns
i
d
ent
i
f
i
e
d as
n
o
rt
h, east
,
so
ut
h, an
d
west
. So
m
e
pai
r
s of
pi
n
s
i
n
t
h
e bl
oc
k c
a
nn
ot
be c
o
nnected; t
h
ese a
r
e called non connectable (NC) pi
ns
.
Pairs that ca
n
be
connecte
d
a
r
e
called connect
able
pi
ns
. T
h
e c
o
n
n
ect
i
on
of
t
h
e
s
e
t
of
pi
ns i
s
c
o
nt
r
o
l
l
e
d
by
t
h
e
co
nfi
g
u
r
at
i
o
n
cel
l
s
dat
a
The
c
o
n
n
ect
abl
e
pi
n
s
are
rep
r
ese
n
t
e
d
by
dot
t
e
d l
i
n
es
.
A co
n
n
ect
i
on
bl
oc
k has t
h
e
sam
e
st
ruct
ure
as a swi
t
c
hi
n
g
bl
ock
,
exce
p
t
for t
h
e
fact
t
h
at
t
h
e
c
o
n
n
ect
i
o
n
bl
oc
ks
hol
d
ro
ut
i
n
g s
w
i
t
c
hes t
h
a
t
serve
t
o
c
o
n
n
ect
t
h
e l
ogi
c
pi
ns
fr
om
C
L
B
t
o
t
h
e
wire seg
m
en
ts, wh
ile th
e ro
u
t
in
g
switch
e
s of th
e switch
i
ng
b
l
ock
s
allow wire seg
m
en
ts to
b
e
conn
ected
to
o
t
h
e
r
wire segmen
ts. Th
e co
nn
ectio
ns
b
e
tween
lin
es ar
e
also
co
n
t
ro
lled b
y
th
e co
nfigu
r
ati
o
n cells d
a
ta.
If t
h
ese ty
pes
of
rec
o
n
f
ig
ura
b
le ha
rd
wa
re a
r
e u
s
ed
for sys
t
e
m
s which its
res
p
onses a
r
e
critical and
th
o
s
e
shou
ld
op
erate
for long ti
m
e
, a h
i
g
h
lev
e
l ru
n ti
m
e
fau
lt to
leran
ce sh
ou
ld b
e
ach
i
ev
ed .Th
e
b
u
ilt
in
self
rep
a
ir system
cap
ab
le
of
run ti
m
e
fau
lt d
e
t
ectio
n
,
ru
n
tim
e
fau
lt d
i
agno
si
s and
sel
f
rep
a
ir will ex
ten
d
th
e life
ti
m
e
o
f
th
e
reco
nfigu
r
ab
le syste
m
s.
A ci
rc
ui
t
u
nde
r t
e
st
fai
l
s
w
h
e
n
i
t
s
o
b
ser
v
e
d
beha
vi
o
r
i
s
di
f
f
ere
n
t
f
r
om
i
t
s
exp
ect
ed
beha
vi
o
r
. I
f
t
h
e
circu
it is to
b
e
rep
a
ired
, the cau
se of th
e
ob
serv
ed
fa
ul
t
m
u
st
be di
agn
o
se
d [
8
]
.
R
e
pa
i
r
i
ng
oft
e
n co
n
s
i
s
t
s
of
su
bstitu
tin
g
one o
f
its rep
l
aceab
le u
n
its (CLB) id
en
tified
as
co
n
t
ain
i
n
g
fau
lts an
d
referred
as a fau
lty C
L
B, b
y
a go
od C
L
B
.
The di
a
g
n
o
si
s
pr
ocess i
s
oft
e
n hi
era
r
c
h
i
cal
. B
u
t
Xi
l
i
nx r
e
l
eased FP
GA
Li
ke Vi
rt
ex
5 ha
s
i
n
t
e
rnal
reco
nf
i
g
u
r
at
i
on s
u
pp
ort
[
8
]
.
I
n
t
h
e
s
e t
y
pe of
FP
GA
’s t
h
e
rec
o
nfi
g
u
r
at
i
on
o
f
som
e
l
ogi
c bl
o
c
ks a
n
d
wi
re se
gm
ent
s
are
pos
si
bl
e,
w
h
i
l
e
som
e
ot
he
r
pr
og
ram
m
able ha
rd
ware
i
s
i
n
t
h
e
f
u
nct
i
ona
l
m
ode
(“R
u
nn
i
ng”
).
3.
RELATED WORK
To i
n
t
r
od
uce
f
a
ul
t
t
o
l
e
ra
nce
i
n
rec
o
nfi
g
u
r
a
b
l
e
sy
st
em
s
m
a
ny
ap
p
r
oac
h
e
s
ha
ve
bee
n
d
e
vel
o
ped
by
researc
h
ers in this field and
a few of them
are consi
d
ered
in
th
is p
a
p
e
r. In
m
o
d
e
rn
FPGA’s th
e prev
iou
s
ly
un
use
d
pa
rt
s can be rec
o
nfi
g
ure
d
wi
t
h
t
h
e
fu
nct
i
o
nal
m
odul
e t
o
re
pl
ace
t
h
e faul
t
y
par
t
of t
h
e FP
GA
. Al
s
o
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
RES
I
S
SN
:
208
8-8
7
0
8
FPGA
Eval
u
a
t
i
on
of
Rec
o
nf
i
g
ura
b
l
e
M
o
dul
e
s
w
i
t
h
F
aul
t
D
e
t
ect
i
on
an
d R
e
pai
r
Tec
hni
qu
e
(
P
radee
p
C
)
41
t
h
ere a
r
e m
a
ny
cost
effect
i
v
e and
ef
fi
ci
ent
m
e
t
hods
ha
ve
been
de
vel
o
p
e
d f
o
r t
o
l
e
rat
i
ng
fa
ul
t
s
wi
t
h
out
t
h
e
com
p
l
e
t
e
shut
d
o
w
n
of
t
h
e sy
st
em
. Am
ong t
h
ese m
e
t
hods T
r
i
p
l
e
m
odul
ar
re
du
n
d
ancy
(TM
R
) i
s
t
h
e
o
n
e
o
f
t
h
e
first and
m
o
st co
mm
o
n
l
y u
s
ed
techn
i
qu
e.
In
th
is m
e
th
od
th
e sam
e
fun
c
tio
n
is im
p
l
e
m
en
ted
u
s
i
n
g th
ree
equi
val
e
nt
m
odul
es
whi
c
h ru
n si
m
u
l
t
a
neous
l
y
and t
h
e m
a
j
o
ri
t
y
out
put
i
s
use
d
. The
faul
t
i
s
unco
v
ere
d
a
s
soo
n
as a m
i
s
m
atch
occurs.
The
m
a
in dra
w
bac
k
of this
m
e
thod is t
h
e ha
rdware
over
hea
d
for the
functi
onality
repl
i
cat
i
on [
6
]
.
B
u
t
t
h
i
s
appr
o
ach has i
m
m
e
nse t
i
m
i
ng
perform
ance advant
age since there
is no fault det
ection
p
h
a
se is req
u
i
red
.
Th
e system will fun
c
tio
n
co
rrectly o
n
l
y
up
to
o
n
e
fau
lt lev
e
l and
th
e i
m
p
l
e
m
en
tatio
n
co
st is
very
hi
g
h
.
An
ot
he
r m
e
t
hod p
r
o
p
o
se
d i
n
[
7
]
t
h
e n
u
m
b
er of
fu
nct
i
o
nal
m
odul
es t
h
at
can be e
x
pan
d
e
d
o
r
re
duc
e
d
depe
n
d
s o
n
t
h
e
appl
i
cat
i
o
n
.
The f
unct
i
o
nal
m
odul
e em
pl
oy
s a dou
bl
e m
o
dul
a
r
red
u
nda
n
c
y
(DM
R
) fo
r i
t
s
o
w
n
faul
t
det
ect
i
o
n
.
Every
fu
nct
i
o
nal
uni
t
has t
w
o m
odul
es one
i
s
t
h
e acti
v
e (M
) and i
t
s
du
p
l
i
cat
e (M
’). Th
e faul
t
det
ect
i
on
of ea
ch w
o
r
k
i
n
g m
o
d
u
l
e
i
s
do
ne
by
com
p
ari
ng
t
h
e out
put
s
of
M
and M
’
usi
ng a
n
EX
OR
gat
e
. If
fau
lt o
c
cu
rs
XOR g
a
te
o
u
tp
u
t
is o
n
e
an
d
it is u
s
ed to
in
itiate fa
u
lt recov
e
ry
b
y
m
ean
s o
f
p
a
rtial
reco
nfi
g
u
r
at
i
o
n. B
u
t
t
h
i
s
m
e
t
h
o
d
al
so ha
ve a di
sad
v
ant
a
ge of are
a
o
v
er
hea
d
si
nce t
w
o m
odul
es of eac
h
fu
nct
i
o
nal
bl
oc
ks a
r
e i
m
pl
em
ent
e
d a
n
d
due
t
o
t
h
e a
r
ea r
e
ser
v
ed
fo
r s
p
are
m
o
d
u
l
e
.
(
a
)
(b
)
Fi
gu
re
2.
F
u
ct
i
onal
di
ag
ram
of TM
R
a
n
d
D
M
R
The thi
r
d m
e
thod c
o
nsiders
the FPGA at a
low a
b
str
act
i
on l
e
vel
,
as a
m
a
t
r
i
x
of
basi
c pr
ocessi
ng
el
em
ent
s
(C
LB
s – C
o
nfi
g
u
r
abl
e
L
ogi
c B
l
ock
)
l
i
nke
d
b
y
swi
t
c
hed i
n
t
e
rco
nnect
i
n
g
bus
es. T
h
e s
p
eci
fi
c
characte
r
istics of t
h
e a
p
plication
syste
m
m
a
ppe
d
onto
t
h
e FPGA are
not tak
e
n
i
n
to acco
un
t.
Detectio
n is
p
e
rf
or
m
e
d
b
y
mean
s o
f
conven
tio
n
a
l techn
i
q
u
e
s [
1
1
]
.
W
h
en
an
err
o
r
is d
e
tected
, th
e fau
lty FPG
A
b
l
o
c
k
is
identified, remove
d from
the
active com
putation and re
pl
aced by s
p
are
ele
m
ents in orde
r to
prese
r
ve the
n
o
m
in
al d
e
tectio
n
ab
ility as lo
ng
as
p
o
ssib
le. To
th
is en
d, th
e i
n
terconn
ectio
n
stru
cture is pro
p
e
rly
r
econ
f
i
g
ur
ed
by u
s
ing
on
e
of
th
e m
a
n
y
r
e
co
nf
igu
r
a
tion
tech
n
i
qu
es fo
r
regu
la
r a
rray
architectures. The
in
terconn
ection
s
an
d th
e con
f
ig
uratio
n m
e
mo
ry are
u
s
u
a
lly
conside
r
ed fa
ult free
.
T
h
e main drawbac
k
s
of t
h
i
s
app
r
oach are
due t
o
t
h
e
har
d
wa
re re
du
n
d
a
n
cy
neede
d
t
o
sup
p
o
r
t
det
e
c
t
i
on (i
n
part
i
c
ul
ar, i
f
chec
ki
ng i
s
per
f
o
r
m
e
d at
low
gra
n
ul
ari
t
y
) an
d t
o
t
h
e
fa
ct
t
h
at
reco
nfi
g
u
r
at
i
o
n m
a
y
be ham
p
ere
d
by
l
ack o
f
su
f
f
i
c
i
e
nt
red
u
nda
nt
pat
h
s.
A
fo
ur
th
ap
proach
adop
ts a h
i
g
h
-
l
evel vie
w
of the system
.
Fault de
tectio
n tech
n
i
qu
es are in
trod
u
ced
at ap
p
lication
syste
m
lev
e
l. Ch
eck
i
n
g is execu
ted
b
y
an
al
yzin
g
th
e in
termed
iate o
r
final ap
p
lication
o
u
t
p
u
t
s,
according to t
h
e adopted
detection t
echnique. T
h
ere is
no relationshi
p
betwee
n the location of the c
h
ecki
n
g
ope
rat
i
o
n an
d t
h
e array
st
r
u
ct
ure
of t
h
e
un
de
rl
y
i
ng FP
G
A
device.
Whe
n
ever an error
is detected, a diagnostic
p
h
a
se m
u
st b
e
in
trodu
ced
i
n
o
r
d
e
r t
o
lo
cat
e th
e fau
lty C
L
B [9
]. Reco
nfigu
r
ation
is th
en
acco
m
p
lish
e
d
b
y
excluding s
u
c
h
elem
ent from
the active
com
putation
t
h
r
o
ug
h i
n
t
e
rco
nnect
i
o
n
rec
o
nfi
g
u
r
at
i
o
n
an
d s
p
are
activ
atio
n
.
In
t
h
is ap
proach, circu
it co
m
p
lex
i
ty an
d p
e
rfo
r
m
a
n
ce l
o
ss are
red
u
c
ed with resp
ect to th
e prev
iou
s
case; howe
v
er, the separate diagnostic phas
e
leads to l
ong
er repai
r
t
i
m
e
,
si
nce ap
pr
op
ri
at
e t
e
st
i
ng need t
o
b
e
ex
ecu
ted
(
obvio
u
s
ly,
r
e
co
nfig
ur
atio
n is
no
t “tr
a
n
s
p
a
r
e
nt” as f
a
r
as ti
m
e
is co
ncer
n
e
d
)
.
H
e
r
e
also
,
recon
f
i
g
uration
m
a
y in
cu
r in
lack
of suffi
cien
t rou
tin
g
path
s, alth
oug
h th
is case is l
e
ss lik
ely th
an
in
th
e
pre
v
i
o
us a
p
pr
o
ach si
nce re
r
o
u
t
i
ng m
u
st
be c
o
m
p
l
e
t
e
l
y
recom
put
ed.
The fi
fth a
p
proach a
u
gm
ents the
physical structure
of the FPGA
de
v
i
ce to
d
i
rectly su
ppo
rt fau
lt
det
ect
i
on a
n
d
con
f
i
n
em
ent
[
10]
.
The
basi
c
C
L
B
s
an
d i
n
t
e
rco
nnect
i
o
ns
are m
odi
fi
ed
so t
h
at
det
ect
i
on i
s
p
e
rform
e
d
b
y
i
n
tern
al ch
eck in
ev
ery CLB
.
Th
is so
lu
tio
n i
s
hi
ghly e
ffective a
n
d efficient, but re
quires
large
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
089
-48
64
IJR
E
S V
o
l
.
3, No
. 2,
J
u
l
y
20
1
4
:
3
9
– 48
42
ci
rcui
t
com
p
l
e
xi
t
y
. The fi
r
s
t
t
w
o m
e
t
hods
m
e
nt
i
oned a
b
o
v
e are
use
d
he
re f
o
r t
h
e c
o
m
p
ari
s
on
wi
t
h
t
h
e ne
w
app
r
oach
an
d t
h
e
fu
nct
i
o
nal
d
i
agram
s
of t
h
o
s
e m
e
t
hods a
r
e
gi
ve
n i
n
fi
g
u
re
2
(a)
an
d
(
b
).
4.
PROP
OSE
D
SELF
REPAIR METHOD
Reco
nfigu
r
ab
l
e
Syste
m
s b
y
mean
s o
f
recon
f
i
g
ura
tio
n
con
s
ists in
p
a
rtiti
o
n
i
n
g
t
h
e FPGA arch
itectu
r
e
in
to
g
r
ou
ps o
f
FPGA
r
e
so
ur
ces
(
called
tiles
)
on
w
h
i
c
h
po
r
t
i
ons
o
f
t
h
e
c
o
m
put
at
i
on are
m
a
pped
.
M
o
st
of
t
h
e
tiles are u
s
ed
to
im
p
l
e
m
en
t
fun
c
tion
a
l b
l
ock
s
o
f
th
e
d
e
sired
co
m
p
u
t
atio
n. More
fun
c
tio
n
a
l un
its can
b
e
map
p
e
d
i
n
th
e
sam
e
tile. So
me tiles (th
e
sp
are tiles
) are left unused s
o
that they
can be
expl
oi
t
e
d t
o
re
pl
ace
th
e fau
lty tiles in
recon
f
iguratio
n
t
o
allow t
h
e syste
m
su
rv
iv
al as sho
w
n
i
n
figu
re
3
.
Fig
u
re 3
.
Tiles in
th
e FPGA
Arch
itecture
In this approa
ch the system
is partitioned in to
various
m
odules for the ease of dy
nam
i
c partial
recon
f
i
g
uration
.
Th
e p
a
rtitio
n
was
do
n
e
in a way th
at
t
h
e system
u
ndergo
e
s a m
o
de ch
an
ge
with b
a
sic
fun
c
tion
a
lity wh
en
a
fau
lt is detected
. Th
e
fun
c
tio
n
a
lity will b
e
in
creased
fu
rt
h
e
r
b
y
recon
f
i
g
uratio
n
o
f
m
o
re
m
odul
es aft
e
r
i
g
n
o
r
i
n
g t
h
e
fa
u
l
t
y
t
i
l
e
. The
o
v
e
ral
l
schem
e
i
s
p
r
esent
e
d
usi
n
g t
h
e
fl
owc
h
art
i
n
fi
g
u
re
4.
To
detect the fault, an
onli
n
e
BIST m
e
thod i
s
use
d
he
re. T
h
e on-line testing is
base
d on
partitioni
ng
th
e d
i
g
ital syste
m
in
to
tiles
an
d
u
s
ing
d
i
stribu
ted
ch
eck
e
rs in
th
e tiles
to
p
r
ov
id
e the fau
lt lo
catio
n
b
y
id
en
tifying
th
e ch
eck
e
r
b
y
wh
ich
t
h
e error i
s
d
e
tected
as
sh
own
in
figu
re 5
.
Each
tile is co
m
p
o
s
ed
of a set o
f
physical res
ources (CLBs
and interc
onnect), a
n
interf
ace sp
ecification
,
wh
ich
d
e
no
tes th
e co
nn
ectiv
ity to
neighboring tiles, and a
net list. The
tiles of sm
all sizes help to re
duce the am
ount
of c
o
nfi
g
uration m
e
m
o
r
y
by
re
duci
n
g t
h
e si
ze
of
t
h
e
com
pone
nt
t
h
at
i
s
rec
o
nfi
g
u
r
e
d
.
Al
l
p
o
s
s
i
b
l
e
co
nfi
g
u
r
at
i
ons
of
t
h
e t
i
l
e
s are
g
e
n
e
rated
off-lin
e. Upon
d
e
tectin
g
an
erro
r
fro
m
a certain
tile, th
e fau
lty tile o
n
l
y n
e
ed to
b
e
d
i
agn
o
s
ed
t
o
lo
cate th
e fau
lty CLB, wh
ich
will b
e
o
u
t
o
f
u
s
i
n
g
in
th
e o
r
ig
in
al config
uration
o
r
as a sp
are elem
e
n
t. The
fau
lty tile lo
cated
b
y
th
e d
i
agn
o
s
is pro
cedu
r
e is th
en
circum
v
e
n
t
ed
b
y
a
n
e
w configu
r
at
io
n
do
wn
lo
ad
ed
fro
m
an e
x
ternal m
e
m
o
ry. This is
pos
sible
beca
use som
e
of
the
CLB’s a
r
e
us
ed as
s
p
ar
es
for the
rest. Since the
rou
ting
area
rep
r
esen
t th
e m
a
j
o
rity o
f
th
e FPGA ch
i
p
,
the
need
for a
de
tection an
d
di
agn
o
si
s a
p
p
r
oa
ch o
f
interconnections extrem
ely
high. T
h
is pa
per
uses an
online approac
h
which re
duces the detection a
n
d
di
ag
no
si
s t
i
m
e
.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
RES
I
S
SN
:
208
8-8
7
0
8
FPGA
Eval
u
a
t
i
on
of
Rec
o
nf
i
g
ura
b
l
e
M
o
dul
e
s
w
i
t
h
F
aul
t
D
e
t
ect
i
on
an
d R
e
pai
r
Tec
hni
qu
e
(
P
radee
p
C
)
43
Fi
gu
re
4.
Fl
o
w
Di
ag
ram
for
f
a
ul
t
det
ect
i
o
n a
n
d
re
pai
r
m
ech
ani
s
m
Whe
n
a
fa
ul
t
i
s
det
ect
ed
, t
h
e
s
y
st
em
unde
rg
o
e
s a m
ode c
h
a
nge
i
m
m
e
di
at
el
y
.
The sy
st
em
i
s
desi
gne
d
in a way that it
will function
accord
ing to la
st com
p
leted operation and
by providi
ng
ne
cessary control signal
to
th
e p
e
riph
erals. In
th
is cond
itio
n
system i
s
n
o
t
ab
le
to
do
an
y o
t
h
e
r pro
cessing
. So
fau
lt id
en
tificatio
n
an
d
rep
a
ir was don
e wit
h
less
co
nfigu
r
ation
ti
m
e
. In
th
e
p
r
op
o
s
ed
app
r
o
ach th
e syst
e
m
s th
at are
to
b
e
i
m
p
l
e
m
en
ted
in
th
e FPGA is
p
a
rtitio
n
e
d
in
t
o
self ch
eck
i
n
g tile sh
o
w
n
in
fig
u
re 5
.
Th
e
fau
lt in
d
i
cating
sig
n
a
l
from
each tile is taken as t
h
e
observa
b
le
points and
fo
r a
m
u
l
tiple out
put circuits m
a
ny sub ci
rcuits c
a
n
be
p
a
rtitio
n
e
d
.
Fi
gu
re 5.
The
pr
o
pose
d
FP
G
A
Ti
l
e
Th
e n
e
w app
r
o
ach
h
a
s two
p
h
a
ses on
e is to
id
en
tify th
e
fau
lty tile u
s
in
g
th
e n
e
w m
e
t
h
od
and
th
e
secon
d
is to
u
s
e an
y ex
istin
g
BIST m
e
th
o
d
to
id
en
tify
fau
lty in
terconn
ect. Th
e
en
tire ci
rcu
it lev
e
l is
d
i
v
i
d
i
ng
in
to
su
b circu
it lev
e
l un
til it beco
m
e
s two
lev
e
ls. Th
en
th
e
su
b circu
its are d
i
v
i
d
e
in
t
o
sel
f
check
i
n
g tiles u
s
ing
t
h
e cone se
gm
ent
m
e
t
hod [
1
1-
1
2
]
wi
t
h
cert
a
i
n
err
o
r
det
ect
i
on an
d co
rrec
t
i
ng co
des. T
h
en t
h
e fa
ul
t
i
ndi
cat
o
r
out
put
of sel
f
c
h
ecki
ng tiles are give
n to t
h
e
com
p
lete
checker. So whe
n
c
o
m
p
lete
checker circuit recei
ve any
fau
lt in
d
i
cation
it can
easily lo
cate th
e fau
lty tile. In
th
e n
e
x
t
ph
ase u
s
es on
lin
e
BIST b
a
sed
diag
no
sis
m
e
t
hods
[
13]
t
o
i
d
e
n
t
i
f
y
t
h
e
f
a
ul
t
y
reso
u
r
ces
.
The fa
ul
t
reco
very
p
r
oces
s i
s
based o
n
t
h
e t
y
pe of faul
t
occur
r
ed a
n
d sepa
rat
e
al
gori
t
h
m
s
for
p
e
rm
an
en
t fau
l
t an
d
tran
sien
t fau
lts are
u
s
ed
.
Algo
rith
m
u
s
ed
in
t
h
is appro
a
ch
for p
e
rman
en
t
fau
lt repair is
g
i
v
e
n
in
Algorith
m
1
.
After fau
lt id
en
tificatio
n
av
aila
b
ility o
f
sp
are tile was ch
eck
e
d
and
fau
lty tile is
replace
d by s
p
are tile if it
available. Als
o
a m
odul
e re
arra
ngem
e
nt proce
d
ure
was
introduced t
o
reduce
ro
ut
i
n
g com
p
l
e
xi
t
y
(R
C
)
. S
y
st
em
under
g
oes a m
odul
e
rear
ran
g
em
ent
ot
her
w
i
s
e b
y
i
gno
ri
n
g
t
h
e l
east
im
port
a
nt
(R
e)
f
unct
i
o
nal
m
odul
e
fr
om
t
h
e s
y
st
em
i
f
spare i
s
n
o
t
a
v
ai
l
a
bl
e.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
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:
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64
IJR
E
S V
o
l
.
3, No
. 2,
J
u
l
y
20
1
4
:
3
9
– 48
44
Al
go
ri
t
h
m
1:
Sel
f
R
e
pai
r
Al
go
ri
t
h
m
.
1.
Do Self Testing
o
f
Tiles
2.
If (fa
ul
t
=
1
)
go
t
o
st
an
d
al
one
m
ode
3.
Id
en
tify th
e
fau
lty Tile.
4.
Ch
eck fo
r th
e
Sp
are
Av
ailab
i
lity
5.
If C
o
rres
ponding section s
p
are available t
h
e
n
6.
Go
T
o
Fu
ll Mo
du
le Rea
r
rang
emen
t
.
7.
IF
fa
ulty Tile <=
High
RC Tile
8.
S
p
a
r
e Tile
= Faulty Tile
9.
Else
10
.
Do rea
rra
ngem
ent to ha
ve
Less RC
11
.
End
12
.
Else
13
.
Go to
Part
i
a
l
Mo
dul
e
Re
arr
a
nge
me
nt
14
.
If
fa
ulty Tile Module = L
o
w
e
st Re
15
.
I
g
nore
it
16
.
Else
17
.
I
g
nore
the
lowest Re m
o
dule
18
.
do rea
rra
ngem
e
nt
19
.
End
20
.
End
21
.
Else
22
.
G
o
t
o
ste
p
1
23
.
End
5.
E
X
PERI
MEN
T
AL SETUP
The a
b
ove
m
e
nt
i
one
d
fa
ul
t
d
e
t
ect
i
on a
n
d
re
pai
r
ap
p
r
oac
h
i
s
eval
uat
e
d
b
y
desi
g
n
i
n
g
a
sy
st
em
cor
e
wi
t
h
st
an
d al
o
n
e m
odul
e a
n
d
fo
u
r
ad
d
o
n
m
o
d
u
l
e
s.
The
sy
st
em
i
s
desi
gn
ed i
n
way
t
h
at
i
t
can w
o
r
k
wi
t
h
any
ad
d on
m
o
du
les with
b
a
sic
fun
c
tio
n
a
lity ie
wh
en
a fau
lt
is d
e
tected
system
wil
l
b
e
d
y
n
a
micall
y
reco
nfi
g
ured
t
o
i
t
s
basi
c
m
ode
. A
dd
o
n
m
odul
es desi
g
n
ed
fo
r t
h
e ev
al
uat
i
on are a
do
u
b
l
e
preci
si
on
fl
oat
i
n
g p
o
i
nt
uni
t
,
in
teg
e
r ALU
cap
ab
le of
d
o
in
g
add
itio
n op
eration
on
ly, SDR
A
M co
ntro
ller and
an asyn
ch
ro
nou
s serial
comm
unication inte
rface
(UART). Eac
h
module is c
o
ded
in
Verilog
HDL a
n
d sim
u
la
ted se
parately by usi
ng
Xilin
x
ISE
simu
lato
r.
The regular synthesis flow ge
nerates
a single
b
it stream
for pro
g
rammin
g
th
e FPGA. This co
nsid
ers
th
e d
e
v
i
ce as
a sin
g
l
e ato
m
ic en
tity. In
con
t
rast, t
h
e Partial Reco
n
f
iguratio
n
flow
p
hysically d
i
v
i
d
e
s th
e
devi
ce i
n
re
gi
ons
. O
n
e re
gi
on i
s
cal
l
e
d t
h
e “st
a
t
i
c
regi
on”
, w
h
i
c
h i
s
t
h
e port
i
o
n o
f
t
h
e devi
ce t
h
at
i
s
pr
o
g
ram
m
ed at
st
art
up a
nd
neve
r c
h
an
ges
.
O
n
e re
gi
o
n
i
s
t
h
e “dy
n
am
ic regi
on” al
s
o
kn
o
w
n as “t
h
e
PR
reg
i
o
n
”
,
wh
ich is th
e po
rtion
o
f
th
e
d
e
v
i
ce t
h
at will
b
e
reco
nfigu
r
ed d
y
na
m
i
call
y
, p
o
t
en
tially
m
u
ltip
l
e
ti
m
e
s
an
d
with
d
i
fferen
t d
e
sign
s. It
is p
o
ssib
l
e to
hav
e
m
u
lt
ip
le PR reg
i
on
s, bu
t we will co
n
s
ider o
n
l
y th
e simp
lest
case he
re [
1
4]
The PR
fl
o
w
g
e
nerat
e
s at
l
e
a
s
t
t
w
o
bi
t
st
rea
m
s, one f
o
r t
h
e st
at
i
c
and
on
e fo
r t
h
e
PR
re
gi
o
n
.
Most likely, there will be
m
u
ltiple PR bit st
ream
s, one for each desi
gn t
h
at can be
dyna
m
i
call
y
loaded. The
PR
regi
o
n
i
s
a phy
si
cal
ent
i
t
y
,
wi
t
h
a gi
ven ge
om
et
ry
. PlanA
h
ea
d i
s
t
h
e t
ool
t
h
at
al
l
o
ws y
ou t
o
de
fi
ne t
h
e
exact
l
o
cat
i
o
n
of
t
h
e
PR
re
gi
o
n
on
y
o
u
r
t
a
rge
t
devi
ce
[
14]
.
The
Vi
rt
e
x
5
LXT M
L
5
0
5
i
s
a
gene
ral
pu
rp
ose
FP
GA
d
e
vel
o
pm
ent
bo
ard
ena
b
l
e
s
de
si
gne
rs t
o
i
nvest
i
g
at
e a
n
d e
xpe
ri
m
e
nt
wi
t
h
feat
ure
s
of
t
h
e
Vi
rt
ex
-
5
L
X
T.
P
r
o
v
i
d
es
feat
u
r
e-
ri
ch
gene
ral
pu
r
pos
e
eval
uat
i
o
n a
n
d
de
vel
o
pm
ent
pl
at
fo
rm
. In
cl
udes
o
n
-
b
o
a
r
d
m
e
m
o
ry
and
i
n
d
u
st
ry
s
t
anda
rd
co
n
n
e
c
t
i
v
i
t
y
interfaces. Delivers
a versatile
de
velopm
ent
platform
for e
m
bedded
a
p
plications [15].
Th
e Virtex
5
FPGA is o
n
e
o
f
th
e latest an
d
wid
e
ly u
s
ed
FPGA for partial reco
nfigu
r
ation
.
Th
e
fam
i
l
y
of Vi
rt
e
x
5
FP
GA
has
adva
nce
d
feat
u
r
es l
i
k
e
ASMB
colum
n
base
d architecture.
The
fam
i
ly has five
di
ffe
re
nt
su
b-
f
a
m
i
li
es [16]
.
Each s
ub f
a
m
i
l
y
has vari
et
y
of fe
at
ure
s
nee
d
ed
fo
r m
oder
n
l
ogi
c
desi
g
n
s
. Few
applications of Virtex
5 FPGA’s a
r
e Reconfigura
b
le
Proc
essors,
Soft process
o
rs
a
n
d DSP process
o
rs
etc.
Virtex 5 FPGA is no
w used as an
altern
ativ
e
to
AIC
d
e
sign
an
d it is bu
ilt on
6
5
n
m
tech
no
log
y
.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
RES
I
S
SN
:
208
8-8
7
0
8
FPGA
Eval
u
a
t
i
on
of
Rec
o
nf
i
g
ura
b
l
e
M
o
dul
e
s
w
i
t
h
F
aul
t
D
e
t
ect
i
on
an
d R
e
pai
r
Tec
hni
qu
e
(
P
radee
p
C
)
45
Fig
u
re
7
.
Exp
e
rim
e
n
t
al setu
p
for
o
n
a
Xilin
x XUPV5 ev
al
uatio
n
b
o
a
rd
6.
RESULTS
A
N
D
DI
SC
US
S
I
ONS
For t
h
e e
v
al
uat
i
on o
f
ab
ove
m
e
nt
i
oned al
g
o
ri
t
h
m
t
h
e sy
stem
was im
pl
em
ent
e
d on a X
i
l
i
nx XU
PV
5
ev
alu
a
tion
bo
ard
with
a Virt
ex
-5
LX11
0. Xilin
x
Paln
ah
ead
with
Partial
reco
nf
iguration
cap
ab
ility w
a
s th
e
d
e
v
e
l
o
p
m
en
t t
o
o
l
u
s
ed
. Th
e p
a
rtitio
n
e
d
syste
m
is co
d
e
d
in
Verilog
HDL an
d
sim
u
late
d
u
s
ing
appropriate test
b
e
n
c
h
e
s fo
r v
e
rifyin
g th
e
fu
nctio
n
a
lity.
The sy
st
em
i
s
desi
g
n
e
d
i
n
a way
t
h
at
i
t
can funct
i
o
n i
n
va
ri
o
u
s m
ode i
.
e. st
and al
one m
ode
, st
an
d
al
one m
ode wi
t
h
on
e ad
d o
n
m
odul
e, st
and
al
one m
ode wi
t
h
t
w
o a
dd
on
m
odul
es, st
a
n
d al
o
n
e m
ode wi
t
h
th
ree add
on
m
o
du
les, and
with
fu
ll fun
c
tio
nality
m
o
d
e
s. All th
e abo
v
e
mo
du
les are syn
t
h
e
sized u
s
i
n
g
Xilin
x
XST
14
.2
u
nder v
a
riou
s m
e
t
h
od
s t
o
o
b
t
ain th
e resou
r
ce
u
tilizatio
n
.
The resu
lt o
f
th
is is g
i
v
e
n
i
n
follo
wing
sect
i
ons.
Fi
gu
re 8.
Si
m
u
l
a
t
i
on
res
u
l
t
s
f
o
r
d
o
ubl
e preci
si
on
fl
oat
i
n
g p
o
i
n
t
uni
t
Si
m
u
latio
n
resu
lt o
f
flo
a
ting p
o
i
n
t
un
it u
s
i
n
g
Xilin
x
ISE si
m
u
lato
r is s
h
own
in
figu
re 8
.
For th
e
desi
g
n
IEE
E
7
54
do
u
b
l
e
prec
i
s
i
on fl
oat
i
n
g
poi
nt
st
anda
rd
use
d
. The m
a
nt
i
ssa i
s
52 bi
t
lon
g
an
d re
pres
ent
e
d
by
bi
t
s
51
-0
. If
t
h
e exp
one
nt
f
i
el
d i
s
great
er t
h
an ‘
0
’
a lead
in
g
‘1’ is also
i
n
clud
ed
with
th
e m
a
n
tissa. 1
1
b
its
are use
d
t
o
rep
r
esent
ex
p
one
n
t
part
and B
i
t
fi
el
d i
s
62-5
2
.
T
h
e act
ual
val
u
e
of ex
po
ne
nt
i
s
cal
cul
a
t
e
d by
2^
(e-
1
024
) th
e
v
a
lue r
e
p
r
esen
ted by 1
1
b
it
f
i
eld
is of
f
s
et
b
y
1
024.
Synthesis Res
u
lts of va
rious
m
e
thods
using Xilinx XST
tool
is
give
n
in
Tables 1-4. T
o
find t
h
e area
ove
r
h
ead
f
o
r t
h
e sel
f
re
pai
r
i
n
g
schem
e
s Sy
nt
hesi
s o
f
t
h
e
sy
st
em
wi
t
hout
i
n
t
r
o
d
u
ci
n
g
any
s
e
l
f
re
pai
r
c
onc
ept
i
s
ev
alu
a
ted
.
The u
tilizatio
n
sh
own
in
tab
l
e 1
d
ep
end
s
o
n
th
e
fun
c
tion
a
lity i
n
tro
d
u
c
ed
in
the d
e
sign
and
the typ
e
of t
h
e c
o
di
n
g
st
y
l
e. Any
way
t
h
e sam
e
desi
gn i
s
use
d
for al
l the three eval
uations
so t
h
e
desi
g
n
m
e
t
hod
and
style o
f
co
d
i
n
g
do
es
no
t in
fl
uen
ce th
e co
m
p
arison
resu
lts.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
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-48
64
IJR
E
S V
o
l
.
3, No
. 2,
J
u
l
y
20
1
4
:
3
9
– 48
46
Tabl
e1
. Sy
nt
he
si
s res
u
l
t
s
f
o
r
S
y
st
em
wi
t
hout
Faul
t
Det
ect
i
o
n a
n
d
R
e
pai
r
M
e
t
h
o
d
W
ithout Fault Detection and Repair
M
e
thod
T
ile No.
M
odule Nam
e
N
u
m
b
er
of S
l
i
c
e
Registers
N
u
m
b
er
of S
l
i
c
e
LUT's
Nu
m
b
e
r
used as
L
ogic
Nu
m
b
er
of fully
used L
U
T-
FF
pair
s
1
Floating Point Unit
4408
6116
6115
3908
2 I
n
teger
Unit
181
181
3 SDRAM
Contr
o
ller
78
168
168
78
4 UART
95
129
128
84
T
O
T
A
L
4581
6594
6592
4070
To pe
rf
o
r
m
t
h
e sy
nt
hesi
s o
f
TM
R
,
al
l
t
h
e fo
ur a
d
d o
n
m
odul
es were
sy
nt
hesi
zed s
e
parat
e
l
y
by
rep
licatin
g it th
ree tim
es an
d in
trodu
cing
a
fun
c
tion
fo
r
maj
o
rity v
o
t
i
n
g.
After th
e TMR
vo
ter
d
e
term
i
n
es th
e
m
a
jori
t
y
o
u
t
p
u
t
val
u
e
,
i
t
se
nd
s t
h
e c
o
rrect
i
n
fo
rm
ati
on
bac
k
t
o
t
h
e t
h
ree a
c
t
i
v
e m
odul
es.
The
TM
R
v
o
t
e
r a
nd
repair circ
uit contains the nec
e
ssary logic for the switc
hi
ng of which thre
e
m
odules are
active in addition t
o
reset
an
d
rei
n
i
t
i
a
l
i
ze any
of
t
h
e m
odul
es.
The sy
nt
hesi
s
res
u
l
t
s
sh
o
w
n i
n
Tabl
es
cl
earl
y
sh
ows
t
h
at
t
h
e
utilization is also three tim
e
s
higher t
h
an tha
t
of a system
w
ithout self
re
pa
ir feature. T
h
ere was no a
dditional
h
a
rdware
d
e
si
gn
ed fo
r th
e
fau
lt d
e
tectio
n.
Tab
l
e
2
.
Syn
t
hesis r
e
su
lts fo
r
Syste
m
Tr
ip
le
Mo
du
lar
Redun
d
a
n
c
y Method
T
M
R M
e
thod
T
ile No.
M
odule Nam
e
N
u
m
b
er
of S
l
i
c
e
Registers
N
u
m
b
er
of S
l
i
c
e
LUT's
Nu
m
b
e
r
used as
L
ogic
Nu
m
b
er
of fully
used
LUT
-
FF pairs
1
Floating Point Unit
1328
9
1842
1
1841
8
1178
1
2 I
n
teger
Unit
616
616
3 SDRAM
Contr
o
ller
299
577
577
291
4 UART
350
460
457
309
T
O
T
A
L 1393
8
2007
4
2006
8
1238
1
Tab
l
e
3
.
Syn
t
hesis r
e
su
lts fo
r
D
oub
le Modu
lar
Redun
d
a
n
c
y
Meth
od
DM
R M
e
thod
T
ile No.
M
odule Nam
e
N
u
m
b
er
of S
l
i
c
e
Registers
N
u
m
b
er
of S
l
i
c
e
LUT's
Nu
m
b
e
r
used as
L
ogic
Nu
m
b
er
of fully
used
LUT
-
FF pairs
1
Floating Point Unit
8861
1228
5
1228
3
7873
2 I
n
teger
Unit
45
415
415
57
3 SDRAM
Contr
o
ller
201
389
389
213
4 UART
235
311
309
225
T
O
T
A
L 9342
1340
0
1339
6
8368
Tabl
e 4. Sy
nt
h
e
si
s
res
u
l
t
s
f
o
r
New
A
p
pr
oac
h
New Approach
T
ile No.
M
odule Nam
e
N
u
m
b
er
of S
l
i
c
e
Registers
N
u
m
b
er
of S
l
i
c
e
LUT's
Nu
m
b
e
r
used as
L
ogic
Nu
m
b
e
r
of fully
u
s
ed
LUT-F
F
p
a
irs
1
Floating Point Unit
4408
6116
6115
3908
2 I
n
teger
Unit
181
181
0
3 SDRAM
Contr
o
ller
78
168
168
78
4 UART
95
129
128
84
5 Spar
e
T
i
le
4408
6116
6115
3908
T
O
T
A
L 8989
1271
0
1270
7
7978
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
RES
I
S
SN
:
208
8-8
7
0
8
FPGA
Eval
u
a
t
i
on
of
Rec
o
nf
i
g
ura
b
l
e
M
o
dul
e
s
w
i
t
h
F
aul
t
D
e
t
ect
i
on
an
d R
e
pai
r
Tec
hni
qu
e
(
P
radee
p
C
)
47
Fin
a
lly all
reco
urse u
tilizatio
n
o
f
th
e
n
e
w ap
pro
ach
was co
m
p
ared
with
th
e resou
r
ce u
tilizatio
n
o
f
TM
R
and
DM
R
m
e
t
hod. Fi
g
u
re
9 s
h
o
w
s t
h
e com
p
ari
s
on
and i
t
has
bee
n
cl
earl
y
o
b
ser
v
ed
fr
om
t
h
e di
agram
t
h
at
t
h
e
new
a
p
pr
oac
h
i
s
havi
n
g
l
e
ss a
r
ea
o
v
e
r
hea
d
t
h
an
t
h
e
TM
R
an
d
DM
R
m
e
t
hods
.
Fig
u
re
9
.
Co
mp
ariso
n
of Reco
ur
se Utilizati
o
n
of Vari
o
u
s Meth
od
s
7.
CO
NCL
USI
O
N
AN
D F
U
T
U
RE W
O
R
K
Thi
s
pape
r pre
s
ent
e
d
t
h
e
e
v
a
l
uat
i
on o
f
a fa
ul
t
de
tection
an
d rep
a
ir al
gorith
m
fo
r Reco
nfigu
r
ab
le
Syste
m
s. In th
i
s
app
r
o
a
ch
effectiv
e
u
tilizatio
n
o
f
FPGA reso
urce
b
y
m
ean
s
of Partial Reco
nfigu
r
ation is u
s
ed.
The
FP
GA is
partitione
d i
n
t
o
vari
ous tiles
whe
r
e t
h
e sy
st
em
m
odules
are im
plem
ented. T
h
e c
o
m
p
arison
of
FPGA rec
o
urs
e
s utilization shows that
this approach
has less area ove
r head
than the
other m
e
thods. S
o
this
m
e
thod is
very useful in re
al-t
im
e em
bedded system
s and l
o
ng life
m
i
ssion critical applications
. The
effi
ci
ency
of t
h
i
s
m
e
t
hod i
s
l
i
m
i
t
e
d by
t
h
e
s
t
ruct
u
r
e
of
dy
n
a
m
i
cal
ly
recon
f
i
g
ura
b
l
e
FP
G
A
. T
h
ese m
e
t
hod
al
so
h
a
s th
e
d
e
si
g
n
co
m
p
lex
ity o
f
p
a
rtitio
n
i
n
g
t
h
e system
as a
stan
d
a
l
o
n
e
m
o
du
le and
add o
n
m
o
du
les.
In
th
is
approach the occurr
ence
of only one fa
ult is evaluated. T
h
e correct
ness o
f
this repair alg
o
rithm
for m
o
re fault
can be eval
uat
e
d by
con
s
i
d
e
r
i
ng an
ot
he
r sy
st
em
wi
t
h
m
o
re add o
n
m
odu
l
e
s and by
di
vi
di
n
g
t
h
e FPG
A i
n
t
o
m
o
re num
ber
o
f
Ti
l
e
s.
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NC
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5000
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