Intern
ati
o
n
a
l
Journ
a
l of
Re
con
f
igur
able
and Embe
dded
Sys
t
ems
(I
JRES)
V
o
l.
3, N
o
. 3
,
N
o
v
e
m
b
er
2
014
, pp
. 85
~97
I
S
SN
: 208
9-4
8
6
4
85
Jo
urn
a
l
h
o
me
pa
ge
: h
ttp
://iaesjo
u
r
na
l.com/
o
n
lin
e/ind
e
x.ph
p
/
IJRES
Design and Implementation of
an Ethern
et
MAC I
P
Core f
o
r
Embedded Applications
Kau
t
ilya Sin
g
h P
a
rmar
*
,
S
a
nke
t
Dess
ai*,
S.G
.
S
h
i
v
a Pr
asa
d
Ya
da
v
*
*
,
A
t
ul
Ch
auh
a
n*
**
**Departm
ent
of
Com
puter S
c
i
e
n
ce
a
nd Engineering,
Facu
lty
of
Engineer
ing an
d
Techno
log
y
, M.S. Ramaiah
School of Adv
a
n
ced Stud
ies, Ban
g
alore India
** Departm
e
n
t
o
f
Telecom
m
unication
Engin
eer
in
g, M.S.
Ram
a
i
a
h
Institut
e
of
T
e
chnolog
y
,
B
a
ngal
o
re,
India
***Hardware En
gineer
,
NVIDIA Gr
aphics Co
.Bangalore, Ind
i
a
Article Info
A
B
STRAC
T
Article histo
r
y:
Received
May 11, 2014
Rev
i
sed
Sep
20
, 20
14
Accepted Oct 12, 2014
An IP (intellectual property
)
co
re is a block of
logic or data that is used in
making a field
programmable gate
arra
y
(FPGA) or application-specific
integr
ated
cir
c
uit (ASIC) for a pr
oduct.
As essential elements of
design reuse,
IP cores are part
of the growing electronic d
e
sign automation (ED
A
) industr
y
trend towards repeated use of previ
ously
d
e
signed components. Ethern
et
continu
e
s to be one of the most
popular LAN technolog
ies.
Due to the
robustness result
ing from
its wid
e
a
ccep
tan
ce
and
deplo
y
m
e
nt
, th
e
r
e has b
een
an att
e
m
p
t to
build Eth
e
rn
et-bas
ed r
eal
-ti
m
e
control ne
tworks
for
manufacturing
automation. Th
er
e is a growing demand for low cost, power
efficient MAC I
P
Core for vario
u
s embe
dded ap
plications. In
this paper a
project is discussed to design an Ethe
rnet MAC IP Core
solution for such
embedded applications. The pro
pos
ed 10_100_1000 Mbps tri-mode Ethern
et
MAC implements a MAC contro
ller
c
onforming to IEEE 802.3
specif
i
cation
.
It is d
e
signed
to
use less than 2
000 LC
s/LEs
to
implement fu
ll
function
.
I
t
will use
infe
rre
d RAMs and PADs to reduc
e
techno
log
y
dep
e
ndence
.
To
increase the flex
ibility
, thr
ee optional
modules can be added to
or removed
from
the pro
j
ec
t. A GUI
confi
guration
int
e
rfa
ce,
cr
ea
ted b
y
Tcl/
tk scr
i
p
t
languag
e
,
is con
v
enien
t
for conf
igur
ing option
a
l modules, FIFO depth an
d
verification par
a
meters.
Furthermore, a verifica
tion s
y
stem was designed
with T
c
l/
tk us
er in
terf
ace
, b
y
whi
c
h
the
stim
ulus can
be
gener
a
t
e
d
automatically
an
d the output packets ca
n b
e
v
e
rif
i
ed with CRC-3
2
checksum.
A solution which would consume a smalle
r part
of the targ
eted
F
P
GA, and
thus giving roo
m
for other on-chip periphe
rals
o
r
enabl
e
the us
e
of a s
m
aller
s
i
zed F
P
GA. To
em
plo
y
a
s
m
all
e
r F
P
GA
is desirable since it w
ould redu
ce
power consumption and
dev
i
ce p
r
ice.
Keyword:
ASIC
CRC-3
2
Ethernet MAC
FPGA
LAN
Copyright ©
201
4 Institut
e
o
f
Ad
vanced
Engin
eer
ing and S
c
i
e
nce.
All rights re
se
rve
d
.
Co
rresp
ond
i
ng
Autho
r
:
Sanket De
ssai,
Depa
rt
em
ent
of C
o
m
put
er
En
gi
nee
r
i
n
g, M
.
S
.
R
a
m
a
i
a
h Sch
ool
o
f
Ad
va
nc
ed St
udi
es
,
#470-P, Peeny
a
Industrial
Area, Pee
n
ya 4
th
Ph
ase,
Bang
al
u
r
u
-
56
005
8, Kar
n
atak
a, I
n
d
i
a.
Em
a
il: san
k
e
tdessai@g
m
ail.c
o
m
1.
INTRODUCTION
W
i
t
h
t
h
e o
n
g
o
i
ng ext
e
nsi
o
n
of t
ech
n
o
l
o
gy
,
we are wi
t
n
e
ssi
ng t
h
e em
ergence
of
new
com
put
i
ng
mach
in
es, wh
i
c
h
will b
r
i
n
g
u
s
far b
e
y
o
nd th
e d
e
sk
to
p
PC. Dev
i
ces featu
r
ing
adv
a
nced
conn
ectiv
ity an
d
Internet functi
onality will soon
becom
e
the standard in c
o
m
puting. In fa
ct
, we'
r
e on the verge of a re
vol
ution
th
at will b
r
i
n
g
u
s
a
wav
e
o
f
smart, electro
n
i
c d
e
v
i
ces th
at can
b
e
co
n
t
ro
lled
,
g
a
th
er info
rmatio
n
,
and
d
i
strib
u
t
e
dat
a
vi
a
t
h
e
w
e
b.
Vi
rt
ual
l
y
e
v
ery
em
bed
d
e
d
desi
g
n
er
i
s
l
o
o
k
i
n
g t
o
use
Int
e
r
n
et
, t
o
e
n
hance
o
r
e
x
pa
nd
t
h
e
reach of em
bedde
d
system
s.
This
nee
d
for connecting de
vices
directly into Internet
has lea
d
m
a
ny great
man
u
f
act
u
r
ers to
i
m
p
l
e
m
en
t ASICs
(Applicatio
n
Sp
ecific In
tegrated
Circu
its) or reu
s
ab
le lib
rari
es for
m
i
croco
n
t
r
ol
l
e
rs, sp
eci
al
l
y
desi
gne
d f
o
r t
h
i
s
pu
r
pose
.
As es
sent
i
a
l
el
em
ents of de
si
g
n
reu
s
e, IP co
res ar
e part
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
089
-48
64
IJR
E
S V
o
l
.
3, No
. 3, N
ovem
b
er
2
0
1
4
:
85
– 97
86
of t
h
e g
r
owi
n
g el
ect
ro
ni
c d
e
si
gn aut
o
m
a
t
i
on (
E
D
A
) i
n
d
u
st
ry
t
r
en
d t
o
war
d
s re
peat
e
d
use o
f
p
r
ev
i
ousl
y
desi
g
n
e
d
c
o
m
pone
nt
s.
Et
he
rn
et
cont
i
n
ues
t
o
be
one
o
f
t
h
e
m
o
st
pop
ul
ar
L
A
N
t
ech
nol
ogi
es.
2.
THE IEEE 802
.3
ARCHIT
ECTURE MODEL
The arc
h
itecture of IEEE
80
2.3 corres
p
onds
closely to the two l
o
we
st layers of the OSI/B
R
m
odel as
sh
own
in
Figure 1
.
Th
e Dat
a
Lin
k
layer in
th
e OSI/BR
m
o
d
e
l is p
a
rtitio
n
e
d
in
t
o
three sub
l
ayers
in
th
e
architecture in
order t
o
obtain
m
a
xi
m
u
m
fle
x
ibility within the fam
i
ly of
IEEE 802 sta
ndards. By doi
ng this,
vari
ous m
e
dia access m
e
thods are allowe
d s
i
nce the LLC s
ubl
ayer is the s
a
m
e
for all of t
h
em
. Each sublayer
in the architectural
m
odel provi
des a set of services
that
the nearest im
ple
m
ented highe
r sublayer uses
.
Ser
v
i
ce i
s
t
h
e
gat
h
e
r
i
n
g
nam
e
f
o
r
f
unct
i
on
,
pr
oce
d
u
r
e a
n
d
vari
a
b
l
e
t
h
at
i
s
m
a
de pu
bl
i
c
a
n
d
u
s
ed
by
ot
h
e
r
part
s
of
a sy
st
em
but
t
h
e
part
pr
o
v
i
d
i
ng t
h
em
.
Fi
gu
re
1.
M
a
p
p
i
n
g
of
Tri
a
ngl
e Spa
n
s
[
1
]
A serv
ice is d
e
scrib
e
d
in its
m
o
st
ab
stract fo
rm
b
y
a serv
i
ce primitiv
e. Th
ere are t
w
o gen
e
ric typ
e
s
o
f
p
r
im
it
iv
es, REQUEST and
INDI
CATION. Th
e REQUEST primitiv
e is p
a
ssed
from a h
i
g
h
e
r lay
e
r to
a
lo
wer and
INDIC
A
TION v
i
ce v
e
rsa. Th
e
REQUEST
p
r
i
m
it
iv
e requ
est
s
a serv
ice to
b
e
in
itiated
wh
ile th
e
INDIC
A
TION p
r
im
itiv
e in
dicates an
ev
en
t. Th
e arch
it
ectu
r
e also
d
e
fin
e
s
fiv
e
im
p
o
r
tan
t
co
m
p
atib
ilit
y
interfaces
(MII, GM
II, AUI,
MDI a
n
d, as
s
h
own in fi
gure
1).
All interfa
ces,
but M
D
I,
are
optional a
n
d in this
stu
d
y
, on
ly MII an
d GM
II are of in
terest.When
im
p
l
e
m
en
te
d
i
n
h
a
rdware th
e typ
i
cal so
lutio
n
un
til to
d
a
y has
b
een
t
o
im
p
l
e
m
en
t th
e Ph
ysi
cal layer ex
cept Reco
n
c
iliatio
n
su
b
l
ayer, RS, in
on
e
d
e
v
i
ce,
o
f
ten
referred
t
o
as
a
PH
Y de
vi
ce, a
nd t
h
e Dat
a
Li
nk l
a
y
e
r t
oget
h
er wi
t
h
R
S
i
n
t
o
an
ot
he
r,
oft
e
n re
fer
r
ed t
o
a
s
a M
A
C
de
vi
ce. The
MAC de
vice a
l
so typically incorporates
a
b
u
s
con
t
ro
ller
su
itab
l
e fo
r the in
tend
ed
ho
st syste
m
, e.g
.
PCI if
i
m
p
l
e
m
en
ted
fo
r u
s
e in a
PC. An
o
t
h
e
r so
lu
tio
n th
at
h
a
s b
e
co
m
e
m
o
re co
m
m
o
n
is to
im
p
l
e
m
en
t th
e
Data Link
layer and
th
e Ph
ysical layer tog
e
th
er in a si
n
g
le d
e
vi
ce
i
n
or
der
t
o
sa
ve
sp
a
ce, power and
cut costs.
Whe
n
a t
w
o-device constellation is
used, the two
de
vices
are connected
to each ot
her
via the M
II
and/
or
GM
I
I
.
A be
ne
fi
t
wi
t
h
sepa
rat
e
M
A
C
and
PH
Y
de
vi
ces i
s
t
h
at
o
n
e M
A
C
de
vi
ce can
be c
o
n
n
ect
ed t
o
several
PH
Y
d
e
vi
ces. B
y
d
o
i
n
g
t
h
at
t
h
e
ban
d
wi
dt
h ca
n
be
in
creased
si
n
c
e th
e link
s
fo
rm a sing
le link
as seen
b
y
th
e LLC
sub
l
ayer. Th
is typ
e
o
f
link
is
referred
t
o
as agg
r
eg
ated
link.
In
t
h
is wo
rk
, a PHY
d
e
v
i
ce
will b
e
u
s
ed
an
d th
e
FPGA
will co
n
t
ain
th
e R
S
an
d
h
i
gh
er sub
l
ayers.
3.
DESIG
N
OF AR
CHITE
C
T
URE OF
T
H
E
M
A
C
IP CO
RE
Th
e Et
h
e
rn
et
IP Cor
e
co
nsists of
f
i
v
e
m
o
du
les (
a
s show
n in f
i
gu
r
e
2)
:
The host interface connects
the Ethe
rnet Core to t
h
e rest
of the
system via the
W
I
SHBONE (using
D
M
A
tr
a
n
sf
er
s)
.
Reg
i
s
t
e
r
s
ar
e a
l
s
o
p
a
rt
of the ho
st in
terface.
Th
e TX
Eth
e
rnet MAC p
e
rform
s
tran
s
m
it fu
n
c
tio
ns.
The R
X
Et
hernet MAC pe
rform
s
receive functions.
The M
A
C
C
o
n
t
rol
M
o
d
u
l
e
pe
rf
orm
s
ful
l
du
p
l
ex fl
ow
co
nt
r
o
l
fu
nct
i
o
ns.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
RES I
S
SN
:
208
8-8
7
0
8
Design
an
d Imp
l
emen
ta
tion
of a
n
Eth
e
rn
et
MAC IP Co
re fo
r Emb
e
dd
ed
App
lica
tio
ns
(
S
anket
Dess
ai
)
87
The M
II M
a
na
gem
e
nt
M
o
d
u
l
e
pe
rf
orm
s
PH
Y c
ont
rol
a
n
d
gat
h
e
r
s t
h
e
st
at
us i
n
f
o
rm
at
i
on
fr
om
i
t
.
The Et
her
n
et
I
P
C
o
re i
s
ca
pa
bl
e o
f
o
p
erat
i
n
g at
1
0
,
1
0
0
o
r
10
0
0
M
bps
f
o
r
Et
her
n
et
a
n
d
Fast
Et
he
rne
t
ap
p
lication
s
.
An
ex
tern
al PHY is
n
e
ed
ed fo
r th
e co
m
p
lete Eth
e
rn
et so
lu
tio
n.
The
Et
her
n
et
IP C
o
re
ca
n
o
p
erat
e i
n
hal
f
-
o
r
ful
l
-
d
upl
e
x
m
ode a
n
d i
s
base
d
o
n
t
h
e
C
S
M
A
/
C
D
(Carrie
r
Sense
Multiple Access / Collision Detection)
pr
otoc
ol.
Whe
n
a station wa
nts to transm
it
i
n
hal
f
-
duplex m
ode, i
t
m
u
st observe
the activ
ity on
the m
e
dia (Carrier Se
nse
)
.
Fi
gu
re
2.
Et
he
r
n
et
M
A
C
IP Core
Architecture
As soon as the
m
e
dia is idle (no tra
n
sm
ission),
a
n
y station
can sta
r
t tra
n
smit
ting (M
ultiple
Access).
If two
o
r
m
o
re statio
n
s
are tran
sm
it
tin
g
at th
e sam
e
ti
me,
a co
llisio
n
o
n
th
e m
e
d
i
a is d
e
tected
. All statio
n
s
st
op t
r
a
n
sm
i
t
ting a
n
d bac
k
o
f
f f
o
r s
o
m
e
random
t
i
m
e
. Aft
e
r t
h
e bac
k
-o
ff
t
i
m
e
, t
h
e st
ation c
h
ec
ks t
h
e
act
i
v
i
t
y
o
n
th
e m
e
d
i
a ag
ain.
If th
e m
e
d
i
a is id
le, it starts
transmitt
in
g
.
All
o
t
h
e
r station
s
wait fo
r t
h
e cu
rren
t
tran
sm
issio
n
to end
.
In
fu
ll-dup
lex
m
o
d
e
, th
e Carrier Se
n
s
e
an
d th
e C
o
llisio
n Detect signals are igno
red. Th
e
MAC Control
m
odule takes c
a
re of se
ndi
ng
and
receivi
ng
t
h
e P
A
USE c
o
ntrol fram
e to achieve Fl
ow c
ont
rol
(see t
h
e T
X
F
L
O
W
a
n
d R
X
F
L
O
W
bi
t
de
scr
i
pt
i
on i
n
t
h
e C
T
RLM
O
D
E
R register
fo
r m
o
re inf
o
rm
ation
)
. T
h
e
MII Ma
nagem
e
nt m
odule
provi
des a m
e
di
a inde
pe
nde
nt
interface
(MII) to th
e e
x
terna
l
PHY. T
h
is
way, the
co
nfigu
r
ation an
d statu
s
reg
i
sters
o
f
th
e
PHY can
b
e
read
fro
m
/
written
to
.
a.
H
o
st
I
n
t
e
rf
a
c
e
The
host interface is connected to the R
I
SC
and
the
m
e
m
o
ry through t
h
e
two
Wishbone
interface
s.
Th
e RISC writes th
e d
a
ta for th
e co
nfigu
r
atio
n
reg
i
ster
s d
i
rectly wh
ile th
e d
a
ta
frames are written
to
th
e
me
m
o
ry.
For writing
d
a
ta
to
con
f
i
g
uration
reg
i
sters, Wish
b
o
n
e
slav
e
in
terface
is u
s
ed. Data in
th
e
m
e
m
o
ry
is
accesses through the
Wis
h
bone m
a
ster interface.
b.
Frame T
r
ans
m
i
ssi
on
Al
g
o
r
i
thm
To
tran
sm
it th
e first
fram
e
, the RISC m
u
st do
sev
e
ral t
h
ings, nam
e
l
y
:
Sto
r
e th
e
fram
e
to
th
e m
e
m
o
ry.
Asso
ciate th
e Tx
BD in
th
e Eth
e
rn
et MAC co
re with
th
e
p
ack
et written
to
th
e
m
e
m
o
ry
(leng
t
h
,
p
a
d, crc,
etc.).
En
ab
le th
e
TX p
a
rt of th
e Et
h
e
rn
et Core
b
y
settin
g
t
h
e TXEN
b
it to
1
.
As soon
as th
e Eth
e
rn
et IP Core
is en
ab
led
,
it co
n
tinuo
usly read
s t
h
e
first B
D
.
Imm
e
d
i
ate
l
y whe
n
the
des
c
riptor is m
a
rked as
rea
d
y, t
h
e
core rea
d
s t
h
e
poi
nt
er t
o
t
h
e
m
e
m
o
ry
st
ori
ng t
h
e ass
o
ciated data and s
t
arts then reading data to the
in
tern
al
FIFO.
At th
e m
o
m
e
n
t
th
e FI
F
O
i
s
f
u
l
l
,
t
r
ansm
i
ssi
on be
gi
ns
.
At th
e end
o
f
t
h
e tran
sm
issio
n
,
t
h
e tran
sm
it
statu
s
is
written
to th
e
bu
ffer
d
e
scri
p
t
or an
d
an
in
terru
p
t
m
i
ght
be
ge
ne
rat
e
d
(
w
he
n e
n
abl
e
d)
.
Next
,
t
w
o
e
v
ent
s
m
i
ght
occ
u
r
(ac
c
or
di
n
g
t
o
t
h
e
W
R
bi
t
(
w
rap
)
i
n
t
h
e
descri
pto
r):
If th
e
WR b
it h
a
s no
t b
e
en
set, th
e BD address is in
crem
en
ted
,
t
h
e n
e
x
t
d
e
scri
p
t
o
r
is l
o
ad
ed
, and
th
e
pr
ocess
st
art
s
a
l
l
ove
r a
g
ai
n
(i
f
next
B
D
i
s
m
a
rke
d
as
rea
d
y
)
.
If th
e
W
R
b
it h
a
s
b
een
set, th
e first BD add
r
ess (b
ase)
is loade
d
a
g
ain.
As s
o
on as t
h
e
BD is m
a
rked as
read
y, transm
is
sio
n
will start.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
089
-48
64
IJR
E
S V
o
l
.
3, No
. 3, N
ovem
b
er
2
0
1
4
:
85
– 97
88
c.
Frame Reception Algorithm
Gri
d
size plays an im
portant role
in both c
o
nverge
nce and
To recei
ve
the
first fram
e
, the RISC m
u
st
do
se
veral
t
h
i
n
gs,
nam
e
l
y
:
Set
the receive buffe
r desc
ript
or
to be
as
soci
ated
with the
received
pac
k
et
and m
a
rk it as
e
m
pty.
Ena
b
le
the Ethernet receive
function
by sett
ing t
h
e RECE
N
bit to
1.
The Ethe
rnet IP Core rea
d
s t
h
e Rx BD. If
it is
ma
rked a
s
e
m
pty, it s
t
a
r
ts receiving fram
es. The
Ethernet receive function re
ceives
an inc
o
ming fram
e
nibble pe
r ni
bbl
e. After the
whole fram
e ha
s bee
n
receive
d and st
ore
d
to t
h
e m
e
m
o
ry, the receive status is
wri
tten to the BD. An i
n
terrupt might be gene
rated (if
en
ab
led
)
. Th
en th
e BD ad
d
r
ess is in
crem
ented and the ne
xt BD loaded. If
the new BD
is
m
a
rked as em
pty,
anot
her fram
e
can be recei
ve
d; othe
rwise the ope
ration
stops. Only fram
e
s with lengt
h greater tha
n
4
bytes
are recei
ve
d
without an error.
Sm
a
ller fram
e
s are
receive
d
with a CRC error (CRC is
4-by
tes long).
d.
T
X
Ethe
rnet MAC
The T
X
Ethe
r
n
et M
A
C
gen
e
rates 1
0
BA
S
E
-T/1
0
0
BAS
E
-TX t
r
ansm
it
M
II
nib
b
le dat
a
stream
s in
respon
se to th
e b
y
te stream
s t
h
e tran
sm
it lo
g
i
c (ho
s
t) su
ppl
i
e
s. It
per
f
o
r
m
s
t
h
e re
q
u
i
r
ed
d
e
fer
r
al
an
d
bac
k
-
o
f
f
alg
o
rith
m
s
, ta
k
e
s care of the in
ter-p
ack
e
t
g
a
p
(IPG),
c
o
m
putes the checksum
(FCS), and m
onitors the
p
h
y
sical m
e
d
i
a (b
y m
o
n
itoring
Carrier
Sen
s
e and
co
llisio
n sig
n
a
ls).
Th
e
TX Et
h
e
rn
et
MAC is d
i
v
i
d
e
d
in
t
o
sev
e
ral m
o
du
les th
at
p
r
o
v
i
d
e
t
h
e
fo
llowing
fu
n
c
tion
a
lity:
Gene
rat
i
o
n
of t
h
e si
gnal
s
c
o
n
n
ect
ed t
o
t
h
e E
t
her
n
et
P
H
Y
d
u
ri
ng
t
h
e t
r
a
n
s
m
i
ssi
on p
r
oces
s
Gene
rat
i
o
n
of t
h
e st
at
us
si
g
n
al
s t
h
e
h
o
st
uses
to
track
th
e tran
sm
issio
n
pro
c
ess
Ran
d
o
m
ti
me g
e
n
e
ration
u
s
ed
in th
e
b
a
ck
-off
pro
cess after a co
llision
h
a
s b
e
en
d
e
tected
CRC g
e
n
e
ration
an
d ch
eck
i
ng
Pad ge
nerat
i
o
n
Dat
a
ni
bbl
e
ge
nerat
i
o
n
e.
32 BIT Checking
Algorithm
Th
e
fram
e
ch
eck
seq
u
e
n
c
e field
p
r
o
v
i
d
e
s a m
ech
an
ism
fo
r error detectio
n
.
Each tran
sm
itter
co
m
p
u
t
es a cyclic red
und
an
cy ch
eck
(CRC) th
at co
v
e
rs
t
h
e ad
dress
field
s
, t
h
e typ
e
and
th
e
d
a
ta fiel
d
.
Th
e
transm
it
ter the
n
places t
h
e c
o
m
puted CRC in the
four
by
tes CRC field. As the CRC
field is the rem
a
inde
r
whe
n
M
(
X
)
i
s
di
vi
de
d by
t
h
e fol
l
o
wi
n
g
p
o
l
y
nom
i
a
l
:
G(
X)
=
X
32
+ X
26
+ X
23
+ X
22
+ X
16
+ X
12
+ X
11
+ X
10
+ X
8
+ X
7
+ X
5
+ X
4
+ X
2
+ X+
1,
wh
ere M
(
X) is
a po
lyn
o
m
ial t
h
at cov
e
rs th
e
d
a
ta b
its.
In g
e
ne
ral
,
di
gi
t
a
l
l
ogi
c do
es not
i
m
pl
em
ent
effi
ci
ent
l
y
t
h
e di
vi
si
on of
very
l
a
r
g
e n
u
m
b
er.
Co
n
s
equ
e
n
tly,
b
i
n
a
ry in
form
a
tio
n
m
u
st b
e
co
nv
erted
i
n
to
a m
o
re app
r
opriate fo
rm
b
e
fo
re th
e CRC i
s
u
s
ed.
Th
e string
s of b
its to
b
e
v
e
ri
fied
is
represent
e
d as the coeffi
cients of a
large polynom
i
a
l
, rather tha
n
as a large
bi
na
ry
n
u
m
b
er,
as s
h
o
w
n i
n
t
h
e f
o
l
l
o
wi
ng
ex
am
pl
e:
1
,
1
000
,0
000
,00
0
0
,
01
01
= X
16
+X
15
+X
2
+1
Typ
i
cally, CR
C calcu
latio
n
s
are im
p
l
e
m
en
ted
with
linea
r-fee
dbac
k
s
h
ift
registers
(
LF
S
R
s). LF
SRs
use a
m
e
t
hod t
h
at
y
i
el
ds t
h
e sam
e
resul
t
s
as subt
ract
i
o
n
and s
h
i
f
t
di
vi
s
i
on p
r
oce
ss w
h
en t
h
e s
ubt
ra
ct
i
on i
s
per
f
o
r
m
e
d wi
t
h
o
u
t
car
ry
by
t
h
e X
O
R
f
u
nct
i
o
n
.
T
o
af
fect
s
ubt
ract
i
on a
n
d
shi
f
t
di
vi
si
o
n
o
n
e bi
t
at
a t
i
m
e, y
o
u
can shift through a
nd e
x
am
in
e each bit in
the ori
g
inal fra
m
e of data. For th
e first bit of value 1, the divis
o
r
hi
g
h
-
o
r
d
e
r
ed b
i
t
i
s
subt
ract
ed
(XOR
) fr
om
the di
vi
den
d
. T
h
at
di
vi
de
n
d
b
i
t
,
whi
c
h i
s
un
necessa
ry
and
i
s
not
g
e
n
e
r
a
ted, is set to
zero
b
y
t
h
e su
b
t
r
actio
n. Th
e low
e
r
ord
e
r b
its
o
f
t
h
e d
i
v
i
so
r cannot b
e
su
b
t
r
acted yet,
because the
c
o
rres
p
onding
di
visor
bits
have
not been
s
h
ift
e
d
i
n
. As shown in the followi
ng fi
gure,
for the
si
m
p
le case o
f
th
e CRC-16
,
th
e alg
o
rith
m
is i
m
p
l
e
m
en
te
d
b
y
sh
ifting
th
e d
a
ta stream
in
to
a 16-b
it
sh
ift
register. Register Bit(0) recei
ves an
XOR of the incom
i
ng data and the ou
tput of Bit(15). Bit(2)
receives an
XOR
of the i
n
put to Bit(0) a
nd t
h
e ou
tput of Bit(1). Bit(15) recei
ves a
n
XOR of the
input to
Bit(0) and the
o
u
t
p
u
t
of Bit(14
). In
t
h
e case of CRC-3
2
,
wh
ich
is used
in
Eth
e
rn
et h
e
ader, we u
s
e
14
XOR
g
a
tes, o
n
e
fo
r
each coefficient of polynomial
G(
X). As data is shifted into
the CRC circuitry, a CRC calc
u
lation
accum
u
lates in
the registers.
Whe
n
the CRC value is loaded
int
o
the CRC calculation register, the e
ndi
ng
CRC ch
eck
sum
is
lo
ad
ed
into
th
e CRC R
e
g
i
ster. Th
e v
a
lu
e lo
ad
ed
in
to
th
e CRC Re
g
i
ster sho
u
l
d
be zero
;
o
t
h
e
rwise, th
e
co
nfigu
r
ation failed
CRC ch
eck
.
In
add
itio
n, as
th
e d
a
ta is
8
-
b
i
t wid
e
we tak
e
ad
v
a
n
t
ag
e of t
h
e
Verilog
v
a
ri
ab
les in
ord
e
r t
o
p
r
o
cess
8
bit data each clock cycle. In orde
r to
calculate the CRC fiel
d, as soon as the
first bit is processed,
we save this
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
RES I
S
SN
:
208
8-8
7
0
8
Design
an
d Imp
l
emen
ta
tion
of a
n
Eth
e
rn
et
MAC IP Co
re fo
r Emb
e
dd
ed
App
lica
tio
ns
(
S
anket
Dess
ai
)
89
register and we
immediately begin the
proces
s of t
h
e sec
o
nd
bi
t
.
Thi
s
way
we ac
hi
eve
t
h
e
seri
al
pr
ocessi
ng
o
f
8
bits for the C
RC calcula
t
i
o
n
i
n
onl
y
one
cy
cl
e.
f.
RX
Et
hernet M
A
C
Th
e RX
Et
h
e
rn
et MA
C tr
ansmits th
e d
a
ta str
eam
s
to
th
e h
o
s
t in
r
e
spo
n
s
e to
th
e 10
/10
0
/
1000
receive
d MII
nibbles. The
m
odule is
di
vide
d into
se
veral sub-m
o
dules
prov
iding t
h
e
foll
owi
n
g functionality:
Pream
ble rem
oval
Data assem
b
ly (fro
m
in
pu
t n
i
bb
le to
ou
tpu
t
byte)
CRC ch
eck
i
n
g
for all in
co
m
i
n
g
p
ack
ets
Gene
rat
i
o
n
of t
h
e si
gnal
t
h
at
c
a
n
be
use
d
f
o
r
add
r
ess
rec
o
g
n
i
t
i
on (i
n t
h
e
ha
sh t
a
bl
e)
Gene
rat
i
o
n
of t
h
e st
at
us
si
g
n
al
s t
h
e
h
o
st
uses
to
track
th
e recep
tio
n pro
cess
g.
MAC Contr
o
l
Module
The M
A
C
C
o
n
t
rol
M
o
dul
e
pe
rf
orm
s
a real
-t
i
m
e fl
ow c
ont
r
o
l
f
unct
i
o
n f
o
r
t
h
e f
u
l
l
-
d
upl
e
x
o
p
e
r
at
i
o
n
.
The control opcode PAUSE
is used
for stopping the sta
tion tra
n
sm
itti
ng t
h
e pac
k
ets
.
The receive
buffe
r
(FIFO) starts filling up
when the uppe
r layer cannot co
ntinue acce
pting the incom
i
ng packets. Before an
ove
rfl
ow
ha
pp
ens, t
h
e
u
ppe
r
l
a
y
e
r sends a
PAU
S
E c
ont
r
o
l
fram
e
t
o
t
h
e t
r
ansm
i
t
t
i
ng st
at
i
on. T
h
i
s
cont
r
o
l
fram
e
in
h
i
b
its
th
e transm
issi
o
n
of th
e
d
a
ta fram
e
s fo
r a
specified pe
riod of tim
e. When the M
A
C
Control
m
odule receives a PAUSE c
ont
rol fram
e, it loads the pa
us
e tim
e
r with the receive
d va
l
u
e into the
paus
e tim
e
r
v
a
lu
e fiel
d
.
The Tx
MAC is sto
p
p
e
d
(pau
sed
)
fro
m
tr
an
s
m
ittin
g
th
e d
a
ta
fram
e
s fo
r th
e
“p
ause ti
m
e
r v
a
lu
e”
slot tim
e
s. The
pa
use tim
er decrem
ents by one eac
h
t
i
m
e a
sl
ot
t
i
m
e
passes by
.
Wh
en t
h
e
pa
use t
i
m
e num
ber
eq
u
a
ls zero
,
t
h
e MAC tran
smitter re
su
m
e
s th
e tran
sm
it o
p
eratio
n.
Th
e M
A
C Contro
l Modu
le h
a
s th
e
fo
llowing fu
n
c
tion
a
lity:
Co
n
t
ro
l fram
e
d
e
tectio
n
C
ont
r
o
l
fram
e
gene
rat
i
o
n
TX/RX M
A
C In
terface
PAUSE Tim
e
r
Slot Tim
e
r
h.
MII Manage
ment Module
The M
I
I Mana
gem
e
nt Module is a
sim
p
le two-wi
re
i
n
terface bet
w
een the host a
n
d a
n
e
x
ternal
PHY
device.
It is used for configuration an
d status read of the physical device.
The physical interface c
o
nsists of a
managem
e
nt data line MDIO (Managem
ent Data Inpu
t
/
O
ut
p
u
t
)
an
d a cl
ock l
i
n
e MDC
(Managem
ent Data
Clo
c
k
)
. During th
e read
/write o
p
e
ration
,
th
e
m
o
st sig
n
i
fican
t b
it is sh
i
f
ted in
/o
u
t
first from/to
th
e MDIO d
a
ta
signal. On eac
h rising edge of the MD
C, a Sh
ift reg
i
ster is sh
ifted
to
th
e left an
d
a n
e
w v
a
lu
e app
ears
o
n
th
e
MD
IO
.
In
tern
ally th
e i
n
terface co
n
s
ists o
f
fou
r
si
gn
als:
MD
C
MD
I
MD
O
M
DOE
N (M
an
agem
ent
Data Out
put Ena
b
le)
The
uni
di
rect
i
onal
l
i
n
e
s
M
D
I, M
D
O
,
an
d
M
DOE
N a
r
e c
o
m
b
i
n
ed t
o
m
a
ke a
bi
-
d
i
r
ect
i
onal
si
gnal
MDIO that is
c
o
nnected to t
h
e
PHY.
Th
e configu
r
at
io
n
an
d
status d
a
ta is written
/
read
to
/
f
ro
m
th
e PHY v
i
a th
e
MDIO sign
al.
Th
e MDC is
a l
o
w
f
r
eq
ue
nc
y
cl
ock
de
ri
ve
d
fr
om
di
vi
di
n
g
t
h
e
h
o
st
cl
oc
k.
Th
ree co
mm
an
d
s
are sup
p
o
r
ted
for co
n
t
ro
lling
th
e PHY:
Write Con
t
ro
l
Data (writes t
h
e con
t
ro
l d
a
ta t
o
th
e PHY Configu
r
ation
reg
i
sters)
R
ead St
at
us
(
r
e
a
ds t
h
e P
H
Y C
ont
rol
a
n
d St
at
us
regi
st
er
)
Scan
Status
(c
ontinuously re
ads t
h
e PHY St
atus re
gi
st
er
o
f
o
n
e
or
m
o
re P
HYs
[l
i
n
k
fai
l
st
at
us]
)
.
The M
II M
a
na
gem
e
nt
M
o
d
u
l
e
co
nsi
s
t
s
of
f
o
ur
su
b m
o
d
u
l
e
s
:
Op
eration
Contro
ller
Sh
ift Reg
i
sters
Out
put
C
o
nt
rol
M
o
d
u
l
e
C
l
ock Ge
nerat
o
r
4.
DESIG
N
OF VERIF
I
CATI
ON
T
OOL
A GUI con
f
i
g
u
r
ation
in
terface, created b
y
Tcl/tk
scrip
t
lan
g
u
a
g
e
, is co
nv
en
ien
t
for
co
nfigu
r
i
n
g
opt
i
o
nal
m
o
d
u
l
e
s, F
I
F
O
dept
h
an
d
veri
fi
cat
i
o
n
param
e
t
e
rs.
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I
S
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E
S V
o
l
.
3, No
. 3, N
ovem
b
er
2
0
1
4
:
85
– 97
90
a.
Confi
g
ur
ati
o
n Op
tion
Mod
u
le
There a
r
e three optional modules ca
n be
rem
ove
d from IP core t
o
reduce area
. This GUI
con
f
i
g
urat
i
o
n t
ool
i
s
used t
o
cust
om
i
ze t
h
i
s
IP c
o
re.
The
d
e
si
gne
d
GU
I
wi
n
d
o
w
a
ppea
r
s o
n
sc
reen a
s
sh
ow
n
in fi
gu
re
3:
Fi
gu
re 3.
G
U
I
C
o
n
f
i
g
urat
i
o
n
C
l
i
c
ki
ng t
h
e c
h
eck
b
u
t
t
on
wi
l
l
enabl
e
t
h
e c
o
r
r
es
po
n
d
i
n
g m
odul
e of
IP c
o
re
. The
FIF
O
dept
h can
be
set
i
n
t
h
i
s
wi
nd
ow
. The de
fa
ul
t
set
t
i
ng of FIF
O
de
pt
h i
s
9, w
h
i
c
h m
eans t
h
at
t
h
e FIFO can
cont
ai
n
51
2 w
o
r
d
s
.
Because of the FIFO
width of
use
r
side i
s
32bit,
the a
c
t
ual capacity of
FIFO
is 512*4=
2K bytes.
Afte
r
chan
gi
n
g
t
h
e s
e
t
t
i
ng, i
t
’
s
rec
o
m
m
e
nded t
o
sa
ve t
h
e
ne
w c
o
n
f
i
g
urat
i
o
n.
b.
Operation of Veri
fi
ca
ti
on
T
ool
Upon
click
i
ng
th
e
“v
erify” b
u
tto
n
o
f
abo
v
e
wind
ow,
a n
e
w wind
ow will
app
ear fo
r v
e
rificatio
n
(as
sho
w
n i
n
fi
gu
r
e
4
)
.
Fi
gu
re 4.
G
U
I
C
o
n
f
i
g
urat
i
o
n
Th
e first bu
tton
“set
_
s
tim
u
l
u
s
”
(p
lease refer
fi
g
u
re 5)
is u
s
ed
to
config
th
e p
a
ram
e
ters
u
s
ed
fo
r
au
to
m
a
tical
ly
g
e
n
e
rate stim
u
l
u
s
for sim
u
lati
o
n
.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
RES I
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8-8
7
0
8
Design
an
d Imp
l
emen
ta
tion
of a
n
Eth
e
rn
et
MAC IP Co
re fo
r Emb
e
dd
ed
App
lica
tio
ns
(
S
anket
Dess
ai
)
91
Fig
u
re 5
.
Stimu
l
u
s
Settin
g Win
d
o
w
Fi
gu
re
6.
R
e
gi
s
t
er C
o
nfi
g
u
r
at
i
o
n
Upon
selectin
g “Ran
do
m
”
m
o
d
e
, th
e
g
e
n
e
rat
e
d
p
a
ck
et leng
th
will b
e
rand
om in
th
e rang
e
o
f
“Pack
e
t
b
e
g
i
n
leng
th
”
an
d
“Pack
e
t en
d
leng
th
” as
sh
own
in
figu
re 6
.
Th
e
g
e
n
e
rated
p
a
ck
et num
b
e
r will b
e
eq
u
a
l
t
o
“Tot
al
Gen Pa
cket
num
ber”.
If nee
d
e
d
t
o
g
e
nerat
e
t
h
e b
r
oadca
s
t
packet
s;
i
t
can be done
by
cl
i
c
ki
n
g
t
h
e
“b
ro
ad
cast” select b
u
tton
.
Th
e “sav
e” bu
tto
n
will sav
e
cu
rren
t co
nfigu
r
ati
o
n
to
“con
f
i
g
.in
i
” file. Fu
rt
h
e
rm
o
r
e,
one ca
n
use “s
ave as” button to save the c
o
nfi
g
uration
a
s
anot
her
fi
l
e
w
h
i
c
h ca
n be
us
ed f
o
r “
b
at
ch
_
m
ode”
“set_
c
pu_
d
a
ta” bu
tto
n
o
f
m
a
in
wind
ow is used
t
o
co
nfig
in
tern
al reg
i
sters.
All th
e
reg
i
sters will
b
e
listed
i
n
follo
win
g
fo
rm
s:
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64
IJR
E
S V
o
l
.
3, No
. 3, N
ovem
b
er
2
0
1
4
:
85
– 97
92
Th
e “sav
e”
b
u
tto
n
will sav
e
cu
rren
t configu
r
ation
to
file “CPU.d
at”.Also
, u
s
er can
u
s
e “sav
e as”
but
t
o
n t
o
save
regi
st
er set
t
i
n
g
t
o
any
ot
hers
f
i
l
e
s y
ou l
i
k
e. S
o
m
e
co
m
p
l
e
x ope
rat
i
o
n o
f
re
gi
st
er s
u
ch as
r
eadi
n
g
st
at
i
s
t
i
c
count
ers
need
t
o
e
d
i
t
“C
PU
.dat
”
fi
l
e
m
a
nual
l
y
.
Th
e “start
_
v
erify” of m
a
i
n
wind
ow
will start
si
m
u
latio
n
.
The co
m
p
ilat
i
o
n
an
d
sim
u
latio
n o
u
t
p
u
t
will be p
r
in
ted
in
the fo
llowing
wi
n
dows as sh
own
i
n
fig
u
re 7.
Fi
gu
re
7.
Ve
ri
f
i
cat
i
on T
ool
Si
m
u
l
a
t
o
r
At first, a b
a
sh
scri
p
t
will b
e
in
vo
k
e
d
to
co
m
p
ile th
e s
o
urce file .If
n
o
an
y error o
ccurred
;
th
e
Mo
d
e
lSim
-si
m
u
l
ato
r
will b
e
in
vo
k
e
d
to
start si
m
u
latio
n
.
Wh
en
an
y erro
r
p
ack
et is receiv
e
d
,
t
h
e sim
u
la
to
r
will stop and
print the
data
of recei
ved error packet. The “b
atch_m
ode” button of m
a
in windwos
will invoke
settin
g
r
e
g
i
ster d
a
ta
w
i
nd
ow
as show
n in
f
i
gur
e
8
.
Fi
gu
re 8.
R
e
gi
s
t
er
Dat
a
Set
t
i
ng W
i
n
d
o
w
Th
is wi
n
dow
will b
e
u
s
ed
to p
e
rform
v
e
rify th
e IP
core
with
sev
e
ral test case. In
t
h
is
wind
ow,
u
s
er
can c
h
an
ge t
h
e
desc
ri
pt
i
o
n,
st
i
m
ul
us and
re
g
vect
o
r
of a
t
e
st
case.
5.
RESULTS
A
N
D
DI
SC
US
S
I
ONS
Before starting to
use th
is
IP
co
re, th
e
fo
ll
owing
work
i
n
g
en
v
i
ron
m
en
t need
s to b
e
m
a
d
e
read
y.
At
fi
rst
,
i
t
i
s
needed t
o
set
up a
W
i
n
X
P (
r
ecom
m
ended
)
o
r
ot
her st
abl
e
o
p
er
at
i
ng sy
st
em
. In ad
di
t
i
on, C
y
gwi
n
i
s
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
RES I
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:
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8-8
7
0
8
Design
an
d Imp
l
emen
ta
tion
of a
n
Eth
e
rn
et
MAC IP Co
re fo
r Emb
e
dd
ed
App
lica
tio
ns
(
S
anket
Dess
ai
)
93
n
eed
ed
to
ru
n
so
m
e
b
a
sh
scri
pts. Tcl/tk
is also
n
e
ed
ed
fo
r m
a
n
y
GUI scrip
t
s. Fin
a
lly, th
e
Mo
d
e
lSim
is n
eed
ed
fo
r sim
u
lation.
a.
1
000
M
bps Full D
uplex 46-
15
00
Lengt
h
Pa
cket
Thro
ugh Test
There a
r
e three optional modules ca
n be
rem
ove
d from IP core t
o
reduce area
. This GUI
co
nfigu
r
ation
t
o
o
l
is
u
s
ed
t
o
cu
sto
m
ize th
is IP core
.
Sp
ecifiy th
e p
a
cket len
g
t
h in
t
h
e settin
g
stim
u
l
u
s
as
sh
own
i
n
Fi
g
u
re
8
.
Th
en select “start_v
erify” at m
a
in
frame. Th
e scri
p
t
will call th
e
Mo
d
e
lSim
si
mu
lation
tools
to verify the
design. The
pack
et se
nt to PHY
will loop
bac
k
to re
c
e
iving
port .When a “
g
ood”
packet
receive
d; the
followi
ng m
e
ss
age is
pri
n
ted:
th
e NO. 000
1 IP Len
g
t
h
is:004
6 CRC-32
ch
eck
OK!
th
e NO. 000
2 IP Len
g
t
h
is:004
7 CRC-32
ch
eck
OK!
th
e NO. 000
3 IP Len
g
t
h
is:004
8 CRC-32
ch
eck
OK!
th
e NO. 000
4 IP Len
g
t
h
is:004
9 CRC-32
ch
eck
OK!
th
e NO. ffff
IP
Leng
th
is:005
0 CRC-32
ch
eck OK!
Press “set
_cp
u
_dat
a”
but
t
o
n
on m
a
i
n
fram
e
t
o
set
core t
o
10
0M
b
p
s m
o
d
e
as sho
w
n i
n
Fi
gu
re 4
.
The
spee
d param
e
ter needs
t
o
be chan
ge
d
as
pe
r
t
h
e fi
g
u
re 9.
Fig
u
re
9
.
Settin
g Reg
i
ster fo
r 10
0
M
b
p
s
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I
S
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64
IJR
E
S V
o
l
.
3, No
. 3, N
ovem
b
er
2
0
1
4
:
85
– 97
94
After selecting the core spee
d, the ve
rification nee
d
s
t
o
be s
t
art
e
d by
cl
i
c
ki
ng
o
n
ve
ri
fy
b
u
t
t
on
o
f
t
h
e
main
w
i
nd
ow
.
Th
e
r
e
g
i
ster settin
g
n
e
ed
s to
be ch
an
g
e
d
as
per
th
e f
l
ow
contr
o
l test as show
n in
Figu
r
e
10
.
Fi
gu
re
1
0
.
Set
t
i
ng R
e
gi
st
er
fo
r Fl
ow C
o
nt
r
o
l
Startin
g th
e
v
e
rify, th
e sim
u
la
tio
n
will o
u
t
put
Pause
fram
e received:
Received
Paus
e Quanta is:
0x000a
At th
e sam
e
ti
me, th
e tran
smit state
m
ach
in
e will en
ter
p
a
u
s
e m
o
d
e
and
d
e
lay p
a
ck
et sen
d
fo
r 10 slo
t
ti
m
e
.
b.
B
r
oa
dcas
t Fi
l
t
er T
e
st
Set
t
i
ng St
i
m
ul
us as
f
o
l
l
o
wi
n
g
wi
n
d
o
ws
as s
h
ow
n i
n
Fi
gu
re
11
.
Evaluation Warning : The document was created with Spire.PDF for Python.