Intern
ati
o
n
a
l
Journ
a
l of
Re
con
f
igur
able
and Embe
dded
Sys
t
ems
(I
JRES)
V
o
l.
4, N
o
. 3
,
N
o
v
e
m
b
er
2
015
, pp
. 19
2
~
20
0
I
S
SN
: 208
9-4
8
6
4
1
92
Jo
urn
a
l
h
o
me
pa
ge
: h
ttp
://iaesjo
u
r
na
l.com/
o
n
lin
e/ind
e
x.ph
p
/
IJRES
An Efficient app
r
oach for De
sign and Testing of FPGA
Programming using LabVIEW
B. Naresh Kumar
Reddy, N. Sures
h
Dept. of
Electro
n
ics and
Commu
nica
tion
Engineering, NIT Goa, I
ndia
Article Info
A
B
STRAC
T
Article histo
r
y:
Received
J
u
n 26, 2015
Rev
i
sed
Sep 9, 20
15
Accepted
Sep 28, 2015
Programming of
Field Programmable Ga
te Array
s
(FPGAs) has long been
the domain of
engineers with
VHDL or
Verilog expertise.
F
P
GA’s have
caught
the atten
t
ion of algor
ithm develo
p
e
rs
and communication research
ers,
who want to use
FPGAs to instan
tiat
e
s
y
s
t
ems or implement DSP algorithms.
These effor
t
s however, ar
e often
stifled b
y
the c
o
m
p
lexities of p
r
ogram
m
i
ng
FPGA
s
.
RTL programming in either VHDL
or Verilog is
generally
not a
high lev
e
l of abs
t
raction needed
to repr
esent
the
world of signal f
l
ow graphs
and complex
signal pro
cessing
algorith
ms.
This
paper
descr
i
bes
the FPGA
Programs using
Graphical
Language rather than
Verilog,
VHDL with the
help of
LabVIEW and featur
es
o
f
the LabVIEW
FPGA environment.
Keyword:
Lab
V
IE
W s
o
ftware
FPGA B
o
ard
Copyright ©
201
5 Institut
e
o
f
Ad
vanced
Engin
eer
ing and S
c
i
e
nce.
All rights re
se
rve
d
.
Co
rresp
ond
i
ng
Autho
r
:
B. Na
res
h
Ku
m
a
r Reddy
,
Depa
rt
em
ent
of El
ect
r
oni
cs
a
n
d
C
o
m
m
uni
cat
i
on E
n
gi
nee
r
i
n
g
,
NIT
Goa, India.
Em
a
il: n
a
resh
.k
lu@g
m
a
il.co
m
1.
INTRODUCTION
A.
In
tro
ducti
on to
FP
GA
:
Fi
el
d Pr
o
g
ram
m
abl
e
Gat
e
A
r
ray
s
pe
rv
asi
v
el
y
kn
o
w
n
as F
P
G
A
i
s
a
n
opt
i
on
fo
r
usa
g
e
of a
d
va
nced
ratio
n
a
le in
framewo
rk
s [1
].
Th
ey are
p
r
e-assem
b
led
ch
i
p
s
t
h
at
m
i
ght
be
cust
om
i
zed electrically to actualize
any advance
d
configuration. The m
a
in
static
m
e
m
o
ry-b
ased
FPGA (o
rd
in
arily termed
as SRAM b
a
sed
FPGA) isin
trod
u
c
ed
. Th
is co
n
s
t
r
u
c
tion mo
d
e
lling
t
o
ok
in
to
con
s
id
eratio
n bo
th log
i
c and
i
n
terco
nnection
arran
g
e
m
e
n
t
u
tilizin
g
a series o
f
d
e
sign
b
its. Xilin
x
in
tr
od
uced
th
e clu
s
ter o
f
co
nfigu
r
e l
o
g
i
c
b
l
o
c
k
s
(C
LB‘s)
wi
t
h
I/
O,
Whi
c
h
hol
d 6
4
C
L
B
‘
s &
5
8
I/
O i
n
Fi
rst
m
oder
n
C
o
m
m
e
rci
a
l
FPG
A‘s
,
FPG
As
ha
ve
becom
e
co
lo
ssally in
man
y
-sid
ed
q
u
ality
[2
]. No
w a d
a
ys
ad
v
a
nced
FPGA can h
o
l
d
rou
g
h
l
y 0
.
3
3
m
ill
io
n
ratio
n
a
le
pieces and 1100 I/O. T
h
e fundam
ental
building desi
gn
of FPGA com
p
rises of
three real
parts: program
m
able
rationale
pieces, which actual
i
ze the rational
e
capacities,
programm
able di
recting
(i
nterc
o
nnects) t
o
execut
e
th
ese cap
acities an
d
I/
O clo
s
es to
Mak
e
o
f
f-ch
i
p
asso
ciatio
n
s
A
Design o
f
FPGA arch
itectu
r
e is sho
w
n
in
fig
u
re
1.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
089
-48
64
I
J
RES Vo
l. 4
,
N
o
. 3
,
No
v
e
m
b
er
201
5
:
1
92
–
20
0
19
3
Fi
gu
re 1.
FP
G
A
Arc
h
i
t
ect
ure
1)
Pr
o
g
ram
m
abl
e
L
ogi
c:
FPG
A c
o
nsi
s
t
s
o
f
pr
o
g
ram
m
abl
e
l
ogi
c
bl
ock
,
whi
c
h i
s
use
d
f
o
r esse
n
t
i
a
l
proce
ssi
n
g
an
d st
ori
n
g
el
em
ent
s
used
i
n
va
ri
o
u
s c
o
m
put
e
r
ized
frameworks. T
h
e Fundam
ental el
e
m
en
t in
pr
og
r
a
mmab
l
e lo
g
i
c b
l
ock
hol
ds se
veral
t
y
pes o
f
rec
o
nfi
g
u
r
a
b
l
e
com
b
i
n
at
i
onal
l
ogi
c l
i
k
e
flip-flop
s, latch
e
s in
o
r
d
e
r to
red
u
c
e area an
d
del
a
y
cost
.
The
r
e are
al
so a
d
v
a
nced
FP
G
A
s,
whi
c
h c
onsi
s
t
of
het
e
r
o
gene
o
u
s m
i
xt
ure
of
di
ffe
re
nt
bl
ock
s
su
c
h
as d
e
d
i
cated
me
m
o
ry b
l
o
c
ks, m
u
ltip
lex
e
rs etc. an
d
each
o
f
t
h
em
are
u
s
ed fo
r sp
ecific fun
c
tion
a
lity.
Design
m
e
m
o
ry is u
tilized
b
y
en
tire l
o
g
i
c
b
l
o
c
k to
con
t
ro
l
cap
acity o
f
ev
ery co
m
p
on
en
t i
n
sid
e
th
e
b
l
o
c
k.
2)
Pr
o
g
ram
m
abl
e
I
n
t
e
rc
on
ne
ct
:
B
y
pro
g
ram
m
ing t
h
e FP
G
A
s,
we can gi
ve c
o
n
n
ect
i
o
ns am
on
g va
ri
o
u
s l
o
gi
c bl
oc
ks an
d I/
O bl
oc
ks t
o
finish a
client characte
r
ized outline.
Each
FPGA c
o
nsists of c
o
m
pone
nt
s like pass
tra
n
sistors, m
u
ltiplexe
r
s
and tri-state buffe
rs [2]. Most part
of
t
h
e
pass
transistors a
nd m
u
ltiplexers
a
r
e used t
o
interface logic elements
i
n
l
o
gi
c cl
ust
e
r,
whi
l
e
eac
h
am
ong
t
h
ree
a
r
e us
ed
f
o
r m
o
re
w
o
rl
dwi
d
e
di
rect
i
n
g st
r
u
ct
ures.
S
o
m
e
of t
h
e
wo
rld
w
ide ste
e
rin
g
struct
ure
s
, w
h
ich
are
used as a part
of FPGAs a
r
e island style, cellular, bus
base
d and
registere
d
a
r
c
h
itectures
3)
Pr
o
g
ram
m
able I/
O:
Programmable I/O
m
eans a media or m
e
a
n
to inte
rface
logic bloc
ks a
nd ro
uting arc
h
itectures to
v
a
riety o
f
ou
ter seg
m
en
ts in
FPGA. Th
e log
i
c circu
itr
y and I/
O pa
d pre
s
ent in FPGA
form
s are also in I/O
cell. These cells are prese
n
t in cr
itical segment of t
h
e FPGA and expa
nded over
40% of FPGAs z
o
ne. The
m
o
st
chal
l
e
ngi
ng c
o
ncer
n am
on
g P
r
o
g
ram
m
a
bl
e I/
O
bl
oc
k
i
s
t
h
at
t
h
ere i
s
a great
di
ve
rsi
t
y
am
ong refe
r
e
nce
and supply voltage standards. A standout
am
ongst th
e
m
o
st critical
choices
in
I/O
struct
ural pla
nni
ng
co
nfigu
r
ation
i
s
th
e d
e
term
in
atio
n
of m
o
d
e
ls th
at will
b
e
back
ed. Th
is in
clu
d
e
s
p
a
in
stak
in
g
l
y m
a
d
e
ex
ch
ange
o
f
f’s
on
th
e
g
r
o
und
s th
at,
d
i
ssi
m
ilar to
Lo
ok
Up
Tab
l
es,
wh
ich
can
actu
alize an
y advan
ced
cap
acities, I/
O
cells can
for t
h
e m
o
st p
a
rt ex
ecu
t
e th
e vo
ltage gu
id
elin
es
cho
s
e
b
y
p
l
ann
e
rs [3
]. Silicon
reg
i
on
n
e
ed
ed fo
r I/O
cells will b
e
e
ssen
tially in
creased
fo
r su
ppo
rting
exp
a
n
s
i
v
e nu
m
b
er o
f
measu
r
es and
m
o
reo
v
e
r t
o
increase
larg
e
nu
m
b
er of
g
a
ug
es
p
i
n cap
acitan
ce m
a
y in
crease
t
h
e num
b
e
r
o
f
p
i
ns, wh
ich
will
restrain
ex
ecu
tio
n.
4)
Ha
rd
wa
re D
e
scri
pt
i
o
n
La
n
gua
ge (
HDL
):
Har
d
w
a
re de
sc
ri
pt
i
o
n Lan
g
u
a
g
es (
H
D
L
) i
n
c
l
udes
VH
DL,
Veri
l
o
g, Sy
st
e
m
c and Ha
ndl
e-C
.
M
o
st
o
f
t
h
e t
i
e
we use
Han
d
l
e
C
for
FPG
A p
r
o
g
ra
m
m
i
ng. VH
D
L
and Ve
ri
l
o
g are devel
o
ped
fo
r i
n
d
u
st
ry
m
easure
s
.
HDL
‘s
have
n
u
m
e
rous sel
l
e
r
s
of
feri
ng
recr
eat
i
on an
d sy
n
t
hesi
s t
ool
s
[4]
.
B
e
ha
vi
o
u
ral
,
R
TL an
d st
ru
c
t
ural
lev
e
ls o
f
d
e
p
i
ctio
n
mig
h
t
b
e
u
tilized
b
e
tween
alterab
l
y in
th
ese d
i
alects. Syte
m
C
is
u
s
ed
fo
r
d
i
splayin
g
fram
e
wor
k
l
e
v
e
l
beha
vi
o
u
r
a
n
d
ha
ve C
++
b
a
sed l
i
b
rari
es.
As
pri
m
ary
l
a
ngua
ge
o
f
Sy
st
e
m
C
i
s
C
++, so
ft
ware
processes ca
n be m
o
re effectively de
m
onstrated whe
n
com
p
ared to conv
entional HDL
,
even
thou
gh
Syste
m
C
i
s
i
n
creasi
n
g t
h
ei
r
devel
o
pm
ent
but
do
es not
reac
h t
h
e de
vel
o
pm
ent
of
V
HDL
or
Veri
l
o
g sy
nt
hesi
s
p
r
od
u
c
ts. H
a
nd
el-
C
r
e
qu
ir
es th
e or
ig
i
n
ator
to
un
eq
ui
v
o
cal
l
y
depi
ct
p
a
ral
l
e
l
han
d
l
i
n
g s
qua
res i
n
si
de a
pr
oce
d
u
r
e.
It
i
n
cor
p
orat
es c
h
ar
act
eri
s
t
i
c
s fo
r
bet
w
ee
n m
e
t
h
o
dol
ogy
c
o
rres
p
on
de
nces.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
RES I
S
SN
:
208
8-8
7
0
8
An
Efficien
t
a
p
p
r
oa
ch
f
o
r
Desig
n
an
d Testing
o
f
FPGA Prog
ramming
u
s
ing
Lab
V
IEW
(B. Na
resh
K.R.)
19
4
In R
e
f.
[
3
]
Al
ast
a
i
r
M
.
S
m
i
t
h
descri
b
e
s ab
out
t
h
e
appl
i
cat
i
o
ns
o
f
g
e
om
et
ri
c pro
g
ram
m
i
ng
con
f
i
g
urat
i
o
n
of
h
o
m
ogene
o
u
s F
P
G
A
a
r
c
h
i
t
ect
ures a
n
d
c
o
nst
r
uct
s
on
an
expa
n
d
i
n
g
gr
o
u
p
o
f
wo
r
k
c
o
ncer
ne
d
wi
t
h
dem
onst
r
at
i
ng rec
o
n
f
i
g
ura
b
l
e
archi
t
e
c
t
ures an
d p
r
es
ent
s
a ful
l
reg
i
on an
d p
o
st
p
onem
e
nt
m
ode
l
of a
Reconfigura
b
l
e
De
vices.
B. Intr
od
ucti
o
n
t
o
L
a
b
V
IE
W:
National
In
stru
m
e
nts pr
o
v
ides
Lab
V
IE
W s
o
f
t
ware
(Lab
o
r
at
ory
Vi
rt
ual
Ins
t
rum
e
nt
at
i
on
E
ngi
neeri
n
g
Wo
r
kbe
nc
h),
whi
c
h pr
o
v
i
d
e
s
a pl
at
form
and
devel
opm
ent
envi
r
o
nm
ent
usi
ng
vi
sual
p
r
o
g
ram
m
i
ng l
a
ng
ua
ge.
LabVIEW
p
r
og
ramm
in
g
is perfect for an
y esti
m
a
t
i
o
n
o
r
co
n
t
ro
l
fram
e
wo
rk
, and
th
e heart of th
e
NI
o
u
tline
stag
e. Coord
i
natin
g
all th
e ap
p
a
ratu
ses th
at
sp
ecialists
a
n
d
r
e
s
e
ar
ch
e
r
s
n
e
e
d
to
a
s
s
e
mb
le
fo
r
an
ex
te
n
s
iv
e
v
a
riety o
f
uses in
d
r
astically l
e
ss ti
m
e
, Lab
V
IEW
is an
ad
van
ced
en
v
i
r
onmen
t f
o
r
critical thinking,
qui
cke
n
e
d
gai
n
s
,
and c
o
nst
a
nt
de
vel
o
p
m
ent
[5]
,
Lab
V
IE
W has
t
w
o sect
i
ons:
t
h
e fro
nt
pa
nel
and f
u
nct
i
o
nal
bl
ock
diagram
.
Functional bl
ock
diagram
is
a programming area and
front pane
l pr
ovide
s
an i
n
terface t
o
de
velop.
B
y
est
a
bl
i
s
hi
n
g
t
h
e
rel
a
t
i
o
ns
bet
w
ee
n
fr
ont
panel
a
n
d t
h
e F
unct
i
o
nal
bl
oc
ks,
ap
pl
i
cat
i
o
n
s
are
de
vel
o
pe
d.
Lab
V
IE
W
pr
o
g
ram
s
are t
e
rm
ed as Vi
rt
ual
Inst
r
u
m
e
nt
s, on t
h
e ot
her
h
a
nd
VI
. La
bV
I
E
W
h
o
l
d
s an
ex
h
a
u
s
tiv
e
set o
f
i
n
stru
m
e
n
t
s for
p
r
o
c
u
r
ing
d
i
ssectin
g, sh
owing
,
what's
m
o
re p
u
ttin
g away in
form
at
i
o
n
and
al
so
pr
ovi
de i
n
st
rum
e
nt
s w
h
i
c
h a
r
e
used
t
o
t
r
ou
bl
es
ho
ot
t
h
e
code
.
W
h
en LabVI
E
W
o
p
en
s, it sho
w
s two
w
i
ndow
s if
o
n
e
w
a
n
t
s to
wr
ite an
y
p
r
og
r
a
m
in
Lab
V
I
E
W
,
f
i
r
s
t
i
n
t
h
at
pr
o
g
ra
m
,
operat
i
o
n i
s
f
o
u
n
d
out
,
t
h
at
ope
rat
i
o
n
w
e
d
r
aw
as
Gra
phi
cal
Di
ag
ra
m
i
n
Fu
nct
i
o
n
a
l
bl
oc
k
di
ag
ram
wi
ndo
w t
h
en
we can
gi
ve i
n
p
u
t
s
(c
ont
rol
)
a
nd
out
put
(i
ndi
cat
o
r)
i
n
fr
ont
pa
nel
,
aft
e
r assi
g
n
i
n
g
,
we
have
t
o
c
o
nnec
t
t
h
ro
u
g
h
wi
re
fr
om
i
nput
s
(c
ont
rol
)
t
o
fu
nc
t
i
on a
n
d
f
unct
i
on
t
o
out
p
u
t
(I
ndi
cat
o
r
)
.
La
b
V
I
E
W
pr
o
v
i
d
es a
n
e
n
vi
r
onm
ent
fo
r
pr
o
g
ram
m
i
ng,
whi
c
h i
s
use
d
fo
r
un
de
rg
rad
u
a
t
e
engi
neeri
n
g t
r
ai
ni
n
g
[
6
]
.
It
al
s
o
of
fers
hel
p
f
o
r dat
a
acqui
si
t
i
on har
d
ware
,
m
u
l
t
i
t
a
ski
n
g
,
i
nhere
nt
l
i
b
r
a
ri
es and
basi
c
m
eani
ng of
cl
i
e
nt
interfaces
and i
s
ge
nerally util
ized withi
n
e
x
pert
building.
2.
FPGA P
R
OG
RAMMING
FPG
A stan
ds
fo
r "Field P
r
o
g
ram
m
able Gate Array
"
.
FPGA essen
tially co
nsis
ts of la
rge a
rray
of
gat
e
s
whi
c
h a
r
e p
r
o
g
ram
m
abl
e
and
ca
n
be
rec
o
n
f
i
g
ure
d
any
t
im
e any
w
here
. "La
r
ge
a
rray
of
gat
e
s"
i
s
an
o
v
e
rsim
p
lified
d
e
scri
p
tio
n
o
f
FPGA
[7
]. FPGA is to b
e
su
r
e
co
nsi
d
e
r
a
b
l
y
m
o
re per
p
l
e
xi
n
g
t
h
an
basi
c
sh
ow
o
f
Gates.
At th
e sam
e
ti
me th
e fact
is, there are num
e
rous doors i
n
si
d
e
t
h
e FP
GA
,
whi
c
h co
ul
d
b
e
sel
f
-
assertively ass
o
ciated togethe
r
to m
a
ke a ci
r
c
ui
t
of
y
o
u
r
de
ci
si
on.
FP
GAs
are fa
bri
cat
e
d
by
o
r
ga
ni
zat
i
o
ns l
i
k
e
Xilin
x
,
Altera, Actel an
d
so
o
n
. FPGA‘s are in
a b
r
o
a
d
sen
s
e lik
e CPLD‘s yet CPLD‘s are little in
si
ze an
d
capacity contra
sted
with FPGA.
Veri
l
o
g i
s
a H
a
rd
ware
Desc
r
i
pt
i
on La
ng
ua
ge (
HDL
) w
h
i
c
h co
ul
d
be ut
i
l
i
zed t
o
po
rt
ra
y
adva
nced
circu
its in
a tex
t
b
a
sed
way.
We h
a
v
e
to
com
p
o
s
e
o
u
r
syst
e
m
fo
r FPGA
u
tilizin
g
a HDL lik
e Verilo
g. Befo
re
HDL
‘s
we
re
f
a
m
ous,
speci
al
i
s
t
s
m
a
de use
of
eve
r
y
t
hi
n
g
with
sch
e
m
a
tic
s.
Wh
ich
are rad
i
an
tly sim
p
l
e
with
litt
le
o
u
tlin
es, yet
are
ex
cru
c
iatin
g
l
y
un
m
a
n
a
g
eab
le fo
r an ex
p
a
n
s
i
v
e d
e
sig
n
.
Ex
am
p
l
e:
Pr
io
rity
en
co
d
e
r
I
n
FPGA
Pro
g
r
a
mmin
g
U
s
ing
V
e
r
ilog
,
VHDL
Pri
o
ri
t
y
encod
e
r i
s
a ci
rcui
t
t
h
at
conve
rt
s enco
de
d i
n
put
s t
o
t
h
e
b
i
nary
fo
rm
. The bi
na
ry
rep
r
ese
n
t
a
t
i
on
of
ori
g
i
n
al
n
u
m
ber from
pri
o
ri
t
y
enco
der ci
rcu
it represen
t fro
m
zero
to
mo
st sign
ifican
t
b
it. By
actin
g
o
n
h
i
ghest p
r
i
o
rity requ
est th
ey con
t
ro
l in
terrup
t
requ
ests.
An 8-b
it prio
rity en
cod
e
r is circu
it
wh
ich is us
e
d
fo
r co
nv
er
tin
g a
n
en
c
o
d
e
d
in
pu
t to
a b
i
n
a
r
y
represen
tatio
n
.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
089
-48
64
I
J
RES Vo
l. 4
,
N
o
. 3
,
No
v
e
m
b
er
201
5
:
1
92
–
20
0
19
5
Fi
gu
re
2.
B
a
si
c Di
ag
ram
& Tr
ut
h
Tabl
e
Dep
e
nd
ing
on
th
e no
of d
a
ta in
pu
t lin
es th
e
d
i
g
ital en
cod
e
r p
r
o
d
u
ce
2
,
3,
4
b
it ou
tpu
t
lin
es. An
n-b
it
enco
de
r ci
rc
ui
t
has
2
n
i
n
p
u
t
l
i
n
es a
n
d
n
-
bi
t
out
put
a
n
d i
n
cl
ude
co
n
f
i
g
urat
i
ons
l
i
k
e
4-t
o
-
2
, 8
-
t
o
-3
an
d
1
6
-
t
o
-
4
l
i
n
e.
A bi
na
ry
equi
val
e
nt
of
i
n
p
u
t
val
u
e
‗
1
‘
i
s gene
rat
e
d
by
t
h
e enc
o
der
as
o
u
t
p
ut
. T
h
e bi
nary
e
qui
val
e
n
t
t
hus
gene
rat
e
d
i
s
a
v
ai
l
a
bl
e t
o
enc
ode ei
t
h
er i
n
d
ecim
a
l or hexa
deci
m
a
l i
nput
pat
t
e
rn as (
b
i
n
ary
code
d deci
m
a
l
)
BCD b
it.
A
)
VH
DL
COD
E
:
En
tity p
r
iority-en
c
od
er_8
-3
is
Po
rt
(a: in log
i
c_
v
ect
o
r
(7
d
o
wn to
0);
b:
o
u
t
l
ogi
c
_
v
ect
or
(2
d
o
w
n
t
o
0)
);
en
d pr
ior
ity-
e
nco
d
e
r_
8-
3
;
Arc
h
i
t
ect
ure
B
e
havi
oral
of
p
r
i
o
ri
t
y
_enc
o
d
er
_8
_
3
i
s
begi
n
Process (a)
begi
n
i
f
a(
0)='
1'
t
h
en
b<="0
0
0
";
el
sei
f
a(
1)='
1'
t
h
en
b<="
0
01";
el
sei
f
a(2
)
='
1'
t
h
en
b
<="01
0";
el
sei
f
a(3
)
='
1'
t
h
en
b
<="01
1";
el
sei
f
a(4
)
='
1'
t
h
en
b
<="10
0";
el
sei
f
a(5
)
='
1'
t
h
en
b
<="10
1";
el
sei
f
a(6
)
='
1'
t
h
en
b
<="11
0";
el
sei
f
a(7)='1
'
th
en
b<="1
1
1
"
; else
n
u
ll;
end if;
en
d pro
cess;
B) Verilog
Cod
e
:
m
odul
e p
r
i
(a
,b
);
in
pu
t [7
:0
] a;
ou
tpu
t
[
2
:0
] b
;
r
e
g [2
:0
]
b;
always@(a
)
begi
n
i
f
(a
[0]
)
b<=
3'
b0
0
0
;
else if
(
a
[
1
]) b
<= 3
'
b
001
;
else if
(
a
[
2
]) b
<= 3
'
b
010
;
else if
(
a
[
3
]) b
<= 3
'
b
011
;
else if
(
a
[
4
]) b
<= 3
'
b
100
;
else if
(
a
[
5
]) b
<= 3
'
b
101
;
else if
(
a
[
6
]) b
<= 3
'
b
110
;
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
RES I
S
SN
:
208
8-8
7
0
8
An
Efficien
t
a
p
p
r
oa
ch
f
o
r
Desig
n
an
d Testing
o
f
FPGA Prog
ramming
u
s
ing
Lab
V
IEW
(B. Na
resh
K.R.)
19
6
else if
(
a
[
7
]) b
<= 3
'
b
111
;
else
b <=
3'
bx
x
x
;
end
end
m
odul
e
In th
is ex
am
p
l
e, I am
ex
p
l
ainin
g
Verilo
g Cod
e
in Xilinx
as
sh
own
as Figu
re 3
Fi
gu
re
3.
Pri
o
ri
t
y
Enco
der
co
d
e
i
n
XIL
I
NX
After
writing the code in
Xilinx to synthesize
the proble
m
it shows
erro
rs/
w
arning (If in this
p
r
og
ram
h
a
v
i
ng
erro
rs/warn
i
n
g
s
)
o
r
R
u
n
n
i
n
g
(it con
t
ain
s
p
e
rfect cod
e
). After co
m
p
etitio
n
o
f
sy
n
t
h
e
size b
y
cl
i
c
k o
n
Vi
ew
R
TL Sc
hem
a
tics as s
h
o
w
n as
Fi
gu
re
4.
Fi
gu
re 4.
R
TL Schem
a
t
i
c
s
After chec
king the e
r
rors
we
can e
x
ecu
te the prog
ram
in
Mo
d
e
lsim
o
u
t
pu
t wav
e
form
s as shown as Fi
g
u
re
5
.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
089
-48
64
I
J
RES Vo
l. 4
,
N
o
. 3
,
No
v
e
m
b
er
201
5
:
1
92
–
20
0
19
7
Fi
gu
re 5.
O
u
t
p
ut
W
a
ve
fo
rm
s
If o
n
e wa
nts p
r
o
g
ram
Execut
e
in hard
wa
re kit (Spa
rtan 3
E
FPG
A Start
e
r kit, Spa
r
tan
6
FP
GA Kit)
y
ou
have t
o
c
r
eat
e UC
F fi
l
e
by
usi
n
g
gen
e
rat
i
ng
Pr
og
ra
m
m
i
ng fi
l
e
. U
s
er C
o
nst
r
ai
n Fi
l
e
s are Am
eri
can
Standa
r
d
Co
de
fo
r I
n
fo
rm
ation
I
n
terc
han
g
e
(A
SCII
)
f
iles sp
ecif
y
ing
co
nstr
ain
t
s on
t
h
e lo
g
i
cal design. Yo
u
can create t
h
es
e files and ent
e
r your
I/
O int
e
rfaces
with a
n
y text editor
Base
d on
hardware
kit. If you wa
nt
C
o
m
p
l
e
t
e
Sy
stem
of
Test
i
n
g
FPG
A e
x
pl
ai
n
e
d
[8]
.
O
n
e al
s
o
uses t
h
e C
o
nstraints E
d
itor
to create
const
r
aints
within
UCF
files. T
h
ese c
ons
traints affect how t
h
e logi
cal
design is im
ple
m
ented in t
h
e
target
device.
These
Fi
l
e
s are
use
d
t
o
ove
rri
de c
o
n
s
t
r
ai
nt
s s
p
eci
fi
ed
du
ri
n
g
desi
gn
ent
r
y
Th
e Xilinx
software still u
s
es "last co
n
s
traint wi
n
s
" m
u
ch
sa
m
e
as HDL/NCF/UCF/PCF
p
r
o
cessi
n
g
.
Presen
tly,
th
e UCF files
are h
a
nd
led with
t
h
e requ
est
i
n
wh
ich
t
h
ey are add
e
d
to th
e Task (eit
h
e
r i
n
the
Pro
j
ect
Na
vi
g
a
t
o
r o
r
vi
a Tc
l
co
m
m
and), a
nd i
t
has n
o
b
eari
n
g o
n
t
i
m
e
st
am
ps or t
h
e
or
der i
n
whi
c
h t
h
e
doc
um
ent
a
t
i
o
n
were a
d
ju
st
ed, a
u
t
o
m
a
t
i
c
gene
rat
i
o
n o
f
VH
DL c
o
de [
9
]
,
UM
L
di
ag
ram
s
expl
ai
ne
d h
o
w
sy
nt
hesi
ze
i
n
VH
DL [
10]
Fi
gu
re 6.
Loa
d
i
ng UC
F
Fi
l
e
After creating UCF
file, we h
a
v
e
to
con
n
ect
h
a
rdw
a
re k
it. Th
en up
lo
ad
th
e pr
og
r
a
m
u
s
i
ng
DI
GIL
E
N
T
s
o
f
t
ware.
Based
o
n
c
ode
P
r
o
g
ra
m
will be e
x
ec
uted
3.
PROBLEM DESCRIPTION
In t
h
i
s
resea
r
ch
we are goi
ng t
o
pr
o
p
o
s
ed t
h
e
FPG
A Pr
og
ra
m
s
usi
ng G
r
ap
hi
cal
Lang
ua
g
e
rat
h
er t
h
a
n
V
e
r
ilog
,
VHDL w
ith th
e
h
e
lp of
Lab
V
I
E
W
.
Based
o
n
fo
llowing
p
o
i
n
t
s we
will
ex
ecu
t
e FPGA
p
r
o
g
ram
in
Lab
V
IEW.
i) La
unc
h
Lab
V
IE
W
so
ftwa
r
e
i
i
)
D
r
aw
G
r
a
p
hi
cal
di
a
g
ram
in B
l
oc
k
Di
ag
ra
m
W
i
nd
o
w
iii) Insert
DAQ
Assistan
ts
for inpu
t (Acqu
i
re sign
al) an
d ou
tpu
t
(g
en
erati
n
g Sign
al)
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
RES I
S
SN
:
208
8-8
7
0
8
An
Efficien
t
a
p
p
r
oa
ch
f
o
r
Desig
n
an
d Testing
o
f
FPGA Prog
ramming
u
s
ing
Lab
V
IEW
(B. Na
resh
K.R.)
19
8
iv
)
Select in
pu
t
po
rt lin
es and
o
u
t
p
u
t
po
rt lines
v
)
DAQ
A
ssistan
t g
i
v
e
s sing
l
e
in
pu
t an
d sing
le ou
tpu
t
W
i
t
h
th
e
help
o
f
In
d
e
x
array an
b
u
ild
array we will
d
e
sign
m
o
re
th
an
on
e in
pu
t
and
on
e o
u
t
p
u
t
vi) C
o
m
p
etitio
n
of Graphical
diagram
conne
ct FPGA
Kit
vii) E
x
ec
ute the program
LabVIE
W program
s
are also called as Virtual Instru
m
e
nt
s, or V
I
s,
beca
us
e i
t
seem
s & o
p
erat
i
o
n l
i
k
e
as ph
ysical elemen
t o
r
orig
inal ele
m
en
t, su
ch
as
o
s
cillo
scop
es and
m
u
lti
meter’s (b
ased on
inpu
t o
s
cillo
sco
p
e
will ch
ang
e
).
LabVIEW prov
id
es a co
m
p
l
e
te set o
f
to
o
l
s fo
r an
alysing
,
d
i
sp
layin
g
, and
sto
r
i
n
g
d
a
ta
an
d
for
t
r
o
ubl
es
ho
ot
i
n
g t
h
e
co
de.
Wh
en
Laun
ch
LabVIEW,
in
itially
sh
o
w
s
―
Gettin
g
Started
ǁ
w
i
n
dow
.
A
s
sh
own
as
Figu
re 7
.
Fig
u
re 7
.
Lab V
I
EW G
e
ttin
g Started
Window
To create a ne
w VI, select Blank
V
I
(i
.e.
LabV
IE
W
pr
og
ram
s
st
or
ed in VI) or to
create a new
LabVIE
W
project and select
Em
pty project.
On cl
i
c
ki
ng t
h
e bl
an
k VI i
t
s
h
o
w
s t
w
o wi
n
d
o
w
s
one i
s
f
r
ont
p
a
nel
wi
nd
ow a
nd t
h
e ot
her i
s
bl
ock
d
i
agram
win
dow.
Fron
t p
a
n
e
l
is th
e u
s
er i
n
t
e
rface co
m
p
onen
t
an
d th
e b
l
ock
d
i
agram
sh
o
w
s th
e fun
c
tio
n
a
lity
o
f
pr
ogr
am
.
Exam
pl
e:
Pri
o
r
i
t
y
encode
r In
FPG
A Pr
og
ra
m
m
i
ng
Usi
n
g Gra
p
hi
cal
Lan
gua
ge
Whe
n
we l
a
un
ch La
b
V
IE
W.
we
have
t
o
i
n
s
e
rt
D
A
Q
A
ssi
s
t
ant
i
n
B
l
oc
k
d
i
agram
wi
nd
o
w
.
Figure
8. DAQ Assistant
B
y
keepi
n
g t
h
i
s
Fu
nct
i
o
n o
n
t
h
e bl
oc
k di
a
g
r
a
m
,
a new t
a
s
k
i
s
creat
ed
by
DA
Q
Assi
st
ant
,
an
d f
o
r co
nt
i
n
u
o
u
s
measurem
ent or
gene
ration a
While loop
is
placed around
DAQ As
sistant.
To
m
a
k
e
th
e task
g
l
ob
ally accessib
l
e from
any a
pplication, y
o
u m
u
st co
n
v
e
r
t
th
e Ex
press VI
to
an
NI
-D
AQ
task
sav
e
d in
MA
X
[1
1-
12
].
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
089
-48
64
I
J
RES Vo
l. 4
,
N
o
. 3
,
No
v
e
m
b
er
201
5
:
1
92
–
20
0
19
9
Y
o
u
can
g
e
n
e
r
a
te N
I-D
AQm
x
A
P
I
cod
e
f
r
o
m
a D
A
Q
A
ssistan
t Exp
r
ess VI
.
Righ
t click
on
the DAQ
Assi
st
ant
E
x
p
r
ess
VI
an
d s
e
l
ect
gene
rat
e
NI
-
D
A
Q
m
x
C
ode
f
r
om
t
h
e sh
ort
c
ut
m
e
nu
t
o
ge
nerat
e
b
o
t
h
configuration a
n
d exam
ple code
for the
task.
In
o
u
r
E
x
am
ple Pri
o
ri
t
y
enc
o
der
has
8
i
n
put
s an
d
3
o
u
t
p
ut
s t
h
en
we
can
u
s
e I
nde
x a
rray
and
B
u
i
l
d
ar
ra
y
.
IN
DE
X
AR
R
AY:
It
co
nt
ai
n
s
n
-
di
m
e
nsi
ona
l
array
.
If
n
d
i
m
ensi
onal
a
rra
y
cont
ai
n
s
no
e
l
em
ent
s
t
h
en s
u
b
ar
ray
prese
n
t
i
n
I
N
D
E
X
AR
R
A
Y
r
e
t
u
r
n
s t
h
e
d
e
fa
ul
t
val
u
e
of t
h
e
de
fi
ne
d
dat
a
t
y
pe. T
h
e
n
u
m
b
er
of i
nde
x i
n
p
u
t
s
i
n
t
h
e ar
ray
m
a
t
c
hes t
h
e
num
ber
o
f
di
m
e
nsi
ons
i
n
n
-
di
m
e
nsi
onal
array
.
In
de
x array
Fu
nct
i
on C
ont
ai
n
s
n-
Di
m
e
nsi
on array
,
i
nde
x a
c
t
s
as cont
rol
s
and el
em
ent
o
r
su
b arra
y
act
s as i
ndi
cat
o
r
. I
n
ou
r Exam
pl
e 8-
bi
t
pa
ri
t
y
enco
de
r t
h
en
we can set
8-
D
i
m
e
nsi
on ar
ray
we are
gi
vi
n
g
In
de
x
(0 to
7
)
, Th
en
au
to
m
a
tical
ly i
t
g
e
n
e
rates
8
el
e
m
en
ts o
r
su
b
arrays.
BUILD ARR
A
Y: It h
a
s on
ly in
pu
t av
ailab
l
e
u
pon
th
e p
l
acemen
t
o
f
fu
n
c
ti
o
n
. To
add
in
pu
t to
th
e nod
e mak
e
a
ri
g
h
t
cl
i
c
k an
d
sel
ect
t
h
e opt
i
on
A
dd
In
p
u
t
f
r
om
t
h
e
m
e
nu
i
f
y
ou
wi
re c
o
nt
r
o
l
refe
renc
e
s
of
di
f
f
ere
n
t
c
l
asses
to
th
is
fun
c
tion.
The B
u
i
l
d
Ar
r
a
y
funct
i
o
n c
ont
ai
n El
em
ent
and A
rray
a
c
t
s
as C
ont
r
o
l
s
appe
n
d
ed a
r
ray
act
s as
In
di
cat
or
. I
n
o
u
r e
x
am
pl
e 8-bi
t
pari
t
y
enco
der
gi
ves 3
ou
t
put
s t
h
e
n
we
can set
3 el
em
ent
s
i
n
B
u
i
l
d
a
rray
i
t
Appe
nde
d a
rra
y connects t
o
t
h
e
DAQ
Assist
ant2
data.
Aft
e
r c
o
nst
r
uct
i
ng i
n
de
x array
and B
u
i
l
d
a
rra
y
i
n
bl
ock
di
ag
ram
wi
ndo
w t
o
dra
w
G
r
ap
hi
c
a
l
di
agram
.
In
p
r
i
o
ri
t
y
enc
ode
r t
o
t
a
l
gr
ap
hi
cal
di
a
g
ram
in B
l
oc
k
Di
ag
ra
m
wi
ndo
w a
n
d
Lab
V
I
E
W as s
h
o
w
n as
fi
g
u
r
e
.
Fi
gu
re
9.
Pri
o
ri
t
y
enco
der
G
r
a
phi
cal
di
ag
ram
i
n
La
b
V
IE
W
Fig
u
re 10
. Priority
en
cod
e
r
Graphical diagra
m
in W
i
ndow
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
RES I
S
SN
:
208
8-8
7
0
8
An
Efficien
t
a
p
p
r
oa
ch
f
o
r
Desig
n
an
d Testing
o
f
FPGA Prog
ramming
u
s
ing
Lab
V
IEW
(B. Na
resh
K.R.)
20
0
4.
RESULT
Whe
n
we
do
F
P
G
A
P
r
o
g
ram
m
i
ng i
n
La
b
V
I
E
W
rat
h
er t
h
a
n
Veri
l
o
g
or
V
HDL
B
a
sed
o
n
Pr
oced
u
r
e
easily we g
e
t
resu
lts rat
h
er t
h
an
Trad
ition
a
l
p
r
og
rammin
g
Lang
u
a
g
e
i
n
prio
rity en
cod
e
r after co
m
p
etit
io
n
of
Gra
p
hi
cal
Di
a
g
ram
we
have
t
o
c
o
n
n
ect
F
P
G
A
Ki
t
an
d
R
u
n
t
h
e
Lab
VIE
W
,
i
t
sh
o
w
s i
n
p
u
t
a
n
d
out
put
i
n
FPGA Kit
and
Fron
t p
a
n
e
l W
i
n
dow.
Resu
lt
in
LabV
IE
W as
sh
ow
n a
s
fi
g
u
r
e
1
1
in
La
bV
I
E
W
.
5.
CO
NCL
USI
O
N
Lab
V
IE
W FP
GA si
de-st
e
ps
t
h
e need f
o
r VH
DL
or Ve
r
i
l
og k
n
o
w
l
e
dg
e and al
l
o
ws no
vi
ces a
n
d
expe
rt
s al
i
k
e t
o
t
a
ke
ad
va
nt
a
g
e
of
FP
GA
h
a
rd
ware
. La
b
V
IE
W FP
G
A
e
m
pl
oy
s G p
r
o
g
r
am
m
i
ng an
d
p
r
o
v
i
d
es
a hi
g
h
l
e
vel
of
abst
ract
i
o
n f
o
r
t
r
ansl
at
i
ng si
g
n
al
pr
ocessi
ng
al
go
ri
t
h
m
s
t
o
code t
h
at
can r
u
n o
n
ha
rd
wa
re.
The
envi
ro
nm
ent
pr
ovi
des
p
o
we
r
d
e
bu
g a
n
d c
o
m
p
i
l
a
t
i
on feat
u
r
es
t
o
hel
p
s
ease
FPG
A a
p
pl
i
cat
i
on
de
vel
o
pm
ent
.
REFERE
NC
ES
[1]
S. Belka
cem
i,
K. Benkrid, A
.
Benkrid, “
E
ffi
ci
ent FP
GA hardware deve
lopm
e
n
t: A m
u
lti-lan
guage appro
ach
”,
Journal of Syst
e
m
s
Ar
chite
ctur
e
, 53, (2007), 184
–209.
[2]
The Xilinx HDL Homepage. Available from: h
ttp
://www.xilinx
.
co
m/labs/lav
a
/ind
e
x.htm.
[3]
George A, Alas
tair M. Sm
ith,
Mem
b
er IEEE
,.
Constan
tinid
es, Senior Member, IEEE,
and Peter Y.K. Ch
eun
g
,
S
e
nior Mem
b
er, IEEE, “
F
P
GA
Archite
cture Opt
i
m
i
zation Using Geom
etric P
r
ogram
m
i
ng”,
IEEE T
r
ansactions
on
Computer-Aided
Design of Inte
grated C
i
rcuits an
d Systems
, Vol.
29, No. 8, August 2010.
[4]
VHDL
Languag
e
guide,
http://ece.wpi.ed
u
/~wrm/Courses
/
EE3810/g
e
ninf
o/Welcome%20
%20the%20
VHDL%20Languag
e
.pdf.
[5]
Brunini, Marilza A. Lemos Da
nilo M. Galden
oro Botura
Jr.
Ma
rc
io A.
Ma
rque
s Luiz
Ca
rlos Rosa
,
“
V
irtua
l
Instrumentation
:
A Practical Ap
proach
to Con
t
r
o
l and
Supervis
ion Process”, 2
011 Intern
ation
a
l Confer
ence on
Computer Scien
ce
and Network
Techno
lo
g
y
978
-1-4577-1587-7/11/$26.00 ©201
1 IEEE.
[6]
B.M. Dunkin
an
d T.L. Schwartz,
“Facilitating in
terdisciplin
ar
y
h
a
nds-on learning
using LabVIEW”,
Int. J. Eng
.
Educ
., vo
l. 16, n
o
. 3
,
pp
. 218–22
7, 2000
.
[7]
Aiwu Ruan, Bairui Jie, Li Wan, J
unhao Yang, Chuan
y
in Xiang
,
Zujian Z
hu, Y
u
Wang, “A bitstream readback
-
based
au
tomatic function
a
l test
and
diagnosis method for Xilinx F
P
GAs”,
Microel
ectroni
cs Re
liabi
lity
(2014)
.
[8]
Ignacio
Bravo,
Alfredo Garde
l
,
Beatr
i
z P
e
r
e
z
,
J
o
s
e
Luis
Lázaro, Jorge García, D
a
vid Sa
lido, “A new approach to
evalu
a
ting
int
e
rn
al Xi
linx F
P
GA res
ources
”
,
Jour
nal of Systems
Architecture
, 57, (
2011), 749–760
.
[9]
P. Martín a
,
∗
, E. Buenoa, Fco
.
J. Rodríguez
a,
O. Machadoa, B.
Vuksanovic, “A
n FPGA-based
approach
to th
e
automatic gener
a
tion of VHDL code for industrial c
ontrol s
y
stems applicatio
ns
: A case stu
d
y
of MSOGIs
implementation”,
Math
ematics a
nd Computers in
Simulatio
n
, 91 (
2013), 178–192
.
[10]
Stephen K. Wood, David H.
Akehurst, Oleg Uzenkov, W.
Gareth
J. Howells, and
Klaus D. McDonald-Maier, “A
Model-Driven Development
A
pproach to
Mapping
UML State Diagrams to
S
y
nthesizable VHDL”.
IE
EE
Transactions on
Computers
, Vol. 57, No. 10
, October 2008.
[11]
Ho Mann,
H.
G.
Essel,
N. Kurz,
R.
S.
May
e
r,
W.
Ott,
D. Schall, “The n
e
w data
acquisition s
y
stem
at GSI”,
I
EEE
Trans. Nucl. Sci
., vol. 43
, no
. 1
,
p
p
. 132–135
, Feb
.
1996
[12]
H Pichlik and R
.
Jam
a
l,
LabVIEW Applications
and Solutions
.
Englewood Cliffs, NJ: Pren
tice-Hall, 1999
, see
also
http://www.
ni.
c
om/
Evaluation Warning : The document was created with Spire.PDF for Python.