Intern
ati
o
n
a
l
Journ
a
l of
Re
con
f
igur
able
and Embe
dded
Sys
t
ems
(I
JRES)
V
o
l. 3,
N
o
.
2
,
Ju
ly 20
14
, pp
. 49
~53
I
S
SN
: 208
9-4
8
6
4
49
Jo
urn
a
l
h
o
me
pa
ge
: h
ttp
://iaesjo
u
r
na
l.com/
o
n
lin
e/ind
e
x.ph
p
/
IJRES
Desi
gn of AES Algorithm for 12
8/192/256 Key Length in FPGA
Pravin V. Kin
g
e
1
, S.
J. Honale
2
, C.
M.
Bob
a
de
3
1
Department of Electronics
an
d
Tel
ecom
m
unicat
ion
Eng
i
neer
ing
G.H. Ra
isoni Co
lleg
e
of
E
ngin
e
ering, Amravati, I
ndia
2,3
F
acult
y
of
Ele
c
troni
cs
and
Te
l
ecom
m
unication
Engin
eering
G.H. Ra
isoni Co
lleg
e
of
E
ngin
e
ering, Amravati, I
ndia
Article Info
A
B
STRAC
T
Article histo
r
y:
Received Feb 22, 2014
Rev
i
sed
May
5, 201
4
Accepted
May 20, 2014
The cr
yp
tograp
hic algor
ithm
s
can be
implemented with softw
a
re or built
with pure hard
ware. However
Field
Programmable Gate Array
s
(FPGA)
implementation
offers quicker
solution and can be easily
upgraded to
incorporate an
y
protocol ch
anges. The availab
l
e AES algorithm is used for
data and
it is als
o
suitable for im
age en
cr
y
p
tion
and decr
y
p
tion
to
protect
the
confiden
tial image from an una
uthorized
access. This project proposes a
method in which the image d
a
ta is an input
to AES algorithm,
to
obtain
the
encr
y
p
ted image, and th
e en
cr
y
p
ted imag
e is th
e input to AES Decr
y
p
tion
to
get th
e origin
al
image.
This pro
j
ect proposed to
implement th
e
128,192 &
256 bit AES algorithm for data encr
y
p
tion and decr
y
p
tion, also
to compare
the speed of operation, efficien
cy
,
security
and
frequency
.
Th
e proposed
work will b
e
s
ynthesiz
e
d and
si
m
u
lated on
FPGA fam
i
l
y
of Xi
li
nk ISE 13.2
and Modelsim
tool respe
c
tiv
el
y in Ve
r
y
hig
h
s
p
eed int
e
gr
ated
circu
i
t
Hardware Descr
i
pti
on Languag
e
(VHDL).
Keyword:
AES
C
i
phert
e
x
t
FPGA
Plaintext
VH
DL
Copyright ©
201
4 Institut
e
o
f
Ad
vanced
Engin
eer
ing and S
c
i
e
nce.
All rights re
se
rve
d
.
Co
rresp
ond
i
ng
Autho
r
:
Pra
v
in V.
Ki
ng
e,
PG
St
u
d
ent
,
D
e
part
m
e
nt
of
E
l
ect
roni
cs
an
d t
e
l
ecom
m
uni
cati
on
En
gi
nee
r
i
n
g,
G. H.
Raison
i Co
lleg
e
o
f
Engin
eering
,
Am
rav
a
ti.
Em
a
il: Kin
g
e
.p.v@g
m
a
il.co
m
1.
INTRODUCTION
In
co
mm
u
n
i
catio
n
security is th
e m
o
st i
m
p
o
r
tan
t
fact
o
r
during
19
cen
t
ury. Th
e
d
a
ta secu
rity is th
e
bi
g i
s
s
u
e i
n
va
r
i
ous
fi
el
d s
o
us
g
ove
rnm
e
nt
i
n
vi
t
e
d t
h
e
ne
w c
r
y
p
t
o
gra
p
hy
co
ncept
.
F
o
r sec
u
re com
m
uni
cat
i
o
n
i
n
st
ead o
f
D
E
S al
go
ri
t
h
m
,
t
h
e di
sad
v
ant
a
ge
of D
E
S al
g
o
ri
t
h
m
i
s
onl
y
56
bi
t
key
.
It
s l
e
ngt
h easy
t
o
b
r
eak so
t
h
e ne
w
AE
S a
l
go
ri
t
h
m
i
s
devel
o
ped
by
Joa
n
Daem
en an
d Vin
c
en
t Rij
m
en
th
is algo
rithm
is ap
prov
ed
b
y
us
n
a
tio
n
a
l i
n
stitute o
f
stand
a
rd
& techn
o
l
o
g
y
i
n
Octob
e
r
20
00
. Th
e
b
a
sic
o
f
AES Rijn
d
ael
are in
a m
a
th
ematical
co
n
c
ep
t called as Galo
is field
th
eory. Si
milar to
th
e way DES
functio
n
,
Rijnd
a
el also
u
s
ed
t
h
e b
a
sic
tech
n
i
qu
es of
su
bstitu
tio
n
and
tran
sp
ositio
n (i.e. p
e
rm
u
t
at
io
n). Th
e
k
e
y
size and
th
e plain
tex
t
b
l
o
c
k size
deci
de
ho
w m
a
ny
r
o
u
n
d
s nee
d
t
o
be exec
ut
e
d
. T
h
e m
i
nim
u
m
num
ber of
r
o
u
n
d
s i
s
1
4
.
O
n
e key
di
ffe
re
n
t
i
a
t
o
r
bet
w
ee
n DES
and
pr
ovi
des f
o
r m
o
re opt
i
m
ized ha
rd
ware
a
nd s
o
ft
ware i
m
pl
em
ent
a
t
i
on of t
h
e al
go
ri
t
h
m
.
AES
al
go
ri
t
h
m
has f
i
x bl
ock
si
ze 1
28
bi
t
an
d
key
si
ze 12
8,
1
9
2
a
nd
2
5
6
bi
t
.
AE
S al
g
o
ri
t
h
m
im
pl
em
ent
e
d by
usi
n
g
har
d
ware an
d s
o
ft
ware by
usi
ng s
o
ft
ware i
t
i
s
easy
t
o
im
pl
em
ent
e
d t
h
e AE
S al
go
ri
t
h
m
an
d i
t
i
s
easy l
o
w cost
but
i
t
i
s
not
ful
l
y
secured m
o
s
t
secure.
AES
al
go
ri
t
h
m
i
s
ap
plied data as
well as im
age every im
age defi
ne in
p
i
x
e
l co
ncorn
in
ten
s
ity v
a
lu
e (d
ig
itel nu
m
b
er) and
lo
cation
ad
dress in
t
h
e
form
o
f
row an
d co
l
u
m
n
. Th
e
ap
p
lication
s
o
f
th
e im
ag
e p
r
ocessin
g
h
a
v
e
been
co
mm
o
n
l
y
foun
d in
t
h
e
Military co
mmu
n
i
cation
,
Foren
s
ics,
Ro
bo
tics, In
tellig
en
t syste
m
s etc. In
t
h
is p
r
oject, th
e AE
S alg
o
rith
m
is p
r
op
o
s
ed
wh
ich
is an
efficien
t sch
e
me
fo
r
bot
h
har
d
w
a
re a
n
d
so
ft
wa
re i
m
pl
em
ent
a
ti
on.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
089
-48
64
IJR
E
S V
o
l
.
3, No
. 2,
J
u
l
y
20
1
4
:
4
9
– 53
50
AES algorithm
An
enc
r
y
p
t
i
o
n
al
go
ri
t
h
m
conve
rt
s a
pl
ai
n
t
e
xt
m
e
ssage i
n
t
o
ci
p
h
er
t
e
xt
m
e
ssage
whi
c
h ca
n
b
e
recovere
d
only by a
u
thorize
d
receive
r
using a dec
r
yp
tion t
echni
que
. T
h
e
AES-Rijndael
algorithm
[4] is a
n
iterative pri
v
ate key symmetric bloc
k ci
pher. T
h
e inpu
t
and output for the AES
algorithm
each consist of
sequ
en
ces
of
1
2
8
b
its (
b
l
o
ck
leng
th)
.
H
e
n
ce Nb
= Block
leng
th
/32
= 4
.
Th
e Ciph
er
K
e
y fo
r
t
h
e A
E
S
al
go
ri
t
h
m
i
s
a
seq
u
ence
of
12
8,
19
2 o
r
2
5
6
bi
t
s
(Key
l
e
ng
th
). In
th
is i
m
p
l
e
m
en
tatio
n
,
the k
e
y len
g
t
h
is 1
28.
Hence
N
k
=
K
e
y
l
e
ngt
h/
3
2
=
4
.
Encry
p
tion Pr
ocess
The Enc
r
y
p
t
i
o
n an
d dec
r
y
p
t
i
on
pr
ocess c
o
nsi
s
t
s
of a n
u
m
ber of di
f
f
er
ent
t
r
ans
f
o
r
m
a
t
i
ons ap
pl
i
e
d
co
nsecu
tiv
ely
o
v
e
r
th
e
d
a
ta blo
c
k
b
its, in
a
f
i
x
e
d
nu
m
b
er
o
f
iter
a
tion
s
, called
r
oun
d
s
. Th
e nu
m
b
er
of
ro
unds
depe
n
d
s
on t
h
e
l
e
ngt
h o
f
t
h
e
key
use
d
fo
r t
h
e e
n
cry
p
t
i
o
n
pr
ocess
.
F
o
r
k
e
y
l
e
ngt
h
o
f
1
28
bi
t
s
, t
h
e
n
u
m
ber of
iteration re
qui
red a
r
e10.
(Nr = 10). As
s
h
own in Fi
gure
1, each
of the
first Nr-1
rounds consists
of 4
tr
an
sf
or
m
a
t
i
o
n
s:
Sub
B
ytes(
)
, Sh
if
tRow
s(
), Mix
C
o
l
u
m
n
s
(
)
& A
d
d
R
o
undK
ey(
)
.
Fi
gu
re
1.
AE
S
R
i
jn
dael
Des
c
r
i
be st
ep
There
are
f
o
u
r
di
ffe
re
nt
t
r
a
n
sf
orm
a
t
i
ons are
descri
bed
i
n
de
t
a
i
l
bel
o
w.
a)
S
u
b
Bytes
Transfo
rma
tion
:
It is a no
n-lin
ear substitu
tio
n
o
f
b
y
tes th
at op
erates in
d
e
p
e
n
d
e
n
t
l
y
o
n
each
b
y
te o
f
th
e State
usin
g
a
su
bstitu
tio
n tab
l
e (S
b
ox). Th
is S-box
wh
i
c
h
is i
n
v
e
rtib
l
e
is con
s
tru
c
ted
b
y
fi
rst tak
i
n
g
th
e m
u
ltip
l
i
cativ
e
in
v
e
rse in
th
e fin
ite field
GF (2
8
) wi
t
h
i
r
red
u
c
i
b
l
e
pol
y
n
o
m
i
al
m
(
x) = x8 +
x4+ x
3
+ x + 1. T
h
e el
em
ent
{00}
is m
a
p
p
e
d
to itself. Th
en
affine tran
sfo
r
m
a
tio
n
is app
lied
(ov
e
r GF (2
)).
b)
S
h
ift Ro
ws Tran
sfo
r
ma
tio
n:
Cyclically shifts the rows
o
f
t
h
e St
at
e over
di
ffe
re
nt
of
fset
s.
Th
e op
eration
is al
m
o
st th
e
sam
e
in
th
e
decry
p
tion process exce
pt
for
t
h
e
fact
t
h
at
t
h
e shi
f
t
i
n
g
o
ffse
t
s ha
ve
di
ffe
re
nt
val
u
es.
c)
Mix
Co
lumns Tran
sfo
r
ma
tion
:
T
h
is
trans
f
ormation
ope
rates on the State
colum
n
-by-c
o
l
u
m
n
,
treating each col
u
m
n
a
s
a four-te
r
m
polynom
i
al. The c
o
lum
n
s are
conside
r
ed as
polynom
i
als over GF (2
8
) and m
u
ltiplied by
m
odul
o
x4 +
1
with
a fi
xe
d
p
o
l
y
no
m
i
al
a(x) =
{0
3}
x3+
{0
1}
x
2
+ {
02}
x
.
d)
Ad
d R
o
u
n
d
K
e
y Tra
n
sf
orm
a
t
i
on
:
In
this
tra
n
s
f
orm
a
tion,
a Round Key is added to the State by
a sim
p
le bitwise XOR ope
r
ation. Each
R
o
u
n
d
Key
co
nsi
s
t
s
of
N
b
w
o
r
d
s f
r
om
t
h
e key
ex
pans
i
o
n. Those Nb words are eac
h ad
ded i
n
t
o
t
h
e c
o
l
u
m
n
s
o
f
th
e
State. Key Add
itio
n is
th
e sam
e
fo
r the d
e
cryp
tion
p
r
o
cess.
Key Expa
nsion:
Each r
o
u
n
d
ke
y
i
s
a 4-w
o
r
d
(1
2
8
-
b
i
t
)
array
gene
rat
e
d as a pro
d
u
ct
of t
h
e pr
evi
ous
ro
un
d key
,
a
constant that c
h
anges
each round, and a
se
ries of S-
Box l
o
okups
for eac
h 32-bit wo
rd of the
key. T
h
e
Key
sche
dul
e
E
x
pa
nsi
o
n ge
nerat
e
s
a
t
o
t
a
l
of N
b
(N
r
+ 1)
w
o
rds
.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
RES
I
S
SN
:
208
8-8
7
0
8
Desi
g
n
of
AE
S
Al
gori
t
h
m f
o
r
12
8/
1
9
2
/
2
56
K
ey Len
g
t
h
i
n
F
P
GA
(P
ra
v
i
n
V.
King
e
)
51
The
decry
p
tion process is
dire
ct i
nverse of the encry
p
tion process.
A
ll th
e t
r
an
sfo
r
m
a
tio
n
s
ap
p
lied
i
n
encry
p
t
i
o
n
p
r
o
cess are
i
n
vers
el
y
appl
i
e
d
t
o
t
h
i
s
pr
ocess.
He
nce t
h
e l
a
st
r
o
un
d
val
u
e
s
of
bot
h t
h
e
dat
a
a
n
d
key
are fi
rst rou
n
d
in
pu
ts for th
e decryp
tion
pr
oc
ess an
d
f
o
l
l
o
w
s
i
n
decrea
si
n
g
o
r
de
r.
2.
RELATED WORK
Th
e system
u
s
es AES
k
e
y ex
p
a
n
s
i
o
n
wh
ich
is u
s
ed
to
gen
e
rate m
u
ltip
le n
o
n
-
lin
ear
k
e
ys fo
r th
e
en
cry
p
tio
n process. Th
is
alg
o
rith
m
is
suitable for im
age en
cryp
tion
in
real ti
me ap
p
li
cations [1]. The
da
ta can
be enc
r
y
p
t
e
d by
1
28
bi
t
ci
pher
key
,
t
h
ro
u
gh t
h
e use
of
ci
pher
key
w
i
t
h
l
e
ngt
h
1
2
8
,
an ef
fi
ci
ent
FP
G
A
im
pl
em
ent
a
t
i
o
n o
f
12
8
bi
t
bl
ock a
n
d 1
2
8
bi
t
key
AES al
go
ri
t
h
m
has been
prese
n
t
e
d
[
2
]
.
They
p
r
ese
n
t
e
d
a l
o
w
cost e
ffective
area ciphe
r
for en
cryp
tion
/
d
ecryp
tion
u
s
ing 12
8
b
it ite
rative a
r
chitecture
,
af
ter foun
d th
at th
e
am
ount
o
f
ha
r
d
ware
res
o
u
r
ces
has
bee
n
opt
i
m
i
ze, One
of
t
h
e i
m
port
a
nt
I
m
pl
em
ent
a
t
i
on of
AE
S al
g
o
r
i
t
h
m
has
been
p
r
ese
n
t
e
d
by
R
a
nees
ha
K, R
e
m
a
Vel
l
ody
an
d R
na
n
d
a
Kum
a
r They
com
p
ared t
w
o
t
y
pe of al
go
ri
t
h
m
for
spee
d of
o
p
era
t
i
on an
d o
b
se
r
v
ed t
h
at
c
ont
r
o
l
l
e
r base ap
pr
o
ach [
4
]
.
M
g
S
u
res
h
,
Nat
a
ra
j.
K.R
,
co
ncl
u
de
d t
h
at
the conce
p
t of Pipeline
d
AE
S arc
h
itecture
can be
practi
cal
l
y
im
pl
em
ent
e
d. It
has
bee
n
o
b
se
rve
d
t
h
at
t
h
e
i
m
p
l
e
m
en
tatio
n
of
AES En
cryp
tio
n
o
n
th
e
FPGA is su
ccessfu
l
and
sev
e
ral d
a
ta in
pu
t.
Th
e
AES al
g
o
rith
m
is
an i
t
e
rat
i
v
e p
r
i
v
at
e key
sy
m
m
e
t
r
i
c
bl
ock c
i
phe
r t
h
at
can
pr
ocess
dat
a
bl
ock
of
1
2
8
-
bi
t
s
t
h
ro
u
gh t
h
e
use o
f
ci
phe
r key
s
wi
t
h
key
l
e
ngt
h
12
8,
1
92 a
nd 2
56
bi
t
s
. An ef
f
i
ci
ent
FPGA i
m
pl
em
ent
a
t
i
on of 1
28 bi
t
bl
o
c
k a
n
d
key
s
12
8,
1
9
2
and
2
5
6
bi
t
s
o
f
AES
–R
i
j
i
n
da
el
al
go
ri
t
h
m
has bee
n
pre
s
ent
e
d
[5]
.
3.
WORKI
N
G
The pr
o
pose
d
w
o
r
k
i
m
pl
em
ent
e
d wi
t
h
Fi
el
d
Pr
o
g
ram
m
a
bl
e
Gat
e
Ar
r
a
y
s
(FP
G
A
)
,
whi
c
h of
fers
qui
c
k
er
sol
u
t
i
o
n a
n
d
ca
n
be
easi
l
y
up
gra
d
e
d
t
o
i
n
c
o
r
p
ora
t
e any
pr
ot
oc
o
l
chan
ges
.
T
h
e
avai
l
a
bl
e
pi
pe
l
i
n
ed
AES algorit
h
m is used for image and suita
ble for im
ag
e encryption and decryption to
protect the confi
d
ential
im
age from
an
unaut
h
orized acces
s.
This
project proposes a
m
e
thod
in
whic
h the im
age is an input to
p
i
p
e
lin
ed
AES algo
rith
m
to
o
b
t
ain th
e en
cryp
ted im
ag
e,
an
d th
e en
crypted
im
ag
e is th
e i
n
pu
t to
p
i
p
e
lined
AES De
cry
p
t
i
on t
o
get
t
h
e ori
g
i
n
al
im
age, as Fi
gu
re 2.
In t
h
i
s
p
r
oject
,
im
pl
em
ent
t
h
e 12
8,
19
2 & 2
56
bi
t
pipeline
d
AES for im
age encryption
and
decryption and
com
p
are the s
p
eed
of ope
r
ation a
n
d efficiency
,
security &
fre
quency.
Fi
gu
re
2.
AE
S
encry
p
t
i
on/
De
cry
p
t
i
o
n m
odul
e i
n
VH
DL
4.
SIMULATION RESULTS
The
desi
g
n
ha
s bee
n
co
de
d
by
V
HDL
. Al
l
t
h
e res
u
l
t
s
are
sy
nt
hesi
zed a
nd si
m
u
l
a
t
e
d b
a
si
ng
o
n
t
h
e
Xilin
k
s
3
E
, the Mo
d
e
l Sim
.
Th
e resu
lts o
f
si
m
u
latin
g
th
e A
E
S
1
2
8
/
192
/2
56
en
cr
yp
tion/d
ecr
yp
tion
algo
r
ith
m
fr
om
t
h
e M
o
d
e
l
S
im
sim
u
l
a
t
o
r are
s
h
o
w
n i
n
Fi
g
u
re
3
,
Fi
g
u
re
4
an
d
Fi
g
u
r
e
5.
We
ha
ve
ge
nerat
e
d a
G
e
neri
c
code
which ca
n
be
use
for all
the three
AES
key.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
089
-48
64
IJR
E
S V
o
l
.
3, No
. 2,
J
u
l
y
20
1
4
:
4
9
– 53
52
Fi
gu
re
3.
Ti
m
i
ng
si
m
u
l
a
t
i
on of
AE
S1
2
8
e
n
c
r
y
p
t
i
o
n al
g
o
ri
t
h
m
Fi
gu
re
4.
Ti
m
i
ng
si
m
u
l
a
t
i
on of
AE
S1
9
2
e
n
c
r
y
p
t
i
o
n al
g
o
ri
t
h
m
Fi
gu
re
5.
Ti
m
i
ng
si
m
u
l
a
t
i
on of
AE
S2
5
6
e
n
c
r
y
p
t
i
o
n al
g
o
ri
t
h
m
They are s
h
owing a l
o
w l
a
tency. Hence
,
the
pr
actical res
u
lts are
in accorda
n
ce t
o
the
o
retical
pre
d
i
c
t
i
ons
an
d sat
i
s
fy
t
h
e e
n
cry
p
t
i
on a
n
d
decry
p
t
i
on m
e
t
h
o
d
o
l
o
gy
. T
o
t
e
st
t
h
e sy
st
em
, a t
e
st
benc
h i
s
use
d
.
The t
e
st
benc
h ap
pl
i
e
s encr
y
p
t
i
on/
dec
r
y
p
t
i
on i
n
p
u
t
pul
se
t
o
t
r
i
gger t
h
e
sy
st
em
. The
out
put
res
u
l
t
of t
h
e
encry
p
tion was
found acc
urat
el
y after 99 cl
ock cycles from the starting
of en
cryp
tion
p
r
o
cess. So
th
e laten
c
y
of enc
r
yption i
s
only 99 cl
ock cycles. Sim
i
la
rly,
th
e laten
c
y
of
d
ecryp
tio
n i
s
99 cl
ock cycles.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
RES
I
S
SN
:
208
8-8
7
0
8
Desi
g
n
of
AE
S
Al
gori
t
h
m f
o
r
12
8/
1
9
2
/
2
56
K
ey Len
g
t
h
i
n
F
P
GA
(Pr
a
vin V
.
Kinge)
53
5.
CO
NCL
USI
O
N
The A
d
vance
d
Encry
p
t
i
on St
anda
r
d
al
go
ri
t
h
m
i
s
a
symmetric block ci
pher that ca
n proces
s data
bl
oc
ks
of
1
2
8
bi
t
s
t
h
r
o
ug
h t
h
e use
of
ci
p
h
er
key
s
wi
t
h
l
e
n
g
t
h
s
o
f
1
2
8
,
1
9
2
,
a
nd
2
5
6
bi
t
s
. A
n
ef
fi
ci
ent
FPG
A
im
pl
em
ent
a
t
i
o
n
of
1
2
8
bi
t
bl
ock
an
d
1
2
8
bi
t
key
AES
al
g
o
ri
t
h
m
has
bee
n
prese
n
t
e
d i
n
t
h
i
s
pa
pe
r.
The
desi
g
n
i
s
im
pl
em
ent
e
d o
n
XIL
I
NKs
usi
n
g S
p
art
a
n
3E F
P
G
A
w
h
i
c
h i
s
base
d
on
hi
g
h
pe
rf
o
r
m
a
nce arc
h
i
t
ect
ur
e. O
u
r
arch
itecture is foun
d
t
o
b
e
b
e
t
t
er in
term
s o
f
laten
c
y,
throughput as
well as area. T
h
e
d
e
sig
n
is tested
wit
h
th
e
sam
p
le v
ecto
r
s pr
ov
id
ed
b
y
FI
PS
19
7.
REFERE
NC
ES
[1]
B. Subraman
y
a
n
,
Vivek
.
M. Chh
a
bria,
T.G. Sank
ar ba
bu
, “Image Encr
y
p
tion B
a
sed On AES
K
e
y
Exp
a
nsion”,
Second In
tern
ational Con
f
erence on
Emerging A
pplications of I
n
formation Technology, DO
I
10.1.109/EAIT.2
011.60,
IEEE, 2
011.
[2]
Hoang Trang,
Nguy
en Van
Loi,
“A
n efficient FPGA imple
m
entation of
th
e advan
ced
En
cr
y
p
tion standar
d
algorithm”,
978-
1-4673-0309-5/1
2
, IEEE
, 2012
.
[3]
A. Amaar, I.
Ashour and M Shiple, “Design and im
plementation
a compact AES Architectur
e for FPGA
Techno
log
y
”,
W
o
rld Acad
emy o
f
scien
c
e,
engineering and technology
, 59
, 2011
.
[4]
Ranees
ha
K, R
e
m
a
Vellod
y
an
d R nanda Ku
m
a
r, “
H
ardware
effi
cien
c
y
com
p
arion of AES
im
plem
entat
i
on”
,
internationa
l co
nference on communication system
and network t
echnolog
y. DOI
10.1109/CSNT.2
012.187, IEEE
,
2012.
[5]
M
g
S
u
res
h
, Dr.
Nataraj
.
K.R,
“
A
rea Optim
ized and P
i
pelined
F
P
GA Im
plementa
tion of AES
Encr
y
p
t
i
on a
n
d
Decr
yption
”
,
International Journ
a
l of Com
putatio
nal Eng
i
neering
Research
, Vol. 2
Issue 7, Nov 20
12.
[6]
Nationa
l Institut
e
of Standards a
nd Techno
log
y
(
U
.S.), "Data
Enc
r
y
p
t
i
on Standard
(DES)",
FIPS Publication 46-3
,
NIST, 1999. Ava
ilable at
http:
/
/
c
src.nist.
gov/publ
ications/
fips/f
i
ps46-3/fips46-3.pd
f
[7]
J.
Yang,
J.
Ding, N.
Li
and Y.
X.
Guo, “FPGA-based desi
gn and
implementation o
f
reduced AES algorithm”
IEEE
Inter. Con
f
. Cha
l
En
vir S
c
i Com
Engin (
C
ESCE)
.
Vol. 02, Issue. 5
-
6, pp
. 67-70
, Ju
n 2010.
[8]
National institu
t
e
of standard an
d technolog
y
,
“Fed
eral inform
ati
on Procesing standaed publi
c
atio
n 197,
the A
E
S”
,
Nov 2001.
Evaluation Warning : The document was created with Spire.PDF for Python.