Intern
ati
o
n
a
l
Journ
a
l of
Re
con
f
igur
able
and Embe
dded
Sys
t
ems
(I
JRES)
V
o
l.
2, N
o
. 3
,
N
o
v
e
m
b
er
2
013
, pp
. 11
6
~
12
1
I
S
SN
: 208
9-4
8
6
4
1
16
Jo
urn
a
l
h
o
me
pa
ge
: h
ttp
://iaesjo
u
r
na
l.com/
o
n
lin
e/ind
e
x.ph
p
/
IJRES
An Effi
cient Imp
l
ement
a
t
i
on of
th
e Entire Transforms in the
H.264/AVC En
coder usi
n
g VHDL
Fa
rha
d
Ra
d*
, A
li Broumandnia*
*
* Departement o
f
Computer
E
ngineering
,
College
of Graduate Stu
d
ies, Scie
n
ce
an
d Resear
ch Br
an
ch of Kohgilu
y
e
h and
Bo
y
e
r-
ahm
a
d,
Is
lam
i
c Az
ad Uni
v
ers
i
t
y
,
Yas
ouj,
Iran
** Depart
em
ent
of Com
puter
En
gineer
ing,
S
c
ien
ce
and R
e
s
ear
ch
Branch of
T
e
hra
n
, Is
lam
i
c
Az
ad
Univers
i
t
y
,
T
e
hr
an,
Iran
Article Info
A
B
STRAC
T
Article histo
r
y:
Received Aug 2, 2013
Rev
i
sed
O
c
t 14
, 20
13
Accepted Oct 28, 2013
The H.264/AVC standard achiev
e
s
remarkable high
er compression
performance
than the pr
evious
MPEG and H.26X standards.
One of th
e
com
putation
a
ll
y intensive uni
ts in
the MPEG and H.26X video coding
fam
ilies
is the Discrete
Cosin
e
Transf
orm
(DCT). In
this pap
e
r
,
we propose
an effi
ci
ent im
p
l
em
enta
tion of
t
h
e DCT, inv
e
rs
e DCTs
and th
e
Hadam
a
rd
transforms in th
e H.264/AVC encode
r using
VHDL. The s
y
n
t
hesis results
indic
a
te
tha
t
ou
r im
plem
enta
tio
n of the
ent
i
re
transform
s
ach
ieves lowe
r
power, d
e
lay
an
d area
consumption compar
ed
to
the
exist
i
ng a
r
c
h
ite
ctures
in
the H.264
/AVC
encoder
.
Keyword:
Discrete C
o
sine Tra
n
sform
H.
26
4 Enc
o
der
Hadam
a
rd T
r
a
n
sf
orm
Inte
ger DCT
VH
DL
Copyright ©
201
3 Institut
e
o
f
Ad
vanced
Engin
eer
ing and S
c
i
e
nce.
All rights re
se
rve
d
.
Co
rresp
ond
i
ng
Autho
r
:
Farhad Rad,
Depa
rt
em
ent
of C
o
m
put
er
En
gi
nee
r
i
n
g,C
o
l
l
ege
of
G
r
ad
uat
e
St
u
d
i
e
s,
Science a
n
d R
e
search Bra
n
ch of Kohgil
u
yeh and B
o
yer-a
hmad,
Islamic
Azad Uni
v
ersity, Ya
souj,
Ira
n
.
Em
a
il: F_
rad
l
@ho
t
m
a
i
l
.co
m
1.
INTRODUCTION
C
o
m
p
ressi
on
i
s
t
h
e
pr
ocess
of
re
duci
ng t
h
e si
ze of
t
h
e
d
a
t
a
sent
, t
h
e
r
e
b
y
,
re
d
u
ci
n
g
t
h
e
ban
d
w
i
d
t
h
req
u
i
r
e
d
f
o
r t
h
e di
gi
t
a
l
rep
r
es
ent
a
t
i
on
of a si
gnal
.
M
a
ny
i
n
expe
nsi
v
e vi
de
o an
d au
di
o ap
pl
i
cat
i
ons are
m
a
de
pos
si
bl
e by
t
h
e
com
p
ressi
on
o
f
si
gnal
s
. C
o
m
p
ressi
o
n
t
echn
o
l
o
gy
can res
u
l
t
i
n
reduce
d
t
r
ansm
i
ssi
on t
i
m
e
due
to less
data bei
n
g tra
n
sm
itted. It also dec
r
eas
es the
st
ora
g
e
requi
rem
e
nts because t
h
ere is
less data. Howe
ver,
sig
n
a
l
q
u
a
lity, i
m
p
l
e
m
en
tati
o
n
co
m
p
lex
ity, and
th
e in
t
r
o
d
u
c
tion
of co
mm
u
n
i
catio
n
d
e
lay are poten
tial
negat
i
v
e
fact
o
r
s t
h
at
sho
u
l
d
be consi
d
ere
d
w
h
en c
h
o
o
s
i
ng com
p
ressi
on t
ech
n
o
l
o
gy
[3]
.
The H
.
2
64/
A
V
C
st
anda
rd
[1]
a
c
hi
eves
rem
a
rkabl
e
hi
g
h
er c
o
m
p
ressi
o
n
pe
rf
orm
a
nce t
h
a
n
t
h
e p
r
e
v
i
o
us
M
P
EG an
d
H.
26
X
st
anda
rd
s. The
hi
ghe
r pe
rf
or
m
a
nce i
n
H.2
6
4
/
A
VC
i
s
due
t
o
vari
ous m
o
d
i
fi
cat
i
ons i
n
di
ffe
rent
co
di
n
g
st
ages
and m
o
st
of t
h
ese m
odi
fi
cat
ions i
m
pose
hi
g
h
com
put
at
i
o
n
a
l
l
o
ad t
o
t
h
e
H.
26
4/
A
V
C
co
dec [
5
]
-
[
7
]
.
O
n
e of t
h
e
co
m
p
u
t
atio
n
a
lly in
ten
s
iv
e
u
n
its in
th
e MPEG and
H.
2
6
X v
i
d
e
o
cod
i
ng
fam
ilies
is t
h
e Discrete Co
si
ne
Transform
(DCT). Hence
,
the architect
ure
ex
p
l
o
r
ation
o
f
th
is un
it is ev
en
attractiv
e fo
r th
e pre-H.2
64/AVC
standa
rds and t
h
ere are
proposals for
ha
rdware architectures to realize th
is u
n
it fro
m
a
l
o
ng
ti
m
e
ag
o
[8
] an
d
it is st
ill co
n
t
i
n
u
i
n
g
[
9
]-[1
0
]
. Th
e in
itial v
e
r
s
ion
of
H
.
264
/AV
C
stand
a
rd
supp
or
ted
o
n
ly 4
×
4
in
teg
e
r
D
C
T.
The
num
ber
of
o
p
erat
i
o
ns
fo
r
com
put
at
i
on
o
f
an
8×
8
or
4×
4 I
n
t
e
g
e
r
DC
T
i
s
n
o
t
ve
ry
hi
gh
b
u
t
si
nce
i
n
hi
g
h
profiles theses
trans
f
orm
s
should be a
pplie
d to the entire 8×
8 or
4×
4 bloc
ks
in a fram
e
, it
will result in a huge
co
m
p
u
t
atio
n
a
l lo
ad
an
d
m
a
k
e
s th
e in
teg
e
r
discrete co
si
ne t
r
ans
f
orm
am
o
ng m
a
i
n
com
p
ut
at
i
onal
l
y
i
n
t
e
nsi
v
e
st
ages i
n
t
h
e
H.
26
4 e
n
co
de
r
.
C
o
nseq
ue
nt
l
y
, t
h
e ha
rd
wa
re i
m
pl
em
ent
a
t
i
on o
f
t
h
e i
n
t
e
ger
DC
T t
r
a
n
sf
orm
at
t
r
act
ed m
o
re at
t
e
nt
i
on an
d
a num
ber of
sol
u
t
i
o
ns
ha
ve
been
pu
bl
i
s
he
d f
o
r
har
d
wa
r
e
im
pl
em
ent
a
ti
on o
f
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
RES
I
S
SN
:
208
9-4
8
6
4
An
Efficien
t
Imp
l
emen
ta
tion
of th
e En
tire Tra
n
s
f
o
rms
in the H.26
4
/
AVC
En
co
d
e
r using
VHDL (Farhad
ra
d
)
11
7
Int
e
ger
DC
T i
n
t
h
e H.
26
4/
A
V
C
st
andar
d
[
1
1
]
-[1
2]
. I
n
t
h
i
s
pape
r,
we p
r
o
p
o
se
d an ef
fi
ci
ent
im
pl
em
ent
a
ti
on o
f
th
e en
tire tran
sform
s
in
th
e
H.
26
4/
A
V
C
E
n
c
ode
r usi
n
g V
H
D
L.
Si
nce t
h
e enc
odi
ng l
o
o
p
o
f
t
h
e H.
26
4/
A
V
C
st
anda
r
d
r
e
qui
res car
ry
i
ng
out
al
l
t
h
e for
w
a
r
d a
n
d
inve
rse tra
n
sform
s
, the proposed im
ple
m
entation is a
very
powe
rful accelerator fo
r t
h
e
H.264/AVC e
n
code
r.
The sy
nt
he
si
s resul
t
s
i
ndi
ca
t
e
t
h
at
our i
m
pl
em
ent
a
t
i
on of t
h
e DC
T
,
i
nverse
DC
T
s
and t
h
e H
a
dam
a
rd
tr
an
sf
or
m
s
in
t
h
e H.264
/AVC
encoder a
c
hieves lower
power, delay
and area cons
um
ption com
p
are
d
to the
existing arc
h
itectures i
n
th
e H.2
6
4
/
AV
C en
cod
e
r.
The re
st
o
f
t
h
e pape
r i
s
or
g
a
ni
zed as
f
o
l
l
o
ws
. I
n
sect
i
o
n 2
we
pr
o
v
i
d
e a bri
e
f o
v
er
vi
ew
of t
h
e
tran
sform
s
in
th
e H.26
4
/
AVC stan
d
a
rd
and
d
i
scu
ss th
e
in
itial h
a
rdware i
m
p
l
e
m
en
tat
i
o
n
.
Th
e
p
r
o
p
o
s
ed
im
pl
em
ent
a
t
i
o
n o
f
t
h
e e
n
t
i
r
e
t
r
ans
f
o
r
m
s
i
n
t
h
e H.
2
64/
A
V
C
st
an
dar
d
i
s
expl
ai
ned i
n
sect
i
on
3.
V
HDL
an
d
sy
nt
hesi
s res
u
l
t
s for t
h
e
gi
ve
n arc
h
i
t
ect
ure
and c
o
m
p
ar
ison with the
pri
m
al arch
itecture are prese
n
ted in
sect
i
on
4.
Fi
nal
l
y
,
Sect
i
on
5
c
oncl
ude
s t
h
e
p
a
per
.
2.
THE H.2
6
4
/
AV
C STAND
AR
D
In t
h
e H.
2
64/
A
V
C
st
an
dar
d
t
h
e fo
rwa
r
d a
n
d
t
h
e i
nve
rse i
n
t
e
ger
DC
T are
defi
ned
res
p
ect
i
v
el
y
i
n
(1
)
an
d (2
) as:
(2)
i
)C
i
E
(Y
T
i
C
X
YA
T
A
X
(1)
f
E
T
f
XC
f
C
Y
T
AXA
Y
Whe
r
e
T
f
XC
f
C
and
i
)C
i
E
(Y
T
i
C
are called ‘’c
ore
‟
t
r
ans
f
orm
s
[2]. The C
f
and C
i
m
a
t
r
i
ces
gi
ven i
n
(3
)
indicate the ‘’core
‟
tr
an
sf
orm
m
a
tr
ix
o
f
t
h
e fo
rw
ar
d
and
inv
e
r
s
e
4
×
4 in
teg
e
r
D
C
T in
th
e H.264/A
V
C
standa
rd,
respe
c
tively [zargari
, m
a
lvar].
(3)
1/2
-
1
1
-
1
1
1
-
1/2
-
1
1
-
1
-
1/2
1
1/2
1
1
1
C
1
-
2
2
-
1
1
1
-
1
-
1
2
-
1
-
1
2
1
1
1
1
i
f
C
H.2
6
4
is un
iqu
e
th
at it e
m
p
l
o
y
ees th
is p
u
rely in
teg
e
r spatial tran
sform as o
p
p
o
s
ed
to
th
e u
s
u
a
l
fl
oat
i
n
g p
o
i
n
t
8x
8
DC
T s
p
ec
i
f
i
e
d wi
t
h
r
o
u
ndi
ng e
r
r
o
r t
o
l
e
rance as
use
d
in earlier standards
[2]. T
h
e
sm
a
l
l
sha
p
e hel
p
s t
o
red
u
ce t
h
e bl
ocki
ng a
nd
ri
n
g
i
n
g art
e
fact
s, wh
ile th
e p
r
ecise in
teg
e
r specificatio
n
elimin
ates
an
y m
i
s
m
atch
b
e
tween
t
h
e en
cod
e
r an
d
d
e
co
d
e
r i
n
t
h
e inv
e
rse tran
sform
.
Th
e m
u
ltip
licatio
n
s
b
y
1
/
2
i
n
the
i
nve
rse t
r
a
n
s
f
o
r
m
can be i
m
pl
em
ent
e
d by
t
h
e si
g
n
prese
r
vi
ng
1
-
bi
t
ri
ght
s
h
i
f
t
s
t
h
us
re
du
ci
ng t
h
e c
o
m
p
l
e
xi
t
y
.
Hadam
a
rd t
r
a
n
sf
orm
i
s
anot
her 2
D
t
r
a
n
sf
orm
whi
c
h i
s
use
d
i
n
t
h
e H
.
2
64/
AVC
st
a
nda
r
d
and i
t
s
‘’c
ore
‟
tran
sform
m
a
tr
ix
is:
(4)
1
-
1
1
-
1
1
1
-
1
-
1
1
-
1
-
1
1
1
1
1
1
4
4
H
Fi
gu
re 1.
Q
u
i
c
k har
d
ware f
o
r 4×4
Ha
dam
a
rd
Transfo
r
m
co
nd
itio
n
Fi
gu
re 2.
Q
u
i
c
k har
d
ware f
o
r fo
rwa
r
d 4×4
I
n
t
e
ger
DCT
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
089
-48
64
I
J
RES
Vo
l. 2
,
N
o
. 3
,
Nov
e
mb
er
201
3
:
1
16
–
12
1
11
8
Since H
T
4×4
= H
4×4
, t
h
e
ha
rd
ware
i
m
pl
em
ent
a
t
i
on
gi
v
e
n
i
n
Fi
gu
re
1 ca
n
be
use
d
f
o
r
bot
h
fo
rwa
r
d
a
n
d
i
nve
rse Ha
da
m
a
rd t
r
ans
f
o
r
m
s
. Fi
gure
2 sho
w
s a
n
q
u
i
c
k ha
rd
ware r
eal
i
zat
i
on fo
r 4×4 f
o
rwa
r
d i
n
t
e
ge
r
t
r
ans
f
o
r
m
usi
ng a
dde
rs a
n
d
shi
f
t
e
rs
an
d Fi
gu
re
3 i
n
di
cat
es a q
u
i
c
k
ha
r
d
wa
re
real
i
zat
ion
f
o
r
4×
4 i
n
vers
e
in
teg
e
r tran
sfo
r
m
[2
].
Fi
gu
re 3.
Q
u
i
c
k har
d
ware f
o
r
i
nver
s
e 4×4 I
n
teger DCT
3.
THE PROPOSED IMPLE
M
ENT
A
TION
Thi
s
sect
i
on i
n
t
r
o
duces t
h
e p
r
op
ose
d
i
m
pl
em
ent
a
t
i
on o
f
t
h
e 4×
4 f
o
r
w
a
r
d t
r
an
sf
orm
and 4×
4 i
n
verse
t
r
ans
f
o
r
m
ado
p
t
e
d
by
t
h
e
H
.
26
4 st
a
n
d
a
r
d
.
‘C
o
r
e’ t
r
ans
f
or
m
i
s
a t
w
o
di
m
e
nsi
onal
t
r
a
n
sfo
r
m
,
whi
c
h
can
be
decom
pose
d
i
n
t
o
t
w
o o
n
e di
m
e
nsi
o
nal
t
r
ans
f
orm
s
. The fi
rst
one di
m
e
nsi
onal
t
r
ans
f
o
r
m
is appl
i
e
d t
o
t
h
e row
s
of t
h
e i
n
put
pi
xel
s
a
nd t
h
e seco
nd
o
n
e
di
m
e
nsi
onal
t
r
ans
f
o
r
m
i
s
appl
i
e
d t
o
t
h
e
col
u
m
n
s of t
h
e one
dim
e
nsional transform
coefficients of t
h
e first stag
e. T
h
e pr
op
ose
d
ar
chi
t
ect
ure
use
s
4×4
paral
l
e
l
i
n
p
u
t
bl
oc
ks;
a
bl
oc
k di
a
g
ram
of t
h
e arc
h
i
t
ect
ure
i
s
sh
ow
n i
n
F
i
gu
re 4
.
T
h
i
s
b
l
ock c
o
nsi
s
t
s
o
f
f
o
ur casca
de
d s
u
b
-
bl
oc
ks.
The c
o
nt
r
o
l
u
n
i
t
i
s
us
ed t
o
c
o
nt
r
o
l
a
d
d
an
d s
h
i
f
t
op
erat
i
ons
. T
h
e
r
e
gi
st
er
ban
k
st
ores
t
h
ese
o
u
t
p
ut
s f
o
r
the ne
xt
four cl
ock cycles.
Fi
gu
re
4.
A
r
chi
t
ect
ure
of
co
re
fo
rwa
r
d a
n
d
i
n
verse
i
n
t
e
ge
r t
r
ansf
o
r
m
s
.
4.
VH
DL A
N
D
S
YNTHE
SIS
R
E
SULT
VHDL
sim
u
la
tio
n
resu
lts
for fo
rward
/inv
e
rse
4
×
4 In
teger DCT and
Had
a
m
a
rd
tran
sfo
r
m
are
depi
ct
ed i
n
fi
g
u
re 5
-
10
. Aft
e
r
successf
ul
sim
u
l
a
t
i
on o
f
w
o
r
k
i
n
g of
di
ffe
re
nt
bl
oc
ks o
f
H.
26
4 enc
o
der (
I
n
t
e
ge
r
DC
T,
In
ver
s
e DC
T,
Ha
dam
a
rd t
r
ans
f
o
r
m
)
, we t
h
en
p
r
ocee
de
d f
o
r sy
nt
h
e
si
s of c
o
d
e
on
Xi
l
i
nx.
ISE
.
D
E
SIG
N
.
S
U
I
TE
.
v
1
2
.
3
a
n
d
Sy
n
opsi
s
.A
n
d
al
so
we h
a
ve c
o
m
p
are
d
ou
r sy
nt
hesi
s res
u
l
t
s
w
i
t
h
t
h
e
per
f
o
r
m
a
nce of exi
s
t
i
ng i
m
pl
em
ent
a
t
i
ons [
4
]
.
C
o
m
p
ari
s
o
n
sh
ow
s t
h
at
po
we
r co
nsum
pt
i
on a
nd
del
a
y
are
lo
wer th
an o
t
her im
p
l
e
m
en
tat
i
o
n
s
.
Also
, th
e area of
ou
r ch
ip is m
u
ch
smaller th
an
o
t
h
e
rs. Su
mm
ar
y o
f
th
e
sy
nt
hesi
s res
u
l
t
s
are sh
ow
n
i
n
Tabl
es 1, 2
a
n
d
3.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
RES
I
S
SN
:
208
9-4
8
6
4
An
Efficien
t
Imp
l
emen
ta
tion
of th
e En
tire Tra
n
s
f
o
rms
in the H.26
4
/
AVC
En
co
d
e
r using
VHDL (Farhad
ra
d
)
11
9
Fi
gu
re
5.
Si
m
u
l
a
t
i
on R
e
sul
t
o
f
Q
u
i
c
k
DC
T4
*4
i
n
VH
DL
Fig
u
re
6
.
Sim
u
latio
n
Resu
lt
of Qu
ick
IDCT4*
4 in
VH
DL
Fi
gu
re
7.
Si
m
u
l
a
t
i
on R
e
sul
t
o
f
H
a
dam
a
rd
4*
4 i
n
V
H
D
L
Fi
gu
re 8.
DC
T
4*
4 Test
i
n
V
HDL
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
089
-48
64
I
J
RES
Vo
l. 2
,
N
o
. 3
,
Nov
e
mb
er
201
3
:
1
16
–
12
1
12
0
Fi
gu
re
9.
I
D
C
T
4
*
4
Test
i
n
VH
DL
Fi
gu
re 1
0
. Ha
d
a
m
a
rd 4*
4
t
e
st
i
n
V
H
D
L
Tabl
e 1. Sy
nt
h
e
si
s
R
e
sul
t
s
of DC
T 4*
4
I
m
ple
m
e
n
tation
Pow
er(
m
W
)
Delay(ns)
Area(MicroM2)
E
x
isting DCT
4.
1494
2.
36
1081
2.
413
114
Pr
oposed DCT
3.
2174
2.
06
7269.
4
197
28
Tab
l
e 2
.
Syn
t
hesis
Resu
lts o
f
I
D
CT
4*4
I
m
ple
m
e
n
tation
Pow
er(
m
W
)
Delay(ns)
Area(MicroM2)
E
x
isting I
D
CT
7.
0668
2.
76
1727
8.
790
363
Pr
oposed I
D
CT
5.
7302
2.
76
1294
3.
068
996
Tabl
e 3. Sy
nt
h
e
si
s
R
e
sul
t
s
of Hadam
a
rd 4
*
4
I
m
ple
m
e
n
tation
Pow
er(
m
W
)
Delay(ns)
Area(
MicroM2)
E
x
isting Hadam
a
rd
3.
1193
2.
55
7223.
2
829
46
Pr
oposed Hadam
a
r
d
3.
0934
2.
44
7223.
1
610
31
Tabl
e 4. Sy
nt
h
e
si
s
R
e
sul
t
C
o
m
p
ari
s
on of
C
o
re Tran
sform
with
Ex
istin
g Im
p
l
e
m
en
tatio
n
This w
o
rk
Ex
isting
i
m
pl
e
m
e
n
ta
tio
n
[4
]
No.
of flip flo
p
s
58
65
No.
of Slices
159
167
M
a
x.
fr
eq
193M
Hz
185M
Hz
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
RES
I
S
SN
:
208
9-4
8
6
4
An
Efficien
t
Imp
l
emen
ta
tion
of th
e En
tire Tra
n
s
f
o
rms
in the H.26
4
/
AVC
En
co
d
e
r using
VHDL (Farhad
ra
d
)
12
1
5
.
CONC
LU
SION
In t
h
i
s
pa
pe
r, a
n
ef
fi
ci
ent
i
m
p
l
em
ent
a
t
i
on o
f
t
h
e co
re
pr
oces
sors
o
f
H.
26
4
vi
de
o e
n
co
der
i
s
pr
op
ose
d
.
Th
e 4x4
in
teg
e
r tran
sfo
r
m
u
s
ed
is sig
n
i
fican
tly si
m
p
ler
and faster t
h
an t
h
e 8×
8 DCT
used in MPE
G
2. T
h
is
tran
sform
is a
scaled
in
teg
e
r
ap
pro
x
i
m
a
tio
n
to
th
e DCT,
whi
c
h al
l
o
w
s
com
put
at
i
on o
f
t
h
e di
rect
or
i
nve
rs
e
t
r
ans
f
o
r
m
wi
th j
u
st
ad
di
t
i
ons an
d a m
i
ni
m
a
l
nu
m
b
er
of sh
ifts,
b
u
t
no
m
u
lt
ip
licatio
n
s
. Syn
t
h
e
sis resu
lts
in
d
i
cate th
at ou
r im
p
l
e
m
en
ta
tio
n
,
wh
ich
realizes th
e en
tire tran
sfo
r
m
s
in
th
e H.
2
64/
AVC st
anda
rd, can
pr
ocess l
o
we
r
po
we
r,
del
a
y
an
d area c
o
nsum
pt
i
on c
o
m
p
ared
to
th
e ex
istin
g ar
c
h
itectures [4],
whic
h
im
pl
em
ent
a n
u
m
b
er of t
h
e
t
r
ans
f
o
r
m
s
i
n
H.
26
4/
A
V
C
.
Al
so, c
o
m
p
ari
s
o
n
sh
ow
s t
h
at
ou
r desi
gn ac
hi
eve
d
h
i
gh
er fr
equ
e
ncy.
REFERE
NC
ES
[1]
ITU-T Rec. H.2
64 / ISO/IEC
11
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Advan
c
ed
vid
e
o coding for
ge
neric audio
v
isual services
.
2005.
[2]
H Malvar, A Hallapuro
,
M Karczewic
z, L Kerof
s
k
y
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com
p
l
e
xit
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tr
ansform
and quanti
zat
ion
in H.264/AVC.
IEEE Trans. Circuit
syst. Vid
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o
Techno,.
2003; 3
(
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[3]
F Zargari, S Ghorbani.
A Hardware Sharing A
r
chitecture for Implem
enting th
e entire Transforms in
H.264/AVC
Video
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15th
IEEE In
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l S
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mposium on
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onics (IS
CE201
1). 2011: 14-17.
[4]
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Pankaj
.
Design and
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Tr
ansform
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antization Blo
c
k
s
of H.264 Vid
e
o
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Inter
nat
io
nal Jour
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m
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r
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nd Developm
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[5]
L Li, Y Song,
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enag
a, S Goto. A H
a
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2008; 5
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[6]
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A Atitallah,
P
Kadionik,
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F
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G
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ati
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Video Coding
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i
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Processi
ng Systems, Online First™.
2011
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[7]
GA Ruiz, JA Michell. An
Eff
i
cient VLSI Ar
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e of
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Journal of Signa
l Processing Sys
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ems
. 2011; 62(3
)
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[8]
W Liebsch.
Par
a
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f
a
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rete co
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n
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e
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its Applications.
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[9]
J Park, K Roy
.
A Low Compl
e
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igu
r
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a
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e off Im
age Qualit
y for P
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u
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h
a,
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W
a
ng, L
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at
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l Conf
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BIOGRAP
HI
ES OF
AUTH
ORS
F
a
rhad Rad
re
c
e
ived
B.S
c
. in
Com
puter Hard
ware Eng
i
ne
erin
g from
S
h
iraz
Univers
i
t
y
in
S
h
iraz
,
Iran in 2005, M.Sc. in Computer Hardware
Engi
neering fro
mIran University
of Scien
ce and
techno
log
y
in Tehran, Ir
an in 2
008, andPh.D.
St
udent in Hard
ware Engin
eerin
g in Islamic Azad
Univers
i
t
y
, S
c
i
e
nce and Res
ear
c
h
Branch in Teh
r
an, Iran
.
His
res
earch int
e
res
t
s
i
n
clude S
y
s
t
em
-on-
Chip design an
d verific
a
t
i
on,
em
bedded s
y
ste
m
s,
VLSI
sy
st
e
m
s/circuits desi
gn for m
u
ltim
edia
application.
Ali Broum
andnia was born in
Esfahan, Ir
an in
1967. He recei
ved B.Sc. inCo
m
puter Hardware
Engineering f
r
o
m
Esfahan Univ
ersity
of
Techno
lo
g
y
in
Esfahan
,
Iran in
1992, M.Sc.
in Computer
Hardware Eng
i
n
eering fromIran
University
of
Sc
ience and
Technolog
y
in
Tehran, Ir
an in 19
95,
andPh.D. degr
ee in Computer
Engine
ering fro
m
Is
lam
i
c Azad Univers
i
t
y
,S
c
i
e
n
ce and R
e
s
ear
ch
Branch in
Teh
r
an, Iran
,
in
2006.
He is interested
in pattern r
ecognition, do
cumentimage analy
s
is, and
wavele
t anal
ysis
.
Evaluation Warning : The document was created with Spire.PDF for Python.