Intern
ati
o
n
a
l
Journ
a
l of
Re
con
f
igur
able
and Embe
dded
Sys
t
ems
(I
JRES)
V
o
l.
4, N
o
. 1
,
Mar
c
h
20
15
,
pp
. 42
~54
I
S
SN
: 208
9-4
8
6
4
42
Jo
urn
a
l
h
o
me
pa
ge
: h
ttp
://iaesjo
u
r
na
l.com/
o
n
lin
e/ind
e
x.ph
p
/
IJRES
Implementation of PI Controller for 3
ф
BLDCM Drive Usin
g
FPGA
S.M. Ram
e
sh Balaji
*, C.
Muniraj*
*Ele
ctri
cal
Driv
es
and Con
t
rol
L
a
borat
ar
y
,
Depar
t
ment
of Electr
i
cal and Elec
tronics Engineering
,
K
.
S. Rang
asam
y
College of
Tech
nolog
y
,
Ind
i
a
Article Info
A
B
STRAC
T
Article histo
r
y:
Received Sep 2, 2014
Rev
i
sed
Jan 27, 201
5
Accepted
Feb 10, 2015
Despite th
e n
e
e
d
of a
com
p
lex
m
o
tor controll
er
, th
e sim
p
le
con
s
truction of
BLDC motors offers several inh
e
rent
advan
t
ag
es not provid
e
d w
ith brushed
DC m
o
tors in term
s of low inerti
a, hi
gh
torque
and a ver
y
wid
e
speed rang
e.
The BLDC m
o
tors
include,
Lon
g
er s
e
rvic
e life d
u
e to a la
ck of el
ectr
i
ca
l and
frict
ion los
s
e
s
and als
o
free
m
a
intenan
ce du
e to a lack of
brus
hes
and
m
echanic
al
com
m
u
tators
. Th
e E
M
I and nois
e
a
r
e redu
ced b
e
c
a
u
s
e
of the
elimination of
io
nizing spik
es fro
m br
ushes. The
control s
y
stem o
f
BLDCM
is highly
complex drive due
to nonlinear n
a
ture. In such a s
y
stem for
implementing
co
ntrol algorithm
needs high sp
eed processor. In
this work the
controller Xilin
x Spartan-6 FP
GA is a
demonstration p
l
atfo
r
m
intended
to
becom
e
fam
iliar
with the new
featur
es and avail
a
bili
t
y
of th
e
Spartan-6
FPGA. The various experimental
tes
t
s
are
carr
i
e
d
out in
3
Ф
B
L
DCM .The
experim
e
nt
al r
e
s
u
lts
are
repor
ted
in order
to v
e
rif
y
the s
t
ead
y s
t
at
e,
trans
i
e
n
t
and robustness p
e
rformance of
th
e con
t
roller.
Keyword:
B
r
us
hl
ess DC
(
B
LDC
)
Mo
to
r driv
e
Co
nv
erters
Fi
el
d-
pr
og
ram
m
a
bl
e gat
e
ar
r
a
y
s
Pu
lse wid
t
h
mo
du
latio
n
Copyright ©
201
5 Institut
e
o
f
Ad
vanced
Engin
eer
ing and S
c
i
e
nce.
All rights re
se
rve
d
.
Co
rresp
ond
i
ng
Autho
r
:
S.M.
Ram
e
sh
Balaj
i
,
Depa
rtm
e
nt of
Electrical and
Electronics
E
n
gineering,
K.S
.
Rang
as
am
y Coll
ege o
f
T
ech
nolog
y, K
.
S
.
R.
Kalvi Nag
a
r,
Tiru
ch
eng
o
d
e
, N
a
mak
k
a
l – 637
21
5
Em
a
il: ra
m
e
sh
b
a
laj
i
13@g
m
ail.co
m
1.
INTRODUCTION
Env
i
ron
m
en
ts an
d requ
irem
e
n
ts in wh
ich man
u
fact
urers
us
e brus
hless
-
type DC m
o
tors
i
n
clude l
o
w
m
a
i
n
t
e
nance
o
p
erat
i
o
n,
hi
g
h
e
r
spee
d, a
n
d n
o
spar
ki
n
g
ope
r
a
t
i
on.
Wh
en c
o
nve
rt
i
n
g el
ectricity into
m
echanical
po
we
r,
br
ushl
ess m
o
t
o
rs ar
e
m
o
re ef
fi
ci
ency
t
h
an
b
r
us
hed m
o
t
o
rs
.
B
r
us
hl
ess DC
m
o
t
o
r (B
L
D
C
)
i
s
a
brus
hless m
o
tor
because the
r
e
are
no
brus
he
s and c
o
mm
utator. In BL
DC
Motor t
h
e c
o
mmutation is a
c
t with
th
e h
e
lp
o
f
electron
ic circu
its, wh
ich
d
e
creases th
e
m
echanic losses and im
proves
the e
f
ficiency. A Brushless
DC
m
o
t
o
r ha
s
a r
o
t
o
r
wi
t
h
perm
anent
m
a
gnet
s
a
n
d a st
at
or
wi
t
h
wi
n
d
i
ngs
. B
L
DC
m
o
t
o
rs
have l
o
n
g
b
een
u
s
ed
in
indu
strial ap
p
licatio
ns su
c
h
as actuators, C
N
C machines
, indust
r
ial rob
o
t
s, ex
t
r
ud
er
driv
es, am
o
n
g
ot
he
rs. Sm
al
l cool
i
n
g fa
ns i
n
el
ect
roni
c eq
ui
pm
ent
are pow
ered e
x
cl
usi
v
el
y
by
brus
hl
ess
m
o
t
o
rs. Lo
w speed
,
low power brushless m
o
tors are use
d
in direct-dri
ve
t
u
r
n
t
a
bl
es fo
r g
r
am
op
h
one
records. The
r
efore
,
BLDC
m
o
t
o
rs m
a
y
be use
d
i
n
fa
ns,
washi
n
g m
achi
n
es,
hi
g
h
-
en
d
pum
ps, a
n
d
i
n
ot
he
r ap
pl
i
a
nc
es w
h
i
c
h
req
u
i
r
e hi
g
h
reliab
ility an
d
efficien
cy.
Th
e con
t
ro
ller m
u
st
d
i
rect th
e ro
tor ro
tation
;
th
e co
n
t
ro
ller requ
ires so
m
e
mean
s o
f
d
e
termin
in
g
the
ro
t
o
r's orien
t
atio
n
/
po
sition
(relativ
e to
th
e
stato
r
co
ils).
Sev
e
ral
d
e
sign
s u
s
e
Hall Effect sen
s
o
r
s or a ro
tary
enco
de
r t
o
di
r
ect
l
y
m
easure t
h
e r
o
t
o
r'
s po
s
i
t
i
on.
A t
y
pi
ca
l
cont
rol
l
e
r c
o
nt
ai
ns
3
bi
-
d
i
r
ect
i
onal
o
u
t
p
ut
s (i
.e.
fre
que
ncy
c
o
nt
rol
l
e
d
t
h
ree
p
h
ase
o
u
t
p
ut
),
whi
c
h a
r
e c
o
n
t
rol
l
e
d
by
a
l
o
gi
c ci
rc
ui
t
s
.
D
i
ffere
nt
m
e
t
hods a
r
e
accessible for
cont
rol the s
p
eed of BLDC
m
o
tor, lik
e Pulse W
i
dth M
o
dulation (P
WM), DC link variable
vol
t
a
ge
. T
h
e
B
L
DC
m
o
t
o
r cont
rol
based
on
r
o
t
o
r
p
o
si
t
i
on s
e
nsi
ng
sc
hem
e
and p
h
a
s
e cur
r
e
n
t
s
t
h
at
t
h
e
m
odi
fi
ed P
W
M
si
gnal
s
t
o
reduce t
h
e cur
r
e
nt
and
hence r
e
sul
t
i
ng l
o
wer
t
o
r
que ri
ppl
es i
n
[4]
.
I
n
[
1
]
,
B
L
DC
M
dri
v
e t
r
a
p
ezoi
d
al
si
g
n
al
has
bee
n
i
m
pl
em
ent
e
d
by
Si
m
p
l
e
di
gi
t
a
l
PWM
co
nt
r
o
l
a
n
d
FP
GA
i
s
use
d
t
o
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
089
-48
64
I
J
RES Vo
l. 4
,
N
o
. 1
,
Mar
c
h
20
15
:
42
–
54
43
veri
fi
cat
i
o
n o
f
expe
ri
m
e
nt
al
resul
t
s
.
Due t
o
t
h
e sim
p
le con
t
ro
l it h
a
s b
e
en
im
p
l
e
m
en
ted
sp
eci
fic lo
w co
st
ap
p
lication
.
Un
d
e
r
v
a
ries
con
d
ition
o
f
l
o
ad d
i
sturb
a
n
ce, red
u
c
tion
i
n
p
r
o
cesso
r cap
a
b
i
lity, p
o
t
en
tial stab
ilit
y
issu
es
d
u
e
to
th
e sim
p
lici
t
y
o
f
t
h
is co
n
t
ro
l
to
be inv
e
stig
ated
. Th
e closed
loop
system
o
f
stab
ility
to
be
an
alyzed
b
y
usin
g
Lyapun
ov
stab
ility criteri
a [9
]. To
im
p
l
emen
ted
cu
rren
t an
d
p
o
s
ition
co
n
t
ro
llers in
a
sin
g
l
e
FPGA ch
ip
i
n
th
is syste
m
to
d
e
velop
a flex
ib
le, con
f
igurab
le, co
m
p
act
an
d
h
i
g
h
-p
erform
an
ce o
f
BLDCM
cont
rol
sy
st
em
[1
3]
.
In
t
h
is
work the PI con
t
ro
ller
is u
s
ed
for co
ntro
l th
e
sp
eed
o
f
t
h
e m
o
to
r.
Th
e con
t
ro
l al
g
o
rith
m
h
a
v
e
been
de
vel
o
pe
d an
d t
e
st
ed b
y
FPGA
pr
oce
ssor
.
Th
e ex
pe
ri
m
e
nt
al
anal
ysi
s
i
s
perf
orm
e
d t
o
t
e
st
t
h
e co
nt
r
o
l
l
e
r
with
respect
to steady state, transien
t. The robust
n
ess
of the
controller also
t
e
st
ed
by
va
ry
i
ng t
h
e l
o
ad
t
o
rq
ue
.
Thi
s
pape
r
or
g
a
ni
zed a
s
f
o
l
l
o
ws,
b
r
i
e
f a
b
o
u
t
B
L
DC
M
an
d
co
nve
rt
er i
n
sect
i
on
2.
The
im
pl
em
ent
a
t
i
on
o
f
FPG
A
pr
ocess
o
r
di
sc
usse
d i
n
sect
i
o
n
3.
S
ect
i
on
4
di
scu
sses t
h
e
co
nt
r
o
l
st
r
u
ct
u
r
e
of
B
L
DC
M
.
Sec
t
i
o
n
5
di
scuss
e
s t
h
e e
xpe
ri
m
e
nt
al
set
up.
Ex
peri
m
e
nt
al
resul
t
s
di
s
c
usse
d i
n
sect
i
on
6 a
nd c
o
ncl
udi
ng t
h
e rem
a
rks i
n
sect
i
on 7.
2.
BLDC MOT
O
R D
R
IVE
Brus
hless DC
m
o
tor (BLDC) is a
brus
hless m
o
tor
because there
are
no brushes and c
o
mm
uta
t
or.
In
BLDC Mo
tor th
e co
mm
u
t
atio
n
is act with
the h
e
lp
o
f
el
ectronic circ
uit, which
decr
ease
s
the m
echanic loss
e
s
and im
prove
s
the efficiency. A B
r
ushless
DC m
o
tor
has
a rotor
with
perm
anent m
a
g
n
ets a
n
d a stat
or with
wind
ing
s
.
In
t
h
e
1
970
s, a m
a
g
n
e
t sen
s
i
n
g d
i
o
d
e
,
who
s
e sen
s
itiv
ity is al
mo
st tho
u
sand
s
o
f
tim
es g
r
eater th
an
that of t
h
e
Hall ele
m
ent, was
use
d
succes
sfully for t
h
e c
o
ntrol of BL
DC
m
o
tor.
Prese
n
tly the electrical and
el
ect
roni
cs
i
n
dust
r
y
w
a
s
d
e
vel
o
pi
n
g
,
a l
a
rge
n
u
m
b
er
of
hi
gh
-
p
er
fo
r
m
ance p
o
w
er
sem
i
conduct
o
rs a
n
d
perm
anent m
a
gnet m
a
terials like sam
a
rium
cobalt an
d Neo
d
y
m
iu
m
-Iron
-
Bo
r
on (N
d
F
eB)
em
erged,
whic
h
co
nv
en
tio
n
a
lly
a so
lid
g
r
ound
f
o
r
w
i
d
e
spr
e
ad
u
s
e of
BLDC
m
o
to
r
s
. Th
e clo
s
ed
lo
op
co
n
t
r
o
l of
BLDCM i
s
sho
w
n i
n
Fi
gu
r
e
1.
Fi
gu
re
1.
B
a
si
c B
l
ock
Di
a
g
ra
m
of B
L
DC
M
o
t
o
r
A B
L
DC
has s
e
veral
ad
va
nt
ages o
v
er ot
her
m
achi
n
es types. BLDCM is
a potentially cleaner,
m
o
re
efficient, less
noise
, faster a
nd m
o
re
reliab
l
e. Mo
st esp
e
cially
th
ey req
u
i
re lower m
a
in
ten
a
n
c
e du
e to
th
e
elimination of the
m
echanical comm
u
t
at
or. I
t
al
so has hi
g
h
po
wer
densi
t
y
. The speci
fi
cat
i
on o
f
t
h
e B
L
D
C
Mo
to
r is sh
own
in th
e
Tab
l
e
1
.
Table
1. BL
DC Motor Speci
fications
Type
Trapezoidal
Motor
Motor Power Rati
ng
1 HP
Voltage
310V DC
No.
of Poles
4.
00
Continu
ous Stall Cur
r
e
nt
4.
52 A
Continu
ous Stall T
o
r
que
2.
20Nm
Voltage constant (
K
e)
5volts
T
o
r
que constant (Kt)
0.
49Nm
M
a
x.
speed
4600 r
p
m
M
o
m
e
nt of iner
tia
(
J
m
)
1.
8/1.
4kg cm
2
Phase / Phase Resi
stance ±10% at 25°C
3.07 oh
m
Phase / Phase inductance
6.
57M
h
E
l
ectr
i
cal ti
m
e
constant
2.
14
m
s
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
RES I
S
SN
:
208
8-8
7
0
8
Im
pl
eme
n
t
a
t
i
o
n
of
PI
C
o
nt
rol
l
er f
o
r
3
ф
BL
D
C
M Drive
Usi
n
g
FP
GA
(S
.M. Ram
e
sh
Ba
la
ji)
44
2.
1.
Intellig
ent Po
wer
Mo
dul
e (IPM)
IPM
ba
sed
p
o
w
er m
o
d
u
le w
o
r
k
as
DC-
D
C
Con
v
e
r
ter (C
h
o
p
p
e
r)
or
DC
-
A
C Co
nv
erter
(I
nve
rter
).
It
wo
rk
s usi
ng a
n
I
G
B
T
base
d
IPM
an
d w
o
r
k
s on
basi
s of s
o
ft
ware f
r
om
SPAR
T
A
N
-
6
Pro
cesso
r. T
h
e
po
wer
m
odule can be
use
d
for
studying the
ope
ra
tion
of choppe
r, t
h
ree
phase
inve
rter, single phase i
nve
rter and
sp
eed
co
n
t
ro
l
o
f
t
h
ree ph
ase in
du
ction
m
o
to
r, sing
le ph
ase ind
u
c
tion
m
o
to
r. In
tellig
en
t Po
wer M
o
d
u
l
es
(IPMs
) are a
d
vanced
hybrid
powe
r de
vi
ces th
at co
m
b
in
e h
i
g
h
e
r sp
eed, lower lo
ss IGBTs with
op
timiz
ed
g
a
te
dri
v
e an
d pr
ot
ect
i
on ci
rcui
t
r
y
.
Hi
ghl
y
effe
ct
i
v
e sho
r
t
-
ci
rc
ui
t
and o
v
er
-c
ur
rent
p
r
ot
ect
i
on i
s
real
i
zed
t
h
r
o
u
g
h
t
h
e use
of a
d
v
a
nced c
u
rre
nt
sense
IGB
T
c
h
i
p
s t
h
at
al
l
o
w co
nt
i
n
uo
us
m
oni
t
o
ri
ng
of
po
we
r de
vi
ce
cur
r
ent
.
IPM
has
bee
n
opt
i
m
i
zed for
m
i
nim
u
m
swi
t
chi
n
g l
o
sses i
n
or
der t
o
m
eet i
n
d
u
st
ry
dem
a
nds
f
o
r ac
ou
st
i
cal
ly
n
o
i
seless inv
e
rters with carrier
f
r
e
que
nci
e
s
u
p
t
o
2
0
K
H
z.
2.
2
.
Power Conver
ter
The Voltage Source Inverter
(VSI)
i
s
use
d
t
o
creat
e si
n
g
l
e
or
pol
y
p
h
ase
AC
v
o
l
t
a
ges
fr
om
a DC
sup
p
l
y
. It
c
ons
i
s
t
s
of I
G
B
T
s
w
i
t
c
hes an
d
di
ode
s. I
f
si
n
g
l
e
-
pha
se VS
Is, t
h
e swi
t
c
hes
of a
n
y
l
e
g o
f
t
h
e i
nve
rt
er
(SW1 a
n
d SW4, SW3 and SW6, or
SW5 a
nd
SW2) cannot be s
w
itche
d
on
sim
u
ltaneously because t
h
is woul
d
resu
lt in
a sh
ort circu
it acro
s
s th
e d
c
lin
k
vo
ltag
e
sup
p
l
y.
T
h
e standard three-phase
VSI t
o
pology is shown i
n
Fi
gu
re 2.
Fi
gu
re 2.
3
Ф
Phase
V
oltage
Source Inve
rter Circuit
Si
m
ilarly,
in
o
r
d
e
r to
avo
i
d
in
d
e
term
in
ate s
t
ates in
th
e VSI, and
thu
s
ind
e
term
in
ate ac
o
u
t
pu
t lin
e
v
o
ltag
e
s, t
h
e switch
e
s
of an
y leg
o
f
th
e inverter cann
o
t
be switch off si
m
u
l
t
an
eo
usly as th
is
will resu
lt i
n
v
o
ltag
e
s th
at
will d
e
p
e
nd
u
pon
th
e
resp
ective lin
e curren
t
po
larity. In
th
is
case, th
e ac line cu
rren
ts freewh
eel
th
ro
ugh
eith
er
th
e upp
er or lower co
m
p
on
ents.
3.
SPAR
TAN
-
6
FPGA
PR
OCESSOR
Th
e
X
ilin
x
Spar
tan
-
6
FPG
A
p
r
o
cessor
is
a d
e
m
o
n
s
tr
ation
p
l
atf
o
r
m
in
t
e
n
d
e
d
f
o
r
you to
b
e
co
m
e
fam
i
liar with
th
e n
e
w feat
u
r
es an
d
av
ailab
ility o
f
th
e
Sp
art
a
n
-
6
FPGA famil
y
. Th
e Sp
artan
-
6
fam
i
l
y
p
r
o
v
i
d
e
s
lead
in
g system in
teg
r
ation
cap
a
b
ilities with th
e lowest to
t
a
l co
st fo
r
h
i
gh
-vo
l
u
m
e ap
p
licatio
n
s
. B
u
ilt o
n
a
matu
re 4
5
n
m
lo
w-po
wer cop
p
e
r pro
cess tech
no
log
y
th
at
d
e
liv
ers th
e
op
ti
m
a
l, p
o
w
er, b
a
lan
ce of cost and
perform
a
nce, the Spartan-6 fa
m
i
ly o
ffers a n
e
w, m
o
re efficien
t, du
al-reg
ister 6-inp
u
t
lo
ok
up
tab
l
e (LUT)
lo
g
i
c an
d a
rich
selection
o
f
bu
ilt-in
system
-l
ev
el b
l
o
c
ks.
Th
e arch
itecture o
f
Xilinx
Sp
artan
-
6
FPGA pro
cessor
is shown in
Figu
re
3.
These featu
r
es prov
id
e a
l
o
w c
o
st
pr
og
ram
m
a
bl
e al
t
e
rnat
i
v
e t
o
c
u
st
om
ASIC
p
r
o
duct
s
wi
t
h
u
n
p
rece
de
nt
ed e
a
sy
t
o
use
.
S
p
art
a
n-
6
FPGAs
offer
th
e
b
e
st so
lu
t
i
o
n
fo
r h
i
g
h
-v
o
l
u
m
e lo
g
i
c d
e
si
g
n
s
, co
st
-sen
sitiv
e emb
e
dd
ed
app
licatio
n
s
,
co
nsu
m
er-orien
ted
DSP
d
e
sig
n
s
. Sp
artan-6 FPGAs are
th
e p
r
og
ramm
a
b
le
silico
n
fo
un
d
a
tion
fo
r Targ
et
ed
Design
Platfo
rm
s
th
at d
e
liv
er in
tegrat
ed s
o
ft
ware a
n
d
har
d
ware c
o
m
p
o
n
e
n
ts
that e
n
able
designers to
focus
on
i
n
n
ovat
i
o
n
as s
o
o
n
a
s
t
h
ei
r
de
vel
o
pm
ent
cy
cle be
gi
ns
.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
089
-48
64
I
J
RES Vo
l. 4
,
N
o
. 1
,
Mar
c
h
20
15
:
42
–
54
45
Fig
u
re 3
.
Arch
i
t
ectu
r
e o
f
Xilinx
Sp
artan
-
6
FPGA
Pro
cessor
4.
BLDC MOT
O
R CO
NTR
O
L
STR
UCT
U
R
E
Th
e am
p
litu
d
e
o
f
th
e app
lied
v
o
ltag
e
is ad
justed
by
usi
n
g
t
h
e P
W
M
t
e
c
h
n
i
ques
.
T
h
e
req
u
i
r
e
d
s
p
e
e
d
is controlled by a speed controller. T
h
e s
p
e
e
d control
is i
m
p
l
e
m
en
ted
as a co
nv
en
tion
a
l PI co
n
t
ro
ller. The
di
ffe
re
nce bet
w
een t
h
e act
ua
l
and re
fere
nce
speed i
s
i
n
p
u
t
t
o
t
h
e PI c
o
nt
r
o
l
l
e
r base
d
on
t
h
i
s
di
ffe
re
nce,
t
h
e PI
co
n
t
ro
ller con
t
ro
ls th
e du
ty cycle o
f
PW
M p
u
l
ses fed
to
th
e v
a
riab
le DC
lin
k
3
Ф
in
vert
er, w
h
ich co
rre
spo
n
d
s
to
th
e
vo
ltag
e
a
m
p
litu
d
e
required
t
o
keep
t
h
e requ
ired
sp
eed
.
Th
e con
t
ro
l
stru
cture
o
f
BLDC m
o
to
r is
sh
own
in
Figur
e
4
.
Fi
gu
re
4.
B
L
D
C
M
PI c
o
nt
rol
st
ruct
u
r
e
4.
1. Desi
gn of
Speed C
o
ntr
o
l
l
er
The re
fere
nce spee
d (
ω
*) is com
p
ared to the spee
d signa
l
(
ω
) to produce a speed
error signal (e
).
Th
en
I*
is achiev
ed
b
y
in
tegral g
a
in (KI),
p
r
op
orti
onal
gain (Kp) a
n
d s
p
eed error(e
).
The PI
base
d
spee
d
cont
rol
l
e
r i
s
sh
ow
n i
n
Fi
gu
re
5.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
RES I
S
SN
:
208
8-8
7
0
8
Im
pl
eme
n
t
a
t
i
o
n
of
PI
C
o
nt
rol
l
er f
o
r
3
ф
BL
D
C
M Drive
Usi
n
g
FP
GA
(S
.M. Ram
e
sh
Ba
la
ji)
46
Fi
gu
re
5.
PI
B
a
sed S
p
ee
d C
o
n
t
rol
l
e
r
Whe
r
e,
Kv : In
tegral gain
Kp : Propo
rtion
a
l g
a
i
n
e: Er
ro
r
e
ω
∗
ω
(
1
)
Th
e
p
r
op
ortional an
d in
teg
r
al
term
s is g
i
v
e
n
b
y
V
∗
e
k
ek
(
2
)
4.
2
P
W
M
C
o
nt
rol
Str
a
te
g
y
In t
h
i
s
sy
st
em
ha
ve
been
us
ed P
u
l
s
e
W
i
dt
h M
odulation
techniques
. T
h
ese techniques
are m
o
st
efficient a
nd t
h
ey control the
dri
v
es of the
s
w
itching
devic
e
s. Different PWM t
echnique
s
are accessi
ble, like
sin
g
l
e, m
u
ltip
le, sin
u
so
i
d
al an
d
m
o
d
i
fied
sin
u
s
o
i
d
a
l PWM. Ou
t
o
f
th
e ab
ov
e techn
i
q
u
e
, sinu
so
id
al PW
M
t
echni
q
u
es a
r
e
m
o
st
wi
del
y
use
d
. They
c
o
nt
r
o
l
t
h
e out
p
u
t
vol
t
a
ge as wel
l
as red
u
ce
t
h
e harm
oni
c
s
. The
si
nus
oi
dal
p
u
l
s
e wi
dt
h m
odul
at
i
on (
P
W
M
) i
s
m
o
st
wi
del
y
use
d
m
e
t
hod
o
f
v
o
l
t
a
ge c
o
nt
r
o
l
i
n
i
n
ve
rt
ers.
The
wi
dt
h
of eac
h
pul
se i
s
wei
g
ht
ed by
t
h
e a
m
pli
t
ude si
ne wave at
t
h
e i
n
st
ant
[
8
]
.
Th
e carri
er si
g
n
a
l
i
s
a
t
r
apez
oi
dal
wa
ve
of
f
r
eq
ue
nc
y
‘fc
’ a
n
d
am
pl
i
t
ude ‘
V
c
’
. T
h
e co
nt
r
o
l
si
g
n
a
l
i
s
a si
ne
wa
v
e
o
f
fre
que
ncy
‘f
’ a
n
d
am
pl
i
t
ude ‘
V
r
’
.
He
re
f
beco
m
e
s t
h
e f
r
eq
ue
ncy
o
f
t
h
e
out
put
i
nve
rt
er.
T
h
e si
ne
wave
a
n
d
t
r
a
p
ezoi
d
al
wave
s
are c
o
m
p
ared a
n
d the
PW
M
signal is
pr
ep
ar
ed
sh
own
i
n
Fi
gu
r
e
6.
Fi
gu
re
6.
P
W
M
Gen
e
rat
i
o
n
Lo
gi
c
From
t
h
i
s
P
W
M
,
t
h
e
dri
v
es
f
o
r
t
h
e
IGB
T
i
n
t
h
e i
n
ve
rt
er
pr
epare
d
t
h
e
out
put
wa
vef
o
rm
of
t
h
e
bri
d
g
e
i
nve
rt
er whe
n
si
ne
P
W
M
dri
v
es
a
r
e
a
ppl
i
e
d. A
v
era
g
e ou
t
put
vol
t
a
ge
i
s
co
nt
rol
l
e
d
t
h
r
o
u
g
h
dut
y
cy
c
l
e
of
P
W
M
.
The
rel
a
t
i
ons
hi
p bet
w
een
a
v
era
g
e o
u
t
put
vol
t
a
g
e
, d
u
t
y
cy
cl
e
an
d
i
n
p
u
t
vol
t
a
g
e
i
s
,
V
avg
= D V
input
(
3
)
Whe
r
e,
D =
Duty cycle
Vav
g
=
A
v
e
r
a
g
e
out
put
v
o
l
t
a
ge
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
089
-48
64
I
J
RES Vo
l. 4
,
N
o
. 1
,
Mar
c
h
20
15
:
42
–
54
47
Vi
n
put
=
I
n
put
DC
vol
t
a
ge
5.
E
X
PERI
MEN
T
AL SETUP
The de
vel
o
pm
ent
co
nt
rol
sy
s
t
em
i
s
t
e
st
ed on a FPG
A
bas
e
d B
L
DC
M
o
t
o
r
dri
v
e set
up
i
n
El
ect
ri
cal
Dri
v
es an
d C
o
nt
r
o
l
l
a
bo
rat
o
r
y
at
K.S.R
a
ng
as
amy co
lleg
e
o
f
tech
no
log
y
. Th
e BLDCM is a 3
Ф
31
0
V
,
1H
p,
Trap
ezo
i
dal ty
p
e
m
ach
in
e. A d
i
od
e rectifier with
VSI is asse
m
b
led
in
a B
L
DCM in
tellig
en
t p
o
wer m
o
du
le. A
Hall Effect vol
t
age and c
u
rre
n
t sensor
was
used to provi
d
e
accurate i
n
forma
tion for t
h
e
angle c
o
ntrol a
s
in the
form
o
f
v
o
ltage p
u
l
ses. A shu
n
t
DC m
o
to
r was coup
led
i
n
th
e BLDCM sh
aft.
It ex
citatio
n
is con
t
rolled
b
y
30
V
DC
p
o
we
r
su
p
p
l
y
an
d
ge
nerat
o
r,
re
si
st
o
r
t
o
a l
o
ad
.
Hall-effect c
u
rre
nt sens
ors a
r
e
us
ed
for m
easuri
n
g the
current.
A loa
d
cell is used t
o
m
eas
u
r
e th
e to
rq
u
e
an
d
its
v
a
lu
es are ind
i
cated
in
to
rqu
e
in
d
i
cator. Th
e to
tal
dri
v
e sy
st
em
is co
nt
rol
l
e
d by
SPAR
T
A
N
-
6
FPG
A
pr
ocess
o
r
.
The
bl
ock
di
ag
ram
of Ex
peri
m
e
nt
al
setup
a
n
d
FPG
A c
o
nt
rol
l
ed B
L
DC
M
d
r
i
v
e i
s
s
h
ow
n i
n
Fi
gu
re
7.
Fi
gu
re
7.
B
l
ock
Di
a
g
ram
o
f
B
L
DC
M
o
t
o
r
Dri
v
e
Th
e Sp
artan-6 FPGA enh
a
nce
m
en
ts, co
m
b
in
e
with
a
dvanced process
technology,
deliver m
o
re
fun
c
tion
a
lity a
n
d
b
a
ndwid
th
p
e
r
d
o
llar th
an was p
r
ev
iou
s
l
y
p
o
ssib
l
e. The clo
c
k
w
ise
d
i
rectio
n
o
f
th
e
sen
s
or
and
d
r
i
v
e
i
s
s
h
ow
n i
n
Ta
bl
e
1
.
Tabl
e
1.
Sens
o
r
C
l
oc
kwi
s
e
Di
rect
i
o
n
o
f
Dri
v
e
Sensor
Clockwise
Dir
ection
A
B
C
1
2 3 4
5
6
0 0
1
0
0 0 1
1
0
0 1
0
1
0 0 0
0
1
0 1
1
1
0 0 1
0
0
1 0
0
0
1 1 0
0
0
1 1
0
0
0 1 0
1
0
1 1
1
0
0 1 0
0
1
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
RES I
S
SN
:
208
8-8
7
0
8
Im
pl
eme
n
t
a
t
i
o
n
of
PI
C
o
nt
rol
l
er f
o
r
3
ф
BL
D
C
M Drive
Usi
n
g
FP
GA
(S
.M. Ram
e
sh
Ba
la
ji)
48
5.1. I
m
plementa
tion of P
I
Controller
The PI s
p
ee
d cont
rol
al
g
o
ri
t
h
m
source co
d
e
has bee
n
de
vel
o
ped
usi
n
g
Spa
r
t
a
n-
6 FP
G
A
pr
oces
so
r
t
h
r
o
u
g
h
t
o
t
h
e
VH
DL
pr
o
g
ra
m
and d
o
w
nl
o
a
ded i
n
t
o
t
h
e
target FPGA proces
sor. T
h
e
PC m
achine and t
h
e
t
a
rget
pr
ocess
o
r
w
e
re
i
n
t
e
rfa
c
e
d usi
n
g USB
cabl
e
.
Fi
gu
re 8.
Im
pl
em
ent
a
t
i
on of PI
C
ont
rol
Al
g
o
ri
t
h
m
The
ph
ot
o
g
r
ap
h o
f
t
h
e e
x
per
i
m
e
nt
al
set
up
i
s
sho
w
n i
n
Fi
gu
re
9. Fl
ow
chart
f
o
r t
h
e
v
a
ri
o
u
s st
ep
s
in
vo
lv
ed
in th
e d
e
si
g
n
of PI co
n
t
ro
l al
g
o
rithm
is sh
own
in
Fig
u
re
8
.
6.
E
X
PERI
MEN
T
AL RES
U
L
T
AN
D
DI
SC
USSI
ON
The
ph
ot
og
rap
h
of e
x
peri
m
e
nt
set
up
f
o
r
spe
e
d c
ont
rol
of
B
L
DC
m
o
t
o
r t
h
r
o
u
g
h
S
P
AR
T
A
N-
6 F
P
G
A
k
it and
d
a
ta acq
u
i
sition
system
is sh
own
in th
e Fi
g
u
re
9
.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
089
-48
64
I
J
RES Vo
l. 4
,
N
o
. 1
,
Mar
c
h
20
15
:
42
–
54
49
Fi
gu
re
9.
Pi
ct
o
r
i
a
l
vi
ew
o
f
e
x
peri
m
e
nt
set
u
p
o
f
B
L
DC
M
o
t
o
r
6.
1.
Open
L
o
o
p
Spee
d
Co
nt
rol
A
n
al
ysi
s
The O
p
e
n
-l
oo
p
sy
st
em
al
so re
fer
r
ed t
o
as
n
o
n
-
f
eed
bac
k
sy
s
t
em
and i
t
i
s
a
t
y
pe of c
ont
i
n
u
ous c
o
nt
r
o
l
sy
st
em
i
n
w
h
i
c
h t
h
e
out
put
ha
s n
o
i
n
fl
uence
or
ef
fect
o
n
t
h
e co
nt
r
o
l
act
i
o
n
of
t
h
e
i
n
put
si
gnal
.
T
h
e el
e
c
t
r
i
cal
ch
ar
acter
istics o
f
BLD
C
M
obtain
e
d
r
e
su
lts i
s
show
n in
t
h
e
Fig
u
r
e
s
10
–
13
.
Figu
re
1
0
. E
ffi
ciency
Vs
O
u
t
put
Po
we
r (
W
)
Fig
u
r
e
11
.
Line Cu
rr
en
t (A
)
V
s
O
u
tp
u
t
Pow
e
r (W
)
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
RES I
S
SN
:
208
8-8
7
0
8
Im
pl
eme
n
t
a
t
i
o
n
of
PI
C
o
nt
rol
l
er f
o
r
3
ф
BL
D
C
M Drive
Usi
n
g
FP
GA
(S
.M. Ram
e
sh
Ba
la
ji)
50
Fi
gu
re 1
2
. Spe
e
d (r
pm
)
Vs O
u
t
p
ut
P
o
we
r (
W
)
Fi
gu
re 1
3
.
T
o
r
que
(
N
m
)
Vs Out
put
Po
we
r (
W
)
Mechanical characteristics of the
pr
o
pos
ed
sy
st
em
open l
o
o
p
s
p
eed c
o
n
t
rol
sy
st
em
ob
t
a
i
n
ed res
u
l
t
are sh
own
in Fig
u
re
1
4
.
Here, sp
eed
o
f
th
e
syste
m
is re
d
u
c
ed
an
d torqu
e
will b
e
attain
ed
co
nstan
t
stall to
rqu
e
.
Fi
gu
re 1
4
. Spe
e
d (r
pm
)
Vs
T
o
r
q
ue
(
N
m
)
6.
2.
Ste
a
d
y
S
t
ate
An
al
ysi
s
It is th
e ab
ility
o
f
electrical mach
in
e or
power
syst
e
m
to
reg
a
i
n
its orig
i
n
al/p
rev
i
ou
s
state is called
Stead
y state stab
ility. Th
e st
ab
ility o
f
a sy
ste
m
refers to
th
e ab
ility o
f
a syste
m
to
ret
u
rn
t
o
its stead
y
state
whe
n
s
u
bject
e
d
t
o
a
di
st
u
r
ba
nce.
In
t
h
i
s
sy
st
em
have a
n
a
l
y
s
i
s
un
der
n
o
l
o
ad
, di
ffe
ren
t
t
o
rq
ue a
n
d v
a
ri
abl
e
to
rq
u
e
with th
e con
s
tan
t
sp
eed.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
089
-48
64
I
J
RES Vo
l. 4
,
N
o
. 1
,
Mar
c
h
20
15
:
42
–
54
51
A. Cons
tant S
p
eed at
No
L
o
ad
Figure
15.
Spe
e
d Res
p
onse
at N
o
L
o
a
d
B. Cons
tant S
p
eed with
Constant Tor
que
Fi
gu
re
1
6
.
Spe
e
d R
e
s
p
o
n
se
w
i
t
h
C
o
nst
a
nt
T
o
r
q
ue
C.
Cons
tant
S
p
eed with
Var
i
able Tor
que
Figu
re
1
7
.
Spe
e
d Res
p
o
n
se
w
ith Va
riable T
o
rq
ue
To analysis the stability of the
propose
d system
unde
r differe
n
t load
c
ondition
with constant s
p
eed.
Spee
d of
the
m
o
tor has been
occurred
s
o
m
e
chan
ges
i
n
u
nde
r t
h
ese
co
n
d
i
t
i
ons
s
h
o
w
n i
n
t
h
e Fi
gu
res
1
8
-
2
0
.
Evaluation Warning : The document was created with Spire.PDF for Python.