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y
in
b
o
th
co
m
m
er
cial
l
y
an
d
p
r
iv
atel
y
p
r
o
d
u
ce
d
p
r
o
d
u
cts.
Mo
d
er
n
S
y
s
te
m
-
on
-
a
-
C
h
ip
(
S
o
C
)
d
esig
n
i
n
te
g
r
ates
m
an
y
co
r
es
in
to
a
s
in
g
le
ch
ip
.
A
n
d
s
o
m
e
o
f
th
e
m
ar
e
e
m
b
ed
d
ed
an
d
ca
n
n
o
t
b
e
ac
c
ess
ed
d
ir
ec
tl
y
f
r
o
m
th
e
o
u
ts
id
e
o
f
th
e
ch
ip
.
T
h
u
s
test
i
n
g
t
h
ese
e
m
b
ed
d
ed
co
r
es i
s
a
g
r
ea
t c
h
alle
n
g
e
in
SOC
d
es
ig
n
s
.
I
n
t
h
is
p
ap
er
,
in
ter
n
al
d
iag
n
o
s
tic
ca
p
ab
ilit
ie
s
ar
e
b
u
ilt
i
n
to
U
A
R
T
b
y
t
h
e
in
tr
o
d
u
ctio
n
o
f
B
u
ilt
-
In
-
Self
-
T
est
(
B
I
ST
)
.
T
h
e
UART
w
it
h
s
tatu
s
r
eg
i
s
ter
an
d
B
I
ST
m
o
d
u
le
is
co
d
ed
in
Ver
ilo
g
H
DL
a
n
d
s
i
m
u
la
ted
u
s
i
n
g
Mo
d
elSi
m
a
n
d
s
y
n
t
h
es
ized
u
s
in
g
Xil
in
x
XST
to
o
l.
T
h
e
co
m
p
lete
i
m
p
le
m
e
n
tatio
n
an
d
v
alid
atio
n
is
d
o
n
e
o
n
Sp
ar
tan
3
E
FP
GA
.
T
h
e
p
ap
er
is
o
r
g
an
ized
in
t
o
5
s
ec
tio
n
s
.
I
n
s
ec
tio
n
2
d
escr
ib
es
t
h
e
B
I
ST
tech
n
iq
u
e
a
n
d
i
m
p
le
m
e
n
ta
tio
n
p
o
s
s
ib
ilit
ies.
T
h
e
s
ec
tio
n
3
d
escr
ib
es
t
h
e
a
r
ch
itect
u
r
e
o
f
U
AR
T
w
i
th
in
t
r
o
d
u
ctio
n
o
f
B
I
ST
tech
n
iq
u
e.
T
h
e
s
ec
tio
n
4
p
r
esen
ts
t
h
e
r
es
u
lts
a
n
d
s
ec
tio
n
5
p
r
o
v
id
es th
e
co
n
c
lu
s
io
n
o
f
w
o
r
k
.
2.
B
I
ST
T
E
CH
N
I
Q
UE
VL
SI
test
in
g
p
r
o
b
le
m
s
li
k
e
T
est
g
e
n
er
atio
n
p
r
o
b
lem
s
,
g
ate
to
I
/O
p
i
n
r
atio
p
r
o
b
le
m
s
,
in
p
u
t
co
m
b
i
n
ato
r
ial
p
r
o
b
le
m
s
ar
e
d
i
s
cu
s
s
ed
an
d
t
h
i
s
m
ad
e
th
e
d
es
ig
n
er
s
to
id
en
t
if
y
r
eliab
le
te
s
t
m
et
h
o
d
s
in
s
o
l
v
in
g
th
ese
d
if
f
ic
u
ltie
s
.
I
n
tr
o
d
u
cin
g
o
f
s
p
ec
ial
test
cir
cu
itr
y
o
n
th
e
VL
SI
cir
cu
it
th
at
allo
w
s
e
f
f
ici
en
t
test
co
v
er
ag
e
i
s
th
e
an
s
w
er
to
th
e
m
atter
.
I
t
h
a
s
b
ee
n
ad
d
r
ess
ed
th
at
th
er
e
is
a
n
ee
d
o
f
d
esig
n
f
o
r
test
ab
ilit
y
(
D
FT
)
an
d
h
en
ce
B
I
ST
g
iv
es
a
s
o
lu
tio
n
f
o
r
th
is
p
r
o
b
lem
.
A
B
I
ST
is
an
o
n
-
ch
i
p
test
lo
g
ic
th
at
is
u
s
ed
to
test
th
e
f
u
n
c
tio
n
al
lo
g
ic
o
f
a
c
h
ip
.
W
it
h
t
h
e
r
ap
id
i
n
cr
e
ase
i
n
t
h
e
d
e
s
ig
n
co
m
p
lex
it
y
,
a
B
I
ST
h
as
b
ec
o
m
e
a
m
aj
o
r
d
esig
n
co
m
p
o
n
e
n
t
i
n
DFT
m
et
h
o
d
s
an
d
is
b
ec
o
m
i
n
g
in
cr
ea
s
in
g
l
y
i
m
p
o
r
ta
n
t in
to
d
ay
‟
s
s
tate
o
f
t
h
e
ar
t SO
C
s
.
B
I
ST
is
an
e
x
e
m
p
tio
n
f
o
r
an
ex
tr
a
h
ar
d
w
ar
e
w
h
ich
is
u
s
e
d
to
test
th
e
ch
ip
an
d
s
i
m
u
l
ta
n
eo
u
s
l
y
it
en
s
u
r
es
th
e
co
s
t
ef
f
ec
ti
v
e,
r
eliab
ilit
y
an
d
test
ab
ilit
y
.
T
est
P
a
tter
n
Gen
er
ato
r
(
T
P
G)
is
a
cir
cu
it
u
s
ed
in
B
I
ST
f
o
r
th
e
g
e
n
er
atio
n
o
f
test
p
atte
r
n
s
.
Fig
u
r
e
1
s
h
o
w
s
a
B
I
ST
m
o
d
u
le
co
m
p
o
s
it
io
n
.
A
g
en
er
ic
B
I
ST
ar
ch
itectu
r
e
co
m
p
o
n
e
n
t i
s
as
f
o
llo
w
s
.
C
ir
cu
it
u
n
d
er
Tes
t
(
C
UT
)
:
T
h
is
is
t
h
e
p
o
r
tio
n
o
f
th
e
c
ir
cu
it
test
ed
in
B
I
ST
m
o
d
e.
I
t
ca
n
b
e
s
eq
u
en
t
ial
cir
cu
i
t,
o
r
a
co
m
b
in
atio
n
al
cir
cu
i
t o
r
a
m
e
m
o
r
y
.
I
t i
s
d
eli
m
i
ted
b
y
t
h
eir
P
r
im
ar
y
I
n
p
u
t (
P
I
)
an
d
P
r
i
m
ar
y
O
u
tp
u
t (
P
O)
.
Tes
t
P
a
tter
n
Gen
era
to
r
(
T
P
G
)
:
T
h
e
test
p
atter
n
s
w
h
ich
ar
e
r
eq
u
ir
ed
to
test
t
h
e
C
UT
ar
e
g
en
er
ated
b
y
T
P
G.
T
h
e
p
atter
n
s
m
a
y
b
e
g
en
er
ated
in
p
s
eu
d
o
r
an
d
o
m
s
eq
u
en
ce
.
No
r
m
a
ll
y
t
h
e
p
atter
n
g
en
er
ato
r
g
e
n
er
ates
ex
h
a
u
s
tiv
e
i
n
p
u
t te
s
t p
atter
n
s
t
o
th
e
C
UT
to
en
s
u
r
e
th
e
h
i
g
h
f
au
lt c
o
v
er
a
g
e.
Tes
t R
esp
o
n
s
e
A
n
a
lysi
s
(
T
R
A
)
: I
t c
o
m
p
ar
es t
h
e
o
b
tain
ed
o
u
t
p
u
t v
al
u
e
w
it
h
ex
p
ec
ted
o
u
tp
u
t v
alu
e.
Fig
u
r
e
1
.
A
Ge
n
er
ic
B
I
ST
Mo
d
u
le
B
I
S
T
C
o
n
tr
o
ller
Un
it
(
B
C
U)
:
T
h
is
u
n
it
co
n
tr
o
ls
all
th
e
m
o
d
u
les
;
it
m
a
n
a
g
es
th
e
T
PG
an
d
T
R
A
.
A
l
s
o
r
ec
o
n
f
i
g
u
r
es
t
h
e
C
UT
an
d
t
h
e
m
u
ltip
le
x
er
.
W
h
e
n
i
t
i
s
ac
ti
v
ated
b
y
th
e
No
r
m
al
/T
est
s
i
g
n
al
a
n
d
g
en
er
ate
s
a
Evaluation Warning : The document was created with Spire.PDF for Python.
I
SS
N
:
2
0
8
9
-
4864
IJ
R
E
S
Vo
l.
5
,
No
.
3
,
No
v
em
b
er
20
1
6
:
1
70
–
1
76
172
Go
/No
-
Go
.
W
h
en
it
i
s
i
n
tes
t
m
o
d
e,
test
p
atter
n
g
e
n
er
ato
r
o
u
tp
u
t
is
co
n
n
ec
ted
to
th
e
C
UT
w
h
ile
d
u
r
i
n
g
f
u
n
ctio
n
al
m
o
d
e,
ex
ter
n
al
i
n
p
u
ts
ar
e
co
n
n
ec
ted
to
C
UT
.
T
h
er
e
ar
e
v
ar
io
u
s
ap
p
r
o
ac
h
es
b
ein
g
u
s
ed
to
g
en
er
ate
te
s
t
p
atter
n
s
f
o
r
B
I
ST
s
u
ch
as
L
FS
R
,
R
OM
,
b
in
ar
y
co
u
n
ter
s
,
ce
llu
lar
au
to
m
atio
n
.
T
h
e
b
in
ar
y
co
u
n
ter
ca
n
g
en
er
ate
a
n
e
x
h
a
u
s
ti
v
e
b
u
t
n
o
t
r
an
d
o
m
ized
te
s
t
s
eq
u
en
ce
s
.
T
h
e
d
r
aw
b
ac
k
o
f
b
in
ar
y
co
u
n
ter
s
is
t
h
at
it
r
eq
u
ir
es
m
o
r
e
h
ar
d
w
ar
e
t
h
an
t
y
p
ic
al
L
i
n
ea
r
Feed
b
ac
k
Sh
i
f
t
R
eg
i
s
ter
(
L
FS
R
)
p
atter
n
g
e
n
er
ato
r
.
A
m
o
d
if
ied
co
u
n
ter
also
h
a
s
b
ee
n
s
u
cc
es
s
f
u
l
l
y
w
o
r
k
ed
as
tes
t
-
p
atter
n
g
e
n
er
ato
r
s
.
T
h
u
s
,
th
e
y
also
r
eq
u
ir
e
lo
n
g
te
s
t
s
eq
u
e
n
ce
s
.
W
h
ile
t
h
i
s
m
et
h
o
d
s
to
r
es
a
g
o
o
d
test
p
atter
n
s
et
i
n
a
R
OM
o
n
th
e
c
h
ip
.
Dr
a
w
b
ac
k
o
f
t
h
i
s
ap
p
r
o
ac
h
is
r
ela
tiv
el
y
e
x
p
en
s
iv
e
in
c
h
ip
ar
ea
.
A
L
FS
R
is
u
s
ed
to
g
en
er
ate
p
s
e
u
d
o
r
an
d
o
m
test
p
atter
n
s
.
No
r
m
all
y
it
r
eq
u
ir
es
a
s
eq
u
en
ce
o
f
o
n
e
m
il
lio
n
o
r
m
o
r
e
test
s
p
atter
n
in
o
r
d
er
to
ac
h
iev
e
h
ig
h
f
a
u
lt
co
v
er
ag
e.
T
h
e
ad
v
an
t
ag
e
o
f
L
F
S
R
is
th
eir
co
m
p
ac
t
an
d
s
i
m
p
le
d
esig
n
an
d
t
h
u
s
is
cu
r
r
en
tl
y
t
h
e
p
r
e
f
er
r
ed
B
I
ST
p
atter
n
g
e
n
er
atio
n
m
eth
o
d
.
L
FS
R
is
p
r
ef
er
r
ed
as
a
test
p
att
er
n
g
e
n
er
ato
r
i
n
t
h
is
p
r
o
j
ec
t.
3.
P
RO
P
O
SE
D
UAR
T
ARCH
I
T
E
C
T
UR
E
W
I
T
H
B
I
S
T
T
h
e
p
r
o
p
o
s
ed
ar
ch
itectu
r
e
d
escr
ib
es
th
e
d
esi
g
n
o
f
an
8
-
b
it
UART
an
d
en
h
a
n
ce
s
t
h
e
tes
tab
ilit
y
o
f
cir
cu
it b
y
t
h
e
in
tr
o
d
u
ctio
n
o
f
B
I
ST
m
o
d
u
le
i
s
ex
p
lai
n
ed
in
t
h
e
f
o
llo
w
i
n
g
s
ec
tio
n
s
.
T
h
e
p
r
o
p
o
s
ed
m
o
d
el
h
as
t
w
o
m
aj
o
r
m
o
d
u
le
s
s
u
ch
as
U
AR
T
an
d
B
I
S
T
.
Fu
r
th
er
in
t
h
e
UART
,
w
e
h
av
e
tr
a
n
s
m
itter
,
r
ec
eiv
er
,
an
d
b
au
d
r
ate
g
en
er
ato
r
.
B
I
S
T
h
as
a
co
n
tr
o
l
r
eg
is
ter
,
p
atter
n
g
e
n
er
ato
r
an
d
a
co
m
p
ar
ato
r
,
as sh
o
w
n
i
n
f
i
g
u
r
e
2.
Fig
u
r
e
2
.
UART
w
it
h
B
I
ST
A
r
ch
itect
u
r
e
A.
UART T
ra
n
s
m
it
t
er
T
h
e
tr
an
s
m
itter
ac
ce
p
ts
p
ar
all
el
d
ata
f
r
o
m
p
er
ip
h
er
al/p
r
o
ce
s
s
o
r
,
an
d
m
ak
e
s
t
h
e
f
r
a
m
e
o
f
t
h
e
d
ata
an
d
tr
an
s
m
it
s
th
e
d
ata
in
s
er
ial
f
o
r
m
o
n
t
h
e
T
r
an
s
m
it
ter
Ou
tp
u
t
(
T
XOUT
)
ter
m
i
n
al.
T
h
e
b
au
d
r
ate
g
en
er
ato
r
o
u
tp
u
t
w
ill b
e
t
h
e
clo
ck
f
o
r
UART
tr
an
s
m
i
tter
.
Fig
u
r
e
3
.
UART
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N
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2
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test
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Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
R
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S
I
SS
N:
2088
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8708
A
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F
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175
r
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FIFO.
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x
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is
co
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w
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to
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e
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B
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p
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s
else B
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ail.
4.
RE
SU
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h
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u
r
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9
.
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m
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m
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u
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10
.
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m
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lt o
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u
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Evaluation Warning : The document was created with Spire.PDF for Python.
I
SS
N
:
2
0
8
9
-
4864
IJ
R
E
S
Vo
l.
5
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3
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20
1
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176
5.
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p
atter
n
g
e
n
er
ato
r
b
y
au
to
m
atica
ll
y
g
e
n
er
atin
g
p
s
e
u
d
o
r
an
d
o
m
p
atter
n
s
to
g
iv
e
g
o
o
d
f
au
lt
co
v
er
a
g
e
to
t
h
e
UART
m
o
d
u
le.
T
h
e
ad
d
itio
n
al
B
I
ST
cir
cu
it
in
cr
ea
s
es
t
h
e
h
ar
d
w
ar
e
o
v
er
h
ea
d
an
d
d
esig
n
ti
m
e,
a
n
d
it
eli
m
i
n
ate
s
th
e
n
ee
d
to
ac
q
u
ir
e
h
ig
h
-
en
d
test
er
s
.
He
n
ce
th
e
r
ed
u
ctio
n
o
f
th
e
te
s
t
co
s
t
h
elp
s
in
th
e
r
ed
u
ctio
n
o
f
o
v
er
all
p
r
o
d
u
ctio
n
co
s
t.
RE
F
E
R
E
NC
E
S
[1
]
M
a
h
a
t
N.F
,
“
De
sig
n
o
f
a
9
-
b
it
UA
R
T
m
o
d
u
le
b
a
se
d
o
n
V
e
ri
lo
g
HD
L
”
,
in
th
e
p
ro
c
e
e
d
in
g
s
o
f
1
0
th
I
EE
E
In
ter
n
a
t
io
n
a
l
Co
n
fer
e
n
c
e
o
n
S
e
mic
o
n
d
u
c
to
r
El
e
c
tro
n
ic
s
(
ICS
E)
,
1
9
-
2
1
st
S
e
p
t.
2
0
1
2
,
DO
I:
1
0
.
1
1
0
9
/
S
M
El
e
c
.
2
0
1
2
.
6
4
1
7
2
1
0
,
p
p
.
5
7
0
-
5
7
3
.
[2
]
F
a
n
g
Yi
-
y
u
a
n
a
n
d
Ch
e
n
X
u
e
-
j
u
n
,
“
De
sig
n
a
n
d
S
imu
l
a
ti
o
n
o
f
UART
S
e
ria
l
Co
mm
u
n
ica
ti
o
n
M
o
d
u
le
Ba
se
d
o
n
VHDL”
,
in
th
e
p
ro
c
e
e
d
in
g
s
o
f
3
r
d
In
ter
n
a
ti
o
n
a
l
W
o
rk
sh
o
p
o
n
I
n
t
e
ll
ig
e
n
t
S
y
ste
m
s
a
n
d
A
p
p
li
c
a
t
io
n
s
(IS
A
),
IEE
E
,
M
a
y
2
0
1
1
,
DO
I:
1
0
.
1
1
0
9
/IS
A
.
2
0
1
1
.
5
8
7
3
4
4
8
,
p
p
.
1
-
4.
[3
]
M
o
h
d
Ya
m
a
n
i
Id
n
a
Id
ris,
M
a
sh
k
u
ri
Ya
a
c
o
b
a
n
d
Zai
d
i
Ra
z
a
k
,
“
A
VHDL
Imp
lem
e
n
t
a
ti
o
n
o
f
UA
RT
De
sig
n
wi
th
BIS
T
C
a
p
a
b
i
li
ty”
,
i
n
t
h
e
p
r
o
c
e
e
d
i
n
g
s o
f
M
a
la
y
sia
n
Jo
u
rn
a
l
o
f
Co
m
p
u
ter S
c
ien
c
e
,
J
u
n
e
2
0
0
6
,
Vo
l
.
1
9
(1
),
p
p
.
7
3
-
8
6
.
[4
]
Dr.
G
a
ri
m
a
Ba
n
d
h
a
w
a
r
k
a
r
Wak
h
l
e
,
Iti
A
g
g
a
r
w
a
l
a
n
d
S
h
w
e
ta
G
a
b
a
,
“
S
y
n
th
e
sis
a
n
d
Im
p
lem
e
n
ta
t
io
n
o
f
UART
u
sin
g
VHDL
Co
d
e
s”
,
in
t
h
e
p
r
o
c
e
e
d
in
g
s
o
f
In
tern
a
ti
o
n
a
l
S
y
m
p
o
siu
m
o
n
Co
m
p
u
ter,
Co
n
s
u
m
e
r
a
n
d
Co
n
t
ro
l
,
IEE
E
Ju
n
e
2
0
1
2
,
DO
I:
1
0
.
1
1
0
9
/IS
3
C.
2
0
1
2
.
1
0
.
[5
]
No
rh
u
z
a
im
in
J
a
n
d
M
a
im
u
n
H.H,
“
T
h
e
d
e
sig
n
o
f
h
i
g
h
s
p
e
e
d
UART
”
,
i
n
th
e
p
r
o
c
e
e
d
in
g
s
o
f
A
sia
-
P
a
c
i
f
ic
Co
n
f
e
re
n
c
e
o
n
A
p
p
li
e
d
El
e
c
tro
m
a
g
n
e
ti
c
s,
A
P
A
CE
0
5
,
IEE
E
,
20
-
2
1
st
De
c
.
2
0
0
5
,
DO
I:
1
0
.
1
1
0
9
/A
P
A
CE.
2
0
0
5
.
1
6
0
7
8
3
1
,
p
p
.
5
-
8.
[6
]
Dr.
T
.
V
.
S
.
P
.
G
u
p
ta,
Y
.
Ku
m
a
ri
a
n
d
M
.
A
sh
o
k
Ku
m
a
r
,
“
UART
re
a
l
iza
ti
o
n
wit
h
BIS
T
a
rc
h
i
tec
tu
re
u
s
in
g
VHDL
”
,
i
n
th
e
p
r
o
c
e
e
d
in
g
s
o
f
In
tern
a
ti
o
n
a
l
J
o
u
r
n
a
l
o
f
En
g
in
e
e
rin
g
Re
se
a
rc
h
a
n
d
A
p
p
li
c
a
ti
o
n
s,
F
e
b
ru
a
ry
2
0
1
3
,
V
o
l
.
3
,
Iss
u
e
1
,
IS
S
N:
2
2
4
8
-
9
6
2
2
,
p
p
.
6
3
6
-
6
4
0
.
[7
]
S
h
ik
h
a
Ka
k
a
r,
Ba
l
w
in
d
e
r
S
in
g
h
a
n
d
A
ru
n
Kh
o
sla
,
“
Imp
lem
e
n
t
a
ti
o
n
o
f
BI
S
T
C
a
p
a
b
il
i
ty
u
sin
g
L
F
S
R
T
e
c
h
n
iq
u
e
s
in
UART
”
,
i
n
t
h
e
p
r
o
c
e
e
d
in
g
s o
f
In
t
e
rn
a
ti
o
n
a
l
J
o
u
r
n
a
l
o
f
Re
c
e
n
t
T
re
n
d
s in
En
g
in
e
e
rin
g
,
M
a
y
2
0
0
9
,
Vo
l
1
,
N
o
.
3
.
[8
]
S
y
b
il
le He
ll
e
b
ra
n
d
,
Birg
it
Re
e
b
a
n
d
S
teff
e
n
T
a
rn
ic
k
,
“
Pa
tt
e
rn
Ge
n
e
ra
ti
o
n
fo
r
a
De
ter
min
isti
c
BIS
T
S
c
h
e
me
”
,
in
th
e
p
ro
c
e
e
d
in
g
s
o
f
IEE
E/
A
CM
In
ter
n
a
ti
o
n
a
l
Co
n
f
e
re
n
c
e
o
n
Co
m
p
u
ter
-
A
id
e
d
De
si
g
n
,
ICCA
D
-
9
5
,
Dig
e
st
o
f
Tec
h
n
ica
l
P
a
p
e
rs,
No
v
e
m
b
e
r
1
9
9
5
,
DO
I:
1
0
.
1
1
0
9
/ICCA
D.1
9
9
5
.
4
7
9
9
9
7
,
p
p
.
8
8
-
9
4
.
[9
]
Na
re
sh
,
V
a
tsa
lk
u
m
a
r
a
n
d
V
ik
a
sk
u
m
a
r
P
a
tel,
“
VHDL
Imp
lem
e
n
ta
ti
o
n
o
f
UART
wit
h
S
ta
t
u
s
Reg
ister
”
,
in
th
e
p
ro
c
e
e
d
in
g
s
o
f
In
tern
a
ti
o
n
a
l
Co
n
f
e
r
e
n
c
e
o
n
Co
m
m
u
n
ica
ti
o
n
S
y
ste
m
s
a
n
d
Ne
t
w
o
rk
T
e
c
h
n
o
lo
g
ies
,
IEE
E
Co
m
p
u
ter
S
o
c
iety
,
11
-
1
3
th
M
a
y
2
0
1
2
,
DO
I:
1
0
.
1
1
0
9
/CS
NT
.
2
0
1
2
.
1
6
4
,
p
p
.
7
5
0
-
7
5
4
.
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