Intern
ati
o
n
a
l
Journ
a
l of
Re
con
f
igur
able
and Embe
dded
Sys
t
ems
(I
JRES)
V
o
l.
4, N
o
. 3
,
N
o
v
e
m
b
er
2
015
, pp
. 20
1
~
20
8
I
S
SN
: 208
9-4
8
6
4
2
01
Jo
urn
a
l
h
o
me
pa
ge
: h
ttp
://iaesjo
u
r
na
l.com/
o
n
lin
e/ind
e
x.ph
p
/
IJRES
Dynamic Partial Reconfiguration
with FIR Filter Application
No
op
ur
Asti
k
,
Pri
t
i
Sh
ah
ane
Department o
f
Electronics
and
Tele
com
m
unicati
on Engin
eering
,
S
y
m
b
iosis Intern
ation
a
l Univ
ersit
y
,
Indi
a
Article Info
A
B
STRAC
T
Article histo
r
y:
Received
May 2, 2015
Rev
i
sed
Au
g
10
, 20
15
Accepted Aug 28, 2015
D
y
namic par
tial reconfiguration
has evol
ved as a ver
y
prominent
state of art
for effic
i
ent
are
a
util
iza
tion of
Field
Programmable Gate Array
(FPG
A) a
s
well as significant reduction in its ove
rall power
consumption wh
en proper
l
y
used to lessen th
e idle logic on FPGA. It
provides desired results
even as th
e
com
putation
a
l
c
o
m
p
lexit
y
in
cre
a
s
es in the
fie
l
d o
f
Digita
l Signa
l
Processing.
This paper exp
l
ains D
y
namic Par
tial R
econ
f
igura
t
ion (DP
R
) with
an ex
am
ple
of Finite Impulse response
(FIR)
filter of ord
e
r 1
0
. Initially
RTL
coding for
Direct Form
FIR structure is writ
ten in
Verilog in
fixed point for
m
at for low
pass and high
pass filter
m
odules using
ISE Desi
gn suite. Funct
i
o
n
ing of
th
e
both the modules is verified ind
i
vidua
lly
through
hardware co-simulation on
ZYBO (Zy
nq Board) from Digilent usi
ng Black
Box from
Sy
stem Generator.
Finall
y d
y
n
a
m
i
c
parti
a
l r
econfigu
r
able
FIR filter
with low pass an
d high pas
s
as reconfigur
able modules is implem
ented on
ZYBO using Plan Ahead tool.
Final
comparison of r
e
source utilizati
on with
and
without DPR is
presented
.
Keyword:
DPR
FIR filter im
p
l
e
m
en
tatio
n
System
Genera
tor
Har
d
w
a
re c
o
-si
m
ul
at
i
on
Black
Box
Copyright ©
201
3 Institut
e
o
f
Ad
vanced
Engin
eer
ing and S
c
i
e
nce.
All rights re
se
rve
d
.
Co
rresp
ond
i
ng
Autho
r
:
N
oop
ur
A
s
tik
,
Depa
rt
m
e
nt
of
El
ect
roni
c
an
d
Tel
ecom
m
uni
cat
i
on E
n
gi
nee
r
i
n
g
,
Sy
m
b
io
sis In
tern
ation
a
l
Un
i
v
ersity,
Sym
b
i
o
si
s I
n
st
i
t
u
t
e
of
Tec
h
n
o
l
ogy
(SI
T
),
La
val
e
, P
u
ne-
M
a
haras
h
t
r
a
4
1
2
1
1
5
,
In
di
a
Em
a
il: Noop
urAstik
@g
m
a
il.c
o
m
or no
o
p
u
r
.a
st
i
k
@si
t
p
une
.e
du
.i
n
1.
INTRODUCTION
Ev
ol
ut
i
o
n o
f
r
econ
f
i
g
ura
b
l
e
devi
ce
bri
dge
d
t
h
e ga
p
bet
w
een t
h
e t
w
o
e
x
t
r
em
i
t
i
e
s, gen
e
ral
-
p
u
r
p
o
se
pr
ocess
o
r a
nd
speci
al
i
zed AS
IC
whi
l
e
o
ffe
ri
ng se
veral
be
n
e
fits fo
r th
e i
m
p
l
e
m
en
tatio
n
o
f
d
i
g
ital circu
its in
t
h
e va
st
an
d
fa
st
gr
o
w
i
n
g
fi
el
d
of
Sy
st
em
Int
e
grat
i
o
n.
M
ode
rn
Field Progr
a
mmabl
e Gate Arr
a
y
available by l
eading
vendors is a Static RAM base
d
reconfi
g
ura
b
le de
vice and it
therefore
outmatches
Ap
p
licatio
n
S
p
ecific In
teg
r
a
t
ed Circu
i
t
in
term
s o
f
co
st
-
effectiv
en
ess
an
d flex
ib
le
b
i
nd
ing
tim
e o
f
the d
e
v
i
ce fun
c
tio
n [1
].
Although Moore’s law has s
u
ccess
f
ully sus
t
ained and
miniaturization of tran
sistor continue
s since
the comm
encement of
Inte
grated circ
uit (IC) era
,
Field Progr
a
mmabl
e Gate A
rray
ind
u
stry
claim
s
for
i
n
n
ovat
i
o
ns
be
y
o
n
d
t
h
e l
a
w.
In o
r
der t
o
q
u
e
n
ch t
h
e
dem
a
nds o
f
hi
g
h
er
ba
nd
wi
dt
h, capac
i
t
y
and reduct
i
on i
n
powe
r consum
ption, FP
GA ve
ndor
s are looki
ng for alternatives th
at outpace
Moore’s law.
Partial
reco
nfi
g
u
r
at
i
o
n (PR
)
feat
ure
of F
P
G
A
t
u
r
n
s o
u
t
t
o
be
on
e su
ch
state
o
f
th
e art in
t
h
is in
du
stry.
W
i
t
h
th
e
adve
nt of SR
AM based FPGA, rec
o
nf
igura
b
le hardware has gaine
d
prom
inent space bet
w
een the e
x
tre
m
es of
gene
ral purpos
e
process
o
r and s
p
ecialized
ASIC
. SR
AM
cells p
r
o
v
i
d
e
un
li
m
ited
reconfigu
r
ation
an
d
m
u
l
tip
le
m
odul
es ope
ra
t
e
sim
u
l
t
a
neou
sl
y
.
PR
enha
nc
es reco
nfi
g
u
r
at
i
on
by
al
l
o
wi
n
g
o
n
l
y
speci
fi
c
regi
o
n
s
of F
P
GA t
o
b
e
repro
g
rammed
with
n
e
w
fun
c
tion
a
lity s
u
ch
th
at th
e remain
in
g
of th
e d
e
v
i
ce con
tinu
e
s to
ru
n
witho
u
t
an
y
n
eed to
reset.
Dy
nam
i
c Part
ial
reco
nfi
g
u
r
at
i
on (
D
PR
) i
s
p
r
act
i
cabl
e
desi
gn s
o
l
u
t
i
on
use
f
ul
t
o
m
a
ny
sect
ors s
u
ch a
s
aerospace, de
fense, m
obile comm
unicati
on, etc. Apart from the
industri
al applications
it is also utili
zed t
o
i
m
p
l
e
m
en
t v
a
rio
u
s
co
m
p
lex
alg
o
rith
m
s
in
Dig
ital Sig
n
a
l
Processing
as well as Dig
ital Im
ag
e Pro
cessin
g
. In
o
r
d
e
r t
o
an
alyze an
d
co
m
p
reh
e
nd
DPR in th
e field
of Dig
ital Sig
n
a
l
Pro
cessing
, it is illu
strated
h
e
re t
o
i
m
p
l
e
m
en
t FIR filter sin
ce
filters are si
gn
al cond
itio
n
e
rs and
form
a
cru
c
ial
p
a
rt
o
f
si
g
n
al pro
c
essin
g
.
A
lth
oug
h
micr
opr
ocess
o
rs
are th
e trad
itio
nal p
l
atform
for im
p
l
e
m
en
tin
g
DSP app
licatio
n
s
un
til recen
tly
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
089
-48
64
I
J
RES Vo
l. 4
,
N
o
. 3
,
No
v
e
m
b
er
201
5
:
2
01
–
20
8
20
2
available acce
lerated
hardware.
As c
o
st a
n
d tim
e
to
market a
r
e s
o
me of the
primary
assets of FPGA,
designers there
f
ore select the
device for
vari
ety of a
ppl
i
cat
i
ons i
n
cl
u
d
i
n
g si
gnal
p
r
oces
si
n
g
. A
n
d FPG
A
al
on
g
with
DPR is su
itab
l
e fo
r ev
ery app
li
cat
i
on
req
u
i
r
i
n
g
hi
g
h
paral
l
e
l
p
r
oce
s
si
ng
rat
h
e
r
t
h
a
n
re
st
ri
ct
i
ng t
o
cl
oc
k
dri
v
en
pe
rf
orm
a
nce.
Th
is
p
a
p
e
r is org
a
n
i
zed in
t
o
3
sectio
n
s
:
-
1
)
Partial
Reco
nfigu
r
ati
o
n
2) FIR filter d
e
sig
n
and
hardware co-si
m
ulation in
system
generator 3) Result ana
l
ysis of
im
plem
entation of
filter m
odules
using
DPR.
2.
PARTI
A
L RE
CO
NFIG
U
R
A
TIO
N
The c
o
ncept
o
f
pa
rt
i
a
l
reco
nfi
g
u
r
at
i
o
n
ori
g
i
n
at
ed f
r
om
reco
nfi
g
u
r
abl
e
c
o
m
put
i
n
g
w
h
i
c
h
h
a
s bee
n
i
n
exi
s
t
e
nce si
nc
e 19
6
0
w
h
e
n
Geral
d
Est
r
i
n
p
r
op
ose
d
t
h
e t
h
e
o
ry
of
reco
nfi
g
u
r
a
b
l
e
har
d
ware.
Part
i
a
l
reco
nfi
g
u
r
at
i
o
n al
l
o
ws p
o
r
t
i
o
n of a
rray
t
o
chan
ge i
n
st
r
u
ct
i
ons
rat
h
e
r
t
h
an
di
st
ur
bi
n
g
t
h
e
funct
i
oni
ng
of
ent
i
r
e
array.
When this change is implem
ente
d at run- tim
e it is term
ed as dyna
mic. It thus
re
duce
s
the
reloa
d
tim
e
and
i
s
usef
ul
w
h
en
al
l
f
unct
i
o
ns
a
r
e not
re
qu
i
r
ed
si
m
u
l
t
a
neousl
y
wo
r
k
i
n
g on
t
h
e FP
GA
f
a
bri
c
.
2.
1
Appr
o
a
ch an
d
T
o
ol
s
Tod
a
y alm
o
st
all FPGA v
e
ndo
rs prov
id
e sup
port fo
r
p
a
rtial recon
f
i
g
urat
io
n
and
till n
o
w three m
a
in
app
r
oaches
ha
ve
been
f
o
l
l
o
wed
.
Di
ffe
rent
ve
nd
or
s p
r
ov
i
d
e PR
s
u
p
p
o
r
t
i
ng t
o
ol
s,
h
o
w
eve
r
t
h
e
t
o
o
l
s and
t
echni
q
u
es
di
sc
usse
d here
are Xi
l
i
nx base
d u
n
l
e
ss
m
e
nt
i
one
d.
a)
Di
ffe
re
nce bas
e
d PR
- It
i
s
used w
h
en a sm
al
l
change i
s
m
a
de t
o
t
h
e desi
gn l
i
k
e m
odi
fy
i
ng a Lo
o
k
-
U
p
Tabl
e (
L
UT
)
f
unct
i
o
n
o
r
m
e
m
o
ry
cont
ent
.
The
part
i
a
l
bi
t
-
st
ream
cont
ai
ns
onl
y
i
n
f
o
r
m
at
i
on ab
out
t
h
e
di
ffe
re
nces
bet
w
een t
h
e c
u
r
r
e
n
t
desi
gn
st
ruc
t
ure (t
hat
resi
d
e
s i
n
t
h
e
FP
G
A
) a
n
d t
h
e
ne
w co
nt
e
n
t
of
a
n
FPGA. Th
e app
r
op
riate too
l
t
o
ach
i
ev
e it is
co
mman
d
lin
e
to
o
l
Bitg
en
and
FPGA ed
itor.[2
]
b)
M
o
d
u
l
a
r PR
-
The m
e
t
hod w
a
s i
n
t
r
o
d
u
ced t
o
al
l
o
w
desi
g
n
e
rs t
o
w
o
r
k
on
di
ffe
rent
m
o
d
u
l
e
s of t
h
e sa
m
e
project in paral
l
el. Eventually it is
an approa
ch by Xilinx for
partial
reconfi
g
uration with
m
a
ny
m
odules
wo
rki
n
g u
nde
r
a t
op-m
o
d
u
l
e
. M
o
d
u
l
e
s occ
upy
t
h
e
ful
l
h
e
i
ght
o
f
t
h
e
d
e
vi
ce wi
t
h
no
i
n
t
e
r-m
odul
e
s
resources
being s
h
are
d
. Bus
m
acros are
used i
n
order to
facilitate inter m
odule c
o
m
m
unication.
Bus
m
acro i
s
a
d
e
fi
ne
d si
g
n
al
pat
h
t
o
cr
oss
o
v
er
pa
rt
i
a
l
reco
nfi
g
u
r
at
i
o
n
bo
u
nda
ry
.
[
3
]
Sy
nt
he
si
s
and
im
pl
em
ent
a
t
i
o
n t
o
ol
s a
n
d
Xi
l
i
nx
XF
LO
W t
o
ol
are
use
d
.
c)
Early Access
Partial Reco
nfig
uration
(EAPR) - It is sim
i
l
a
r to
M
o
dular PR.
Th
e d
e
si
gn
er
sets
up
a top
l
e
vel
desi
gn
t
h
at
i
n
st
ant
i
a
t
e
s
gl
o
b
al
re
so
urc
e
s, I/
O-
pi
n
s
a
n
d st
at
i
c
a
n
d
pa
rt
i
a
l
reco
nfi
g
ur
abl
e
m
odul
es.
It
uses slice bus
macro rathe
r
than tri-state buffe
r (T
B
U
F). T
B
UF co
nnect
PR
regi
o
n
t
o
a com
m
on bus b
u
t
th
e effectiv
en
ess o
f
TBUFs
was co
m
p
ro
m
i
sed
b
y
th
eir fi
x
e
d
lo
cati
o
n
s
[4
] an
d
p
r
o
v
i
d
e
d
less flex
ib
ility
al
on
g wi
t
h
t
h
e
ri
sk of i
n
t
e
r
f
e
r
ence bet
w
ee
n
recon
f
i
g
ura
b
l
e
m
odul
es, he
nce repl
ace
d b
y
slice-based
bus
m
acros. Lat
t
e
r
com
p
ri
se of 2-L
U
Ts
per
bi
t
si
gnal
crossi
ng
reco
nfi
g
u
r
a
b
l
e
m
odul
es
[
5
]
and
pr
ovi
de
a
fixe
d interface
betwee
n static and rec
o
nfigurable m
odul
es i
n
the
desi
gn. All signals e
x
ce
pt gl
obal si
gna
ls
bet
w
ee
n PR
M
and
st
at
i
c
m
odul
e are
r
out
e
d
t
h
r
o
ug
h
b
u
s m
a
cro
.
Alth
oug
h recen
t
adv
a
n
cem
e
n
t fro
m
Xilinx
in
t
r
odu
ced
Plan
Ah
ead
t
o
o
l
wh
ich
d
o
n
o
t
req
u
i
re
b
u
s
m
acro
in
stan
tiatio
n
an
y lon
g
e
r sin
ce th
ey are h
a
rd
m
a
c
r
o
with
two
slices n
eed
ed
in
t
h
e d
e
si
g
n
. Part
itio
n
pi
ns a
r
e t
h
e i
m
provi
sed
sol
u
t
i
on
o
v
er
b
u
s
m
acro.
It
re
q
u
i
r
es si
ngl
e L
U
T
per
bi
t
si
g
n
al
an
d a
u
t
o
i
n
sert
e
d
at
each RM boundary. It is also called
as proxy
-
LUT. [6] The sam
e
approach
of PlanAhea
d
flow has bee
n
use
d
to
im
p
l
e
m
en
t FIR filter.
2.
2
P
a
rtial Confi
g
ur
ati
o
n Methiods
FPG
A can
be
con
f
i
g
ure
d
usi
ng se
ve
ral
con
f
i
g
urat
i
o
n m
odes and
d
u
ri
n
g
reco
nfi
g
u
r
at
i
o
n Sel
ect
M
a
p
,
JTA
G
or IC
A
P
p
o
rt
i
s
sel
ect
ed depe
n
d
i
n
g o
n
t
h
e
rec
o
nf
iguratio
n b
it file tran
sfer
b
e
ing
extern
al
o
r
i
n
ternal.
a)
SelectMap
m
o
d
e
-
It is a p
a
rallel
m
o
d
e
of ex
tern
al con
f
ig
uratio
n. In
t
h
is m
o
d
e
an
ex
tern
al ho
st is
require
d
, s
u
ch as a
m
i
croprocess
o
r
or m
i
croc
ontrolle
r t
o
lo
ad
b
y
te wid
e
con
f
iguratio
n
d
a
ta in
to
th
e
FPGA
d
e
v
i
ce
fro
m
an
y n
o
n
-
v
o
l
atile m
e
m
o
ry. It is a faster m
o
d
e
of configu
r
ation
an
d
can
b
e
u
s
ed
for
Sp
artan
series
wh
ich
lack in
te
rnal
c
o
nfi
g
u
r
at
i
on
p
o
rt
.
[
7
]
b)
Internal Confi
g
uration Acces
s Port
(ICAP)
- ICAP is a subset ve
rsio
n of the SelectMAP interface tha
t
allows acce
ss
to the
confi
g
uration
re
gisters
of the
FPGA. The
IC
AP
e
n
ables the
self
reconfi
g
uration
featu
r
e o
f
the
FPGA with
p
a
rallel d
a
ta
tran
sf
er
. I
C
AP
i
n
terfac
e
s
are
u
s
ed
only
fo
r pa
rtial
recon
f
i
g
uration
s
and
n
o
t
for
in
itial
co
nfiguratio
n. [8
] Par
tial b
itstream
s
are lo
ad
ed
in
t
o
th
e FPGA
with
t
h
e hel
p
of a
n
IC
AP
,
whi
c
h i
s
us
ual
l
y
co
nt
r
o
l
l
e
d
by
an
em
bed
d
e
d
pr
oces
sor
.
Hence
rec
o
n
f
i
g
urat
i
o
n t
i
m
e
is d
i
rectly propo
rtion
a
l to
to
tal recon
f
i
g
urab
le reg
i
on
.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
RES I
S
SN
:
208
9-4
8
6
4
Dynamic Pa
rtia
l Reco
n
figu
r
ati
o
n
with
FIR Filter
Ap
p
lica
t
io
n
(Noo
pu
r Astik
)
20
3
c)
JTAG m
o
d
e
- It is a si
m
p
le s
e
rial co
nfigu
r
atio
n
m
ode. T
h
e JTAG interfa
ce requires
programm
ing cable
and t
h
e
bi
t
fi
l
e
i
s
dow
nl
oa
d
e
d usi
ng i
M
P
A
C
T
. It
su
p
p
o
r
t
s
har
d
ware
d
e
bu
g
g
i
n
g an
d
can p
r
o
g
ram
SPI
f
l
ash
.
[9
]
3.
FIR FILTER IMPLEME
N
TAION
A filter sep
a
rates a d
e
sired
sig
n
a
l fro
m
an
y u
n
wan
t
ed
d
i
stu
r
b
a
n
ces and
b
a
sic filters are freq
u
e
n
c
y
selectiv
e filters. Th
e
d
e
sign
o
f
FIR filter inclu
d
e
s
d
e
sired
freq
u
e
n
c
y respo
n
s
e and
co
efficien
t calcu
lati
o
n
for
th
e FIR filter. [10
]
Co
efficien
ts o
f
filter are calcu
la
ted
h
e
re with
Hammin
g
wi
n
dow u
s
in
g
FDA too
l
b
o
x
i
n
MatLab
. Filter
sp
ecification
s
fo
r Direct
Form FIR l
o
w p
a
ss (LPF) and
h
i
gh
p
a
ss
filters (HPF) are as fo
llows:-
LPF: -
Sam
p
lin
g
f
r
e
qu
en
cy =22
000H
z
Cu
t-
of
f fr
equ
e
n
c
y =
9
000
H
z
Filter
o
r
d
e
r=
10
HPF:
-Sam
pl
i
ng fre
que
ncy
=
4
80
0
0
Hz
Cu
t-
of
f fr
equ
e
n
c
y =
1
080
0Hz
Filter
o
r
d
e
r=
10
3.
1.
Fi
xe
d P
o
i
n
t F
o
rm
at
Real d
a
ta typ
e
s are no
t sy
n
t
h
e
sizab
le in Verilo
g.
Real
num
b
ers a
r
e t
h
ere
f
ore converted to
fixe
d
poi
nt
form
at
in
o
r
d
e
r to
write RTL Verilog
cod
e
fo
r Di
rect
Fo
rm
FIR filter structu
r
e withou
t usin
g
an
y IP co
res fo
r
dat
a
t
y
pe con
v
e
rsi
o
n. Th
e fi
x
e
d p
o
i
n
t
fo
rm
at
em
pl
oy
ed i
s
Q[
QI]
.
[Q
F]
for
m
at
where QI
i
s
num
ber of i
n
t
e
ge
r
b
its an
d
QF is n
u
m
b
e
r of fractio
n
a
l b
its
[11
]
. Ran
g
e
an
d
reso
l
u
tio
n fo
r sign
ed
integ
e
r is calcu
lated
as
fo
llows:
2
2
2
|
2
(3.1)
Co
eff
i
cien
ts are r
e
pr
esen
ted
i
n
Q1
.7
for
m
at
an
d
r
a
ng
e
f
r
om -
1
to
0.9921
85
w
ith
th
e reso
lu
tion
o
f
0.
00
7
8
1
2
5
w
h
en cal
cul
a
t
e
d u
s
i
ng eq
uat
i
o
n
3.
1. 8
-
bi
t
i
n
put
dat
a
i
s
assu
m
e
d t
o
be i
n
t
h
e f
o
rm
of Q5
.3 a
nd t
h
us
in
rang
e o
f
-1
6
to
1
5
.875
with
th
e reso
l
u
tion
o
f
0.125
.
Mu
ltip
licatio
n
o
f
Q1
.7
and
Q5
.3
form
at resu
lts in
Q6
.10
format th
u
s
1
6
-b
it
ou
tpu
t
is tak
e
n.
3.
2. RT
L
usi
n
g Veri
l
o
g
C
o
d
e
RTL fo
r
Direct
Form
FIR lo
w p
a
ss m
o
du
le an
d
h
i
g
h
p
a
ss m
o
du
le is
g
e
n
e
rated
u
s
i
n
g Xilinx
ISE
1
4
.6
fo
r im
pl
em
entat
i
on o
n
ZYB
O
xc
7z0
1
0
-
1
cl
g4
0
0
. Dat
a
i
n
put
i
s
8-
bi
t
and dat
a
out
p
u
t
i
s
16-
bi
t
.
Ad
di
t
i
onal
out
put
net
‘l
d’
sh
ow
n i
n
fi
gu
re 1
i
s
co
n
n
ect
ed t
o
LED
an
d
i
s
of
f
whe
n
l
o
w p
a
ss i
s
i
m
plem
ent
e
d an
d
ON
i
n
case of
h
i
gh
p
a
ss to
m
a
rk
the
co
rrect work
i
n
g
o
f
filters
d
u
ri
n
g
d
y
n
a
m
i
c swap
o
f
m
o
du
les. Thu
s
t
o
tal IOBs are
27 for each filter m
odule
Figure
1. In-out schem
a
tic of low
pas
s
&
hi
gh pass FIR filter
m
odules
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
089
-48
64
I
J
RES Vo
l. 4
,
N
o
. 3
,
No
v
e
m
b
er
201
5
:
2
01
–
20
8
20
4
Fig
u
re
2
.
RTL
sch
e
m
a
tic o
f
Direct Form
FIR filter
Fi
gu
re
3.
IS
E
1
4
.
6
desi
g
n
s
u
m
m
a
ry
of
b
o
t
h
t
h
e i
n
di
vi
du
al
fi
l
t
e
r m
odul
es (
w
i
t
h
o
u
t
DPR
)
3.3. Filter
Ve
r
f
icati
o
n Using
Sys
t
em Gene
rator
Sy
st
em
Gener
a
t
o
r i
s
a
DS
P
desi
g
n
t
o
ol
f
r
o
m
Xi
li
nx t
h
at
enabl
e
s t
h
e
us
e of
t
h
e M
a
t
h
Wo
r
k
s m
odel
-
base
d Si
m
u
l
i
n
k desi
gn e
nvi
r
onm
ent
for F
P
GA
desi
g
n
. [
1
2]
Sy
st
em
generat
o
r
pr
o
v
i
d
e
s
Xi
l
i
nx bl
ock
s
et
s i
n
Si
m
u
lin
k
to gen
e
rate test
v
ect
o
r
s.
The F
I
R filter
Verilog m
odul
es are ve
rified usin
g Black
Box
from
the Xilinx
bloc
kse
t
. Black Box
bl
oc
k pr
o
v
i
d
es
a way
t
o
i
n
co
rp
orat
e V
H
D
L
or Veri
l
o
g co
de i
n
t
o
t
h
e Si
m
u
li
nk m
odel
.
[13]
Whi
l
e
dr
aggi
n
g
th
e Black
Box in
to
th
e Sim
u
lin
k
m
o
d
e
l, it p
r
o
m
p
t
s to
a
ssig
n
n
ecessary HDL
file to
it. All n
ecessary in
pu
ts
and
o
u
t
p
ut
s a
r
e defi
ned
t
h
ro
ug
h
Gat
e
way
I
n
a
nd
Gat
e
wa
y Ou
t FPG
A
bou
nd
ar
y b
l
o
c
k
s
as show
n
i
n
f
i
g
u
r
e
4
bel
o
w.
B
l
ack B
ox
us
es ISE si
m
u
l
a
tor m
ode an
d b
e
l
o
w m
odel
sh
ow
n i
s
a rep
r
e
s
ent
a
t
i
on f
o
r b
o
t
h
l
o
w pass
and
hi
g
h
pass
whe
r
e res
p
ect
i
v
e Ve
ri
l
o
g fi
l
e
i
s
assi
gne
d t
o
B
l
ack B
o
x
.
Fi
gu
re 4 al
s
o
i
n
cl
udes
har
d
wa
re co
-
sim
u
l
a
t
i
on bl
o
c
k o
f
ZYB
O
t
h
r
o
ug
h JT
AG
do
w
n
l
o
a
d
. D
u
r
i
ng Si
m
u
l
i
nk r
u
n
,
res
u
l
t
s
are com
p
i
l
e
d i
n
hard
ware
and
di
s
p
l
a
y
e
d
back
o
n
Si
m
u
l
i
nk si
nk
res
o
u
r
ce (sc
o
pe)
.
I
n
put
si
gnal
i
s
c
h
i
r
p si
g
n
al
wi
t
h
t
a
r
g
et
f
r
eq
u
e
ncy
10
Hz and in
itial 1
00Hz
with targ
et
ti
m
e
0
.
0
0
0
1
. Cl
o
c
k
p
e
ri
o
d
is 1
/
5
∗
1
0
. Sim
u
latio
n
is
run for
0
.
01
s.
Si
nce si
m
u
l
a
t
i
on
us
es
hi
g
h
fr
eque
nci
e
s al
l
p
a
ram
e
t
e
rs are s
e
t
fo
r
bet
t
e
r
vi
s
u
al
sc
ope
g
r
ap
h.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
RES I
S
SN
:
208
9-4
8
6
4
Dynamic Pa
rtia
l Reco
n
figu
r
ati
o
n
with
FIR Filter
Ap
p
lica
t
io
n
(Noo
pu
r Astik
)
20
5
Fig
u
re
4
.
Desi
g
n
v
e
rification
o
f
FIR
filter
with
ord
e
r
10
u
s
i
n
g Black
B
o
x in
SysGen
Tim
e
dom
ai
n out
put
o
f
sc
op
e i
s
show
n i
n
bel
o
w pl
ot
s
fo
r l
o
w
pass as
wel
l
hi
gh
pass
. Ho
we
ver
out
put
o
f
Sc
o
p
e
1 as
wel
l
as
fr
om
Gat
e
way
O
u
t
1
o
f
hwc
o
si
m
bl
ock i
s
hi
g
h
f
o
r
HPF
an
d
l
o
w
f
o
r
LPF
si
nce i
t
i
s
t
h
e o
u
t
p
ut
gi
ve
n t
o
LE
D at
t
h
e t
i
m
e
of
DPR
im
pl
em
ent
a
t
i
o
n.
Fi
gu
re
5 s
h
ows
chi
r
p si
gnal
i
n
put
a
n
d L
PF a
n
d
HPF
o
u
t
p
ut
s
obs
er
ved
o
n
Sc
ope
bl
ock
.
Fi
gu
re
5.
Sc
op
e o
u
t
p
ut
f
o
r
L
o
w
pass m
o
d
u
l
e
an
d
Hi
g
h
pass
m
odul
e
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
089
-48
64
I
J
RES Vo
l. 4
,
N
o
. 3
,
No
v
e
m
b
er
201
5
:
2
01
–
20
8
20
6
Fi
gu
re
6 gi
ves
t
h
e com
p
act
ou
t
put
o
f
har
d
wa
re co
-si
m
ul
at
i
o
n pe
rf
o
r
m
e
d on Z
Y
B
O
fo
r l
o
w pas
s
an
d
hi
g
h
pa
s
s
m
odules. The
Gateway Out i
s
filtered si
gna
l and
Gateway
Out
1
is
agai
n LED out
put which
is high
when HP
F
is r
u
n
n
i
n
g
and
lo
w
w
h
ile LPF is r
u
n
n
i
n
g
. Belo
w
h
a
rdw
a
r
e
co
-
s
im
u
l
atio
n
resu
lts ar
e
f
ound
sim
i
lar
to
Sim
u
l
i
n
k
sim
u
l
a
t
i
on
o
u
t
put
sh
ow
n
i
n
fi
gu
re 5.
Fi
gu
re
6.
Ha
rd
ware
C
o
si
m
Out
p
ut
f
r
om
Gat
e
way
O
u
t
usi
n
g Z
Y
B
O
3.4.
FIR Filter
Implementati
on
Using Dynamic
P
a
rti
a
l Reconf
i
g
ur
ati
o
n in PlanAhe
a
d T
ool
PlanAhea
d tool from
Xilinx provides acce
s
s
to
pa
rtial rec
o
nfiguration
(PR)
design from
Hardwa
re
Descri
pt
i
o
n
La
ng
ua
ge (
H
DL)
sy
nt
hesi
s.
It
hel
p
s c
r
eat
e full an
d
p
a
rtial co
nfigu
r
ation
b
it files b
y
allo
wi
ng
desi
g
n
er t
o
de
fi
ne rec
o
nfi
g
u
r
abl
e
m
odul
es.
[1
4]
Fi
gu
re
7 i
s
t
h
e bl
ock
di
agram
depi
ct
i
ng rec
o
nfi
g
ura
b
l
e
m
odules (RM)
of FIR
filter.
Fi
gu
re 7.
B
l
oc
k Di
ag
ram
for DPR
of
FIR
fi
l
t
er
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
RES I
S
SN
:
208
9-4
8
6
4
Dynamic Pa
rtia
l Reco
n
figu
r
ati
o
n
with
FIR Filter
Ap
p
lica
t
io
n
(Noo
pu
r Astik
)
20
7
For F
I
R filter t
w
o rec
o
nfigura
b
le m
odules a
r
e creat
ed:
- L
P
F and
HPF
wit
h
a se
pa
rate top m
odule i
n
Veri
l
o
g t
h
at
c
ont
ai
n
s
onl
y
I
O
i
n
st
a
n
t
i
a
t
i
ons,
cl
oc
k
p
r
i
m
it
iv
es and
PRM in
stan
tiatio
n
s
along
with
th
e
necessa
ry
user
const
r
ai
nt
s d
e
fi
ne
d u
nde
r
UC
F fi
l
e
. I
n
bri
e
f
,
Pl
an
Ah
e
a
d fl
o
w
f
o
r
D
P
R
begi
ns wi
t
h
H
D
L
descri
pt
i
o
n
,
de
si
gn c
o
nst
r
ai
nt
s, i
m
pl
em
ent
a
ti
on
of
base
d
e
si
gn a
n
d PR
m
odul
es, c
r
e
a
t
i
ng r
eco
nfi
g
ura
b
l
e
p
a
rtitio
n
s
, floorp
l
an
n
i
n
g
, g
e
neratin
g
b
it file
an
d
fi
n
a
lly d
o
wn
l
o
ad
i
n
g it to th
e FPGA
bo
ard. [14
]
Fi
gu
re 8.
C
o
m
b
i
n
e
d
r
esource usage of FIR filter i
m
plementation using DPR
3.
5. POWE
R AN
ALY
S
IS
Xp
o
w
er
A
n
al
y
s
i
s
t
ool
(
X
P
A
)
i
s
use
d
fo
r t
h
e
anal
y
s
i
s
o
f
p
o
w
er
co
ns
um
ed by
i
n
di
vi
dual
l
o
w
pa
ss a
n
d
h
i
gh
p
a
ss m
o
du
les and
t
o
analyze p
o
wer co
n
s
u
m
p
tio
n
in DPR
p
r
oj
ect
o
f
filters. Tab
l
e 1
is a co
m
p
arison
o
f
d
y
n
a
m
i
c an
d
st
atic p
o
wer estimatio
n
b
y
XPA too
l
for i
n
d
i
v
i
du
al LPF and
HPF filter
d
e
sig
n
as
well com
b
in
ed
d
e
sign
o
f
filters withou
t DPR
an
d with DPR.
Tabl
e 1. Po
wer
A
n
al
y
s
i
s
Supply
Power
Filter D
e
sign
T
o
ta
l (W
)
D
y
nam
i
c
(W)
Q
u
ie
sc
e
n
t (W
)
L
PF only
0.
103
0.
00
0.
103
HPF only
0.
103
0.
00
0.
103
Co
m
b
ined L
P
F
&
HPF without DPR
0.
161
0.
061
0.
100
filter with DPR
(c
onfi
guration
1: LPF)
0.152
0.053
0.100
Filter w
ith DPR
(c
onfi
gurati
on 2:HPF)
0.149
0.049
0.100
4.
RESULT ANALYSIS
FIR filter m
o
d
u
l
es for th
e filter o
r
d
e
r
o
f
1
0
ar
e v
e
rified
with
and
witho
u
t
d
y
n
a
m
i
c p
a
rtial
recon
f
i
g
uration
in
th
e ab
ov
e sectio
n
s
.
In
Tab
l
e 2
wit
h
collated
resou
r
ce u
tilizatio
n
d
a
ta, it is o
b
s
erv
e
d
th
at
t
o
t
a
l
IOB
s
re
q
u
i
r
e
d
t
o
i
m
pl
em
ent
bot
h t
h
e
m
odul
es sim
u
l
t
a
neo
u
sl
y
are 44
(excl
udi
ng
t
h
e com
m
on clock
&
r
e
set sign
als) an
d cer
tain
ly mo
r
e
th
an
1
665
LU
Ts r
e
q
u
i
r
e
d un
d
e
r
D
P
R
pro
j
ect.
Tab
l
e 2
.
Resource u
tilizatio
n
Resource
Low pass filter only
High pass filter onl
y
LPF+
HPF w
ithout DPR
LPF+HP
F using DPR
Slice r
e
gister
s
113
101
188
113
Slice LUT
s
1966
1912
3883
1665
I
O
Bs 27
27
44
27
Th
e efficien
cy
in
case
o
f
DSP app
licatio
n
s
can
be
in
creased
fu
rt
h
e
r
with u
tilizatio
n
of
DSP
b
l
o
c
k
s
whi
c
h
a
r
e not
use
d
at
prese
n
t
.
5.
CO
NCL
USI
O
N
A pr
eci
se st
ud
y
of dy
nam
i
c
part
i
a
l
reco
nfi
g
u
r
at
i
o
n i
s
pre
s
ent
e
d c
ove
ri
n
g
i
t
s
si
gni
fi
can
t
aspect
s. Th
e
d
e
sign
statistics of a sim
p
le FIR f
ilter
app
licatio
n
with
filter o
r
d
e
r
of
10
an
d rem
a
in
in
g sp
ecificatio
n cho
s
en
fo
r t
h
e dem
ons
t
r
at
i
on p
u
r
p
ose
do p
r
ove t
h
at
dy
nam
i
c part
i
a
l
recon
f
i
g
urat
i
on ca
n f
unct
i
o
n as p
o
we
rf
ul
st
at
e of
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
089
-48
64
I
J
RES Vo
l. 4
,
N
o
. 3
,
No
v
e
m
b
er
201
5
:
2
01
–
20
8
20
8
art wh
en
ex
ten
d
e
d
to
h
i
gh
er ord
e
r filters with
h
i
g
h
e
r
sam
p
lin
g
rate
s.
Wh
en
ex
ercised
with
su
itab
l
e
ap
p
lication
s
wh
ere no
t all fun
c
tio
n
a
lities are req
u
i
red
at
a ti
m
e
an
d
su
ch th
at th
ey can
ti
m
e
sh
are reso
urces,
desi
g
n
m
a
y
t
h
en be
o
p
t
i
m
i
zed usi
n
g D
P
R
wi
t
h
pr
o
p
er
k
n
o
w
l
e
d
g
e o
f
rec
o
nfi
g
u
r
at
i
on
o
v
e
rhea
d a
nd
fre
que
ncy
of
swi
t
c
hi
ng
re
qui
red
i
n
t
h
e a
ppl
i
cat
i
o
n. T
h
e
rec
o
n
f
i
g
ur
ation
can
furth
e
r be ex
tend
ed
to
self recon
f
iguratio
n
by
usi
n
g
IC
AP
cont
rol
l
e
r
or
u
s
i
ng a
n
ext
e
rna
l
pro
cesso
r.
Ho
weve
r i
n
gen
e
r
a
l
sense, sel
ect
i
on
of F
P
G
A
,
ASI
C
o
r
GPP is p
u
rely b
a
sed
o
n
ap
p
lication
and
is lin
k
e
d
to
maj
o
r
p
a
ram
e
t
e
rs lik
e co
sts, to
o
l
av
ailab
ility an
d
per
f
o
r
m
a
nce.
REFERE
NC
ES
[1]
Andr´
e
DeHon, “Reconfigurab
le Architectures
for General-Purpose Computing”, r
e
search
at
the Artif
icia
l
Intelligen
ce Laboratory of
the M
a
ssa
chusetts Institute
of Techno
lo
gy
,
1996
[2]
Emi Ato, Differ
e
nce B
a
sed
Par
tia
l Re
configura
tio
n,
X
ilin
x In
c.
X
A
P
290
[3]
Partial
Re
config
uration
,
Dev
e
lop
m
ent S
y
st
em
Re
ferenc
e Guid
e,
X
ilinx
Inc
.
[4]
Patrick
L., Bran
don B., Jeff
M.,
“Enhanced Ar
chitectures, Design Met
hodologies And Cad To
ols For D
y
namic
Reconfigur
ation
Of Xilinx FPGAs”,
IEEE
, 2006
[5]
Dirk Koch,Jim Torresen and C
h
ristian Beckhof
f, “Zero L
ogic
Overhead Integr
ation of
Partially
Reconfigur
able
Module.” University
of Oslo
[6]
Partial
Re
config
uration
User Gui
d
e,
Xilinx Inc. U
G
702,
2010
[7]
M
i
ke P
eatt
i
e
,
“Using a Micropr
ocessor to Configure Xilinx FP
GAs
via S
l
ave
S
e
rial or S
e
lec
t
M
A
P
M
ode,”
Xilinx
Inc. XA
PP502
[8]
“Virtex Series C
onfigurati
on Arc
h
ite
cture
Us
er G
u
ide,
”
Xi
linx
Inc
.
XA
PP151
[9]
“7 series FPGAs
Confi
guration” user
guide,
Xilin
x
Inc.UG470,
20
13
[10]
Steven W. Smith, Digital Signal
Processing-
A practical gu
ide for
Engin
eers and S
c
ien
tists
[11]
Oberstar Erick
L.,” Fixed
Point Repres
entation
&
Fraction
a
l Math
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[12]
“Sy
s
tem Gen
e
rator for DSP,” G
e
tting started
guid
e
,
Xilinx
Inc.UG639
[13]
S
y
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a
tor for DSP,” Us
er guid
e
,
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x I
n
c.UG640,
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[14]
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config
uration
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ead Design
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x In
c. UG743,
2012
Evaluation Warning : The document was created with Spire.PDF for Python.