Intern
ati
o
n
a
l
Journ
a
l of
Re
con
f
igur
able
and Embe
dded
Sys
t
ems
(I
JRES)
V
o
l. 3,
N
o
.
2
,
Ju
ly 20
14
, pp
. 54
~61
I
S
SN
: 208
9-4
8
6
4
54
Jo
urn
a
l
h
o
me
pa
ge
: h
ttp
://iaesjo
u
r
na
l.com/
o
n
lin
e/ind
e
x.ph
p
/
IJRES
Desi
gn and Implement
a
ti
on of Ad
ap
tive FIR filter using Systolic
Architecture
Rav
i
H
Ba
ilma
re, S.J
.
Honale,
Prav
in V King
e
Department o
f
Electronics
&
Tel
ecom
m
unication
Engin
eering
,
G
.
H.Ra
isoni Co
llege of
Engin
eerin
g,
Amravati, Maharashtra, India
Article Info
A
B
STRAC
T
Article histo
r
y:
Received Feb 20, 2014
Rev
i
sed
May
5, 201
4
Accepte
d
J
u
n 3, 2014
The tr
emendous growth of computer and
Internet techno
log
y
wan
t
s a data
to
be process with a high speed and in a powerful manner. In such complex
environm
ent, the convent
ional
m
e
thods of perfor
m
ing m
u
ltiplicat
ions are no
t
suitable to obtain the perfect solution.
To obtain perfect
solution parallel
computing is us
e in
contr
a
dictio
n.
Th
e DLM
S
a
d
aptiv
e a
l
gorith
m
m
i
nim
i
zes
approximately
the mean square error
b
y
re
cur
s
ivel
y
al
tering t
h
e weight
vector
at e
ach s
a
m
p
ling ins
t
an
c
e
. In
order to o
b
tain minimum mean square
error and updated value of weig
ht vector
ef
fectively
,
s
y
s
t
olic ar
chitectur
e is
us
ed. S
y
s
t
o
lic
ar
chit
ectur
e is
an
arrangem
e
nt
of
proces
s
o
r where
data f
l
ows
s
y
nchronously
across
array
element.
This
p
r
oject demonstrates
an effectiv
e
design for adaptive filter using
S
y
st
oli
c
arch
ite
c
t
ure for DLM
S
algorithm
,
s
y
nthesized and
simulated on Xilinx ISE Pr
oject
navigator tool in
ver
y
high
speed integr
ated
circuit hardw
a
r
e
description language
(VHDL) and Field
Programmable Gate Array
s
(F
PGAs).
Here, by
combining th
e concep
t of
pipelin
ing and
parallel pro
c
essing in to th
e s
y
stolic arch
itecture
the
com
puting s
p
eed
incr
eas
es
.
Keyword:
DLMS al
g
o
rithm
FPGA
Systo
lic Arch
itectu
r
e
VH
DL
Xilin
x
ISE
Copyright ©
201
4 Institut
e
o
f
Ad
vanced
Engin
eer
ing and S
c
i
e
nce.
All rights re
se
rve
d
.
Co
rresp
ond
i
ng
Autho
r
:
Rav
i
H Bail
m
a
re,
Depa
rt
m
e
nt
of
El
ect
roni
cs
&
Tel
ecom
m
uni
cat
i
on E
n
gi
nee
r
i
n
g
.
Em
a
il: rb
ail
m
a
r
e@g
m
ail.co
m
1.
INTRODUCTION
Ad
ap
tiv
e
d
i
g
ital filters are m
o
stl
y
u
s
ed
i
n
v
a
riou
s si
g
n
al-p
ro
cessi
n
g
ap
p
lication
s
su
ch
as,
n
o
i
se
can
cellatio
n
,
ech
o
can
cellatio
n, syste
m
id
e
n
tificatio
n
a
n
d
chan
nel
equal
i
zat
i
on. M
o
st
of t
h
ese a
ppl
i
c
at
i
ons
requ
ire real
-time ad
ap
tiv
e fi
lterin
g
to
im
p
l
e
m
en
t th
e in
ten
d
e
d
fun
c
tio
n
a
lities with
h
i
g
h
d
e
sire
qu
ality. Fo
r
su
ch
app
lication
s
th
e Ad
ap
tive d
i
g
ital filters
are th
eref
o
r
e realized
th
rou
g
h
d
e
d
i
cated
VLSI system
s. A
m
o
n
g
s
t
th
e ex
isting
Ad
ap
tiv
e d
i
g
ital filters least
mean
sq
u
a
re
(LMS)-b
a
sed
fi
n
ite i
m
p
u
l
se resp
on
se
(FIR) ad
ap
tive
filter is th
e m
o
st p
o
p
u
l
ar du
e
to
its si
m
p
licit
y an
d
sa
tisfact
o
r
y co
nv
erg
e
nce p
e
rfor
m
a
n
ce. Ho
wev
e
r, the d
e
lay
in
av
ailab
ility o
f
t
h
e
feedb
a
ck
erro
r
fo
r
up
datin
g
th
e wei
g
h
t
s acco
r
d
i
ng
t
o
th
e LMS al
go
rith
m
d
o
e
s not favo
rs
i
t
s
pi
pel
i
n
e i
m
pl
em
ent
a
t
i
on u
nde
r
hi
g
h
sam
p
l
i
ng
rat
e
co
n
d
i
t
i
on. F
o
r t
h
at
pu
r
pose t
h
e
de
l
a
y
e
d LM
S (
D
LM
S)
alg
o
rith
m
fo
r
pip
e
lin
e im
p
l
e
m
en
tatio
n
of LM
S.
1.1. Sys
t
olic
Architecture
In com
puter architecture,
a sy
st
ol
i
c
arc
h
i
t
ect
ure
i
s
a
pi
pel
i
n
ed
net
w
or
k
of
Pro
cessi
n
g
El
e
m
ent
s
(PEs
)
called cells. It
is a specialized form
of arra
nge
m
e
nt,
wh
ich
p
e
rform
s
p
a
rallel co
m
p
u
tin
g, wh
ere cells com
p
u
t
e
t
h
e dat
a
whi
c
h i
s
com
i
ng from
l
e
ft
si
de
and t
o
p o
f
PE
as i
nput
an
d
st
ore t
h
em
i
ndepen
d
e
n
t
l
y
. Sy
st
ol
i
c
architecture
re
prese
n
t a
net
w
ork
of
a
proce
ssing elem
ent (PEs
) that
rh
y
t
hm
i
cal
l
y
co
m
put
e
an
d
pass
dat
a
th
ro
ugh
th
e ste
m
, th
e PEs reg
u
l
arly p
u
m
p
d
a
ta in
an
ou
t su
ch
th
at regu
lar flow o
f
d
a
ta is
main
tain
ed
, as a
resul
t
sy
st
ol
i
c
array
feat
ure
m
odul
ari
t
y
and re
g
u
l
a
ri
t
y
w
h
i
c
h a
r
e i
m
por
t
a
nt
pr
o
p
ert
y
f
o
r
VLS
I
desi
g
n
. T
h
e
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
089
-48
64
IJR
E
S V
o
l
.
3, No
. 2,
J
u
l
y
20
1
4
:
5
4
– 61
55
sy
st
ol
i
c
array
m
a
y
be use as
a cop
r
ocess
o
r
i
n
com
b
i
n
at
i
o
n
of
ho
st
com
put
er
pass t
h
ro
u
gh
PEs a
nd t
h
e fi
nal
resu
lt is
return
to
ho
st co
m
p
u
t
er (Figu
r
e 1).
In
ord
e
r to
achiev
e th
e h
i
gh
sp
eed
an
d
low
p
o
wer in
DSP
ap
p
lication
s
, parallel array
mu
ltip
liers are
wi
del
y
use
d
.
I
n
D
SP a
ppl
i
c
a
t
i
ons, i
f
desi
gn
usi
n
g si
m
p
l
e
m
u
lt
i
p
l
i
e
r and
adde
r m
e
t
hod
i
t
requi
re l
a
rge
no
o
f
m
u
l
tip
lier an
d
ad
d
e
r and
m
o
st o
f
th
e
po
wer is con
s
u
m
ed
b
y
th
e m
u
ltip
liers.
Hen
ce, l
o
w
p
o
wer m
u
lti
p
liers
m
u
st
be desi
g
n
e
d i
n
o
r
der t
o
r
e
duce
t
h
e
p
o
w
e
r
di
ssi
pat
i
o
n.
Fi
gu
re
1.
B
a
si
c Pri
n
ci
pl
e of systolic
syste
m
1
.
2
.
LM
S (
L
eas
t
M
e
an
Sq
uare)
A
l
go
rit
h
m
Th
e LMS ad
ap
tiv
e algorithm
is
m
o
stly u
s
e to
m
i
n
i
m
i
z
e
approxim
a
t
ely the m
ean-square
error
by
recursiv
ely
u
p
d
a
tin
g th
e wei
g
h
t
v
ect
o
r
at each
sam
p
lin
g
in
stan
ce.
An adap
tiv
e
FIR
d
i
g
i
tal filter driv
en b
y
t
h
e
LM
S al
g
o
ri
t
h
m
can be de
scr
i
bed a
s
Fi
gu
re
2.
Fig
u
re
2
.
Ad
aptiv
e d
i
g
ital FIR
filter driv
en
by LMS algo
rit
h
m
Whe
r
e
d(
n
) a
n
d
y(n
)de
n
ot
e t
h
e desi
r
e
d
si
g
n
a
l
and
out
put
signal res
p
ective
l
y.
The step-size
µ
is
u
s
ed
fo
r al
t
e
ri
ng
of t
h
e wei
g
ht
vect
or
, an
d e(
n) i
s
t
h
e feed
ba
c
k
error. In the a
b
ove equa
tion
s
, t
h
e tap
-
weigh
t
v
ector
w(n
)
an
d
th
e tap
-
i
n
pu
t
v
ector
x(n)
are define
d as
.
Whe
r
e
N
is the len
g
t
h
of an FIR
d
i
g
ital filter and
[
●
]
t
de
not
es
t
h
e t
r
a
n
spo
s
e o
p
e
r
at
o
r
. The
bl
ock
d
i
agram
o
f
th
e LMS ad
ap
tive FIR d
i
g
ital filter is as sh
own
in
Fig
u
re 1.2
wh
ere th
e symb
o
l
■
d
e
no
tes th
e un
it
d
e
lay ele
m
en
t. In
th
is u
tilize th
e alg
e
bra fo
r th
e d
e
sign
of a systo
lic-array i
m
p
l
e
m
en
tati
o
n
for ad
ap
tiv
e filters
base
d o
n
t
h
e L
M
S al
go
ri
t
h
m
.
Ho
we
ver
,
si
nc
e t
h
e LM
S al
gorithm
contains a feedbac
k
loop, the
delays create
d
in
th
e d
e
co
m
p
o
s
itio
n and
ret
i
m
i
n
g
pro
c
ess
p
r
oh
ib
it th
e exact i
m
p
l
e
m
en
t
a
tio
n
o
f
th
e alg
o
rith
m
.
Th
e
d
e
si
gn
p
r
o
c
ed
ure leads to
a systo
lic
array wh
ich
im
p
l
e
m
en
ts
a s
p
ecial case of the so-called
delayed LMS (DLMS)
algorithm
.
The error
e(n)
u
s
ed
in
th
is algo
ri
th
m
is av
ailab
l
e o
n
l
y after the p
r
o
cessing
delay o
f
th
e systo
lic
array an
d thu
s
th
e
u
p
d
a
te
o
f
th
e co
efficien
ts
is p
e
rfo
rm
ed
with
th
is
d
e
lay.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
RES I
S
SN
:
208
8-8
7
0
8
Design
an
d Imp
l
emen
ta
tion
of Ada
p
tive FIR
filter u
s
in
g
S
y
sto
lic Arch
itectu
r
e
(Ra
v
i H
Bailma
r
e)
56
1.
3 DL
M
S
(
D
e
l
ayed
L
e
as
t M
e
an Squ
are
)
A
l
gori
t
hm
LMS algorithm
uses the fe
edbac
k
-error co
rresp
ond
ing
to
th
e
n
th
iterat
i
o
n
for u
p
d
a
ti
n
g
th
e filter
weigh
t
s to
b
e
used
for co
m
p
u
t
in
g
th
e filter ou
tpu
t
fo
r t
h
e (
n
+1)
Th
iteration
.
Th
e
DLMS al
g
o
rith
m
is si
mi
lar to
th
e LMS al
g
o
rith
m
,
ex
cep
t t
h
at in
case
o
f
DLMS al
g
o
rith
m
,
th
e weight in
crem
en
t term
s
to
b
e
u
s
ed in
the
cu
rren
t iteration
are esti
m
a
te
d
fro
m
th
e erro
r v
a
l
u
e and
in
pu
t sam
p
les c
o
rresp
ond
ing
to
a p
a
st iterati
o
n
. Th
e
st
ruct
u
r
e
of
co
nve
nt
i
o
nal
D
L
M
S
al
go
ri
t
h
m
i
s
as sh
o
w
n i
n
Fi
gu
re
3.
The
wei
g
ht
u
p
d
at
e
equat
i
o
n al
go
ri
t
h
m
is
gi
ve
n by
,
W
(n+
1
)
=W
(
n
) +µe
(
n-
D
)
X(
n-D
)
Here
D
is th
e
nu
m
b
er of iterat
i
o
n
s
b
y
wh
ich
t
h
e ad
ap
tation
i
s
d
e
layed.
Fig
u
r
e
3
.
conven
tio
n
a
l D
L
M
S
algo
r
ith
m
2.
RELATED WORK
On
e
o
f
th
e imp
o
rtan
t im
p
l
e
m
en
tatio
n
b
y
R. D. Po
ltm
an
n
con
v
e
rts th
e d
e
layed
LMS alg
o
rith
m
in
to
th
e LMS algo
r
i
th
m
.
Th
ey sh
ow
n
t
h
e
w
a
y how
th
e
d
e
laye
d
LMS (DLMS)
algorithm
can be c
o
nverte
d i
n
to t
h
e
st
anda
rd
LM
S
al
go
ri
t
h
m
at
on
l
y
sl
i
ght
l
y
i
n
cr
eased i
n
c
o
m
put
at
i
onal
e
x
pen
s
e [
10]
.
A
n
o
t
h
e
r
im
p
o
r
tan
t
im
p
l
e
m
en
tatio
n
b
y
Lan-D
a
V
a
n AND
W
u
-Sh
i
u
n
g
Fen
g
,
A
n
Ef
f
i
cien
t Systo
lic
Arch
itectu
r
e
fo
r t
h
e DLMS Ad
ap
tiv
e
Filter and
Its
Ap
p
lication
s
.
In th
is p
a
p
e
r an
efficien
t systo
lic
arch
itecture for ad
ap
tiv
e
fin
i
te i
m
p
u
l
se resp
on
se (FIR), d
i
g
ital filter d
r
iv
en
b
y
d
e
lay least
m
ean
sq
uare
(DLMS
)
base
d on a new t
r
ee-systolic processing el
ement (PE
)
and an optim
i
zed
tree-level rul
e
was
p
r
esen
ted. Th
ey sh
ows co
m
p
reh
e
nsiv
e
co
m
p
arison
resu
lts fo
r d
i
fferen
t N-
t
a
p
ad
ap
tiv
e FIR filter stru
ct
ure and
v
e
rify t
h
e
resu
l
t
o
f
systo
lic-array arch
itectu
r
e fo
r ad
ap
tiv
e
eq
u
a
lization
and
system
id
en
tificatio
n
app
licatio
n
s
[1
1]
.
An
ot
he
r i
m
por
t
a
nt
i
m
pl
em
ent
a
t
i
on
by
Fá
bi
o
Fabi
a
n
Dai
t
x
,
Va
gne
r
S. R
o
sa, E
dua
r
d
o
C
o
st
a,
Paul
o
Flores
, Sérgi
o
Bam
p
i
,
VHDL Gen
e
ration
of Op
tim
ized
FIR Filters
,
In
t
h
i
s
pape
r a nea
r
opt
i
m
u
m
al
gori
t
h
m
was u
s
ed
fo
r co
n
s
tan
t
co
efficien
t FIR filters. Th
is al
g
o
rithm u
s
es g
e
n
e
ral co
efficien
t rep
r
esen
tatio
n
for th
e
o
p
tim
al sh
aring
of
p
a
rtial produ
cts in
M
u
ltip
le Co
n
s
tan
t
s Mu
ltip
licatio
n
s
(MCM).Th
e im
p
l
e
m
en
tatio
n
so
ft
ware was d
e
v
e
l
o
p
e
d
in
C
lan
g
u
ag
e
an
d
p
r
od
u
c
es VHDL
co
d
e
fo
r
th
e op
ti
m
i
z
e
d
FIR filter
fro
m
a
co
efficien
t sp
ecificatio
n
file. Th
e
d
e
v
e
l
o
p
e
d
so
ftware
was app
lied
to
sev
e
ral FIR filters and
co
m
p
ared
t
o
Matlab’s Filter Design &
Ana
l
ysis (FDA). T
h
e FDA tool
box includes a fe
ature to ge
nera
te optim
ized VHDL
code
f
r
om
t
h
e
gene
rat
e
d
coe
f
fi
ci
ent
s
an
d
wa
s use
d
t
o
c
o
m
p
are t
o
t
h
e
de
vel
ope
d
so
ft
wa
re
[1
2]
.
An
ot
he
r i
m
por
t
a
nt
im
pl
em
ent
a
t
i
on by
P
r
a
m
od K. M
e
he
r an
d M
e
gha
M
a
hesh
wa
ri
,
A Hi
gh
-S
pee
d
FIR Ad
ap
tiv
e
Filter
Arch
itectu
r
e u
s
ing
a Mo
d
i
fied
Dela
yed
LMS
Algo
rith
m
.
In th
is p
a
p
e
r, a m
o
dified
delayed least means square
(DLMS) a
d
apt
i
ve algorith
m
t
o
ach
iev
e
lower ad
ap
tatio
n-delay an
d
p
r
o
posed
an
efficien
t p
i
p
e
li
n
e
d
arch
itectu
r
e fo
r im
p
l
e
m
e
n
tatio
n
of ad
ap
tiv
e filter. They sh
o
w
n
th
at th
e p
r
o
p
o
s
ed
DLMS
ad
ap
tiv
e
filter can
b
e
im
p
l
e
m
en
ted
b
y
a p
i
p
e
lin
ed
in
ner-prod
u
c
t co
m
p
u
t
atio
n
u
n
it wh
ich
i
s
u
s
e fo
r calcu
l
a
tio
n
of
feed
bac
k
m
ean-s
q
u
are e
r
r
o
r a
n
d a pi
pel
i
n
ed
u
pdat
e
d v
a
l
u
e o
f
wei
ght
s uni
t
,
w
h
i
c
h c
onsi
s
t
i
n
g
of
N
paral
l
e
l
m
u
l
tip
lies acc
u
m
u
l
ato
r
s for filter o
r
d
e
r N.
Th
ey sug
g
e
sted
a
m
o
d
i
fied
DLMS ad
ap
tive alg
o
r
ith
m
to
ach
ieve
less ad
ap
tation-d
e
lay co
m
p
ared
with
th
e con
v
e
n
tion
a
l DLMS alg
o
r
ith
m
,
an
d
sho
w
n
th
at
th
e p
r
o
p
o
s
ed
DLMS
al
go
ri
t
h
m
can
be i
m
pl
em
ent
e
d e
ffi
ci
ent
l
y
b
y
a pi
pel
i
n
ed
i
nne
r
pr
o
duct
com
put
at
i
on
u
n
i
t
an
d
par
a
l
l
e
l
an
d
p
i
p
e
lin
ed
weigh
t
upd
ate un
it
u
s
ing
carry-sav
e redu
ction
s
.
Sub
s
tan
tial redu
ctio
n of ad
ap
t
a
tio
n
-
d
e
lay ADP and
EPS
ov
er t
h
e e
x
i
s
t
i
n
g
st
r
u
ct
ur
es has
bee
n
ac
hi
eve
d
by
t
h
e
p
r
o
p
o
sed
de
si
g
n
[
13]
.
An
ot
he
r
i
m
por
t
a
nt
i
m
pl
em
ent
a
t
i
on by
K.R
.
S
a
nt
ha
an
d V V
a
i
d
ehi
,
A
Ne
w Pi
pel
i
n
ed
Arc
h
i
t
ect
ure
f
o
r
t
h
e DLM
S
Al
go
ri
t
h
m
.
Thi
s
pape
r p
r
ese
n
t
s
a desi
gn o
f
a systolic array architecture for the 1-dim
e
nsional
Fin
ite I
m
p
u
l
se Resp
on
se ad
ap
tiv
e filter. The d
e
sig
n
is
b
a
sed
on
th
e Delayed
Least Mea
n
Squ
a
res alg
o
rith
m
(DLM
S
)
. T
h
e
per
f
o
r
m
a
nce o
f
t
h
e
pr
op
ose
d
desi
g
n
i
s
anal
yzed in term
s
of s
p
ee
d up, a
d
aptation delay and
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
089
-48
64
IJR
E
S V
o
l
.
3, No
. 2,
J
u
l
y
20
1
4
:
5
4
– 61
57
th
ro
ugh
pu
t. The
d
i
fferen
t N-t
a
p
1
-
D
ad
ap
tive filters are analyzed
and
it is
shown th
at t
h
e propo
sed sche
m
e
is
su
perior i
n
term
s o
f
ad
ap
tatio
n d
e
lay,
sp
eed
an
d thr
oug
hpu
t withou
t th
e
n
eed fo
r add
itio
n
a
l
h
a
rdware
[14
]
.
A
n
o
t
h
e
r
i
m
p
o
r
t
an
t i
m
p
l
e
m
e
n
tatio
n
b
y
Lan
-
D
a
V
a
n
and
W
u
-
S
h
i
ung Fen
g
,
Effici
en
t Systo
lic
Arch
itectu
r
es
fo
r l-D and
2-D DLMS
Ad
ap
ti
v
e
Di
g
ital. Two
efficien
t
N
th
t
a
p 1
-
D an
d
wi
nd
o
w
si
ze
N
x
N
2-D
systo
lic ad
ap
tiv
e d
i
g
ital filters u
tilizin
g
th
e tree-systo
l
i
c
PE
has bee
n
p
r
esent
e
d i
n
t
h
i
s
pa
per.
Un
de
r
consideri
n
g maxim
u
m
num
ber
of t
a
p-c
o
nne
ct
i
ons
of
t
h
e
fe
edbac
k
e
r
r
o
r si
gnal
,
t
h
e
p
r
act
i
cal
rul
e
t
o
deci
de t
h
e
o
p
tim
ized
tree
lev
e
l with
ou
t sacrificing
th
e systo
lic ch
ar
act
eri
s
t
i
c
s i
s
pro
v
i
ded.
At
l
a
st
, t
h
ey
veri
fy
I-
D and
2-
D e
fficient syst
olic arc
h
itectures
v
i
a
app
lic
a
t
i
o
n
s
of
ad
ap
tiv
e e
q
u
a
lizer a
n
d image restoration [15].
An
ot
he
r
i
m
por
t
a
nt
im
pl
em
ent
a
t
i
on by
S.
R
a
m
a
nat
h
an an
d V. Vi
sva
n
at
ha
n, A Sy
st
ol
i
c
Arc
h
i
t
ect
ure
for LMS Ad
ap
tiv
e Filterin
g
with
Min
i
m
a
l
Ad
ap
tatio
n
Delay.
This paper pres
ente
d a systolic architecture
with
m
i
n
i
m
u
m
ad
ap
tatio
n d
e
lay an
d in
pu
t/ou
t
pu
t laten
c
y, wh
ich is respo
n
s
i
b
le for im
p
r
ov
ing
th
e
con
v
e
r
ge
nce
b
e
havi
or t
o
nea
r
t
h
at
of t
h
e
ori
g
i
n
al
LM
S al
g
o
ri
t
h
m
.
The ar
chi
t
ect
ure i
s
sy
nt
hesi
ze
d by
u
s
i
ng a
num
ber
of
fu
n
c
t
i
on p
r
ese
r
vi
n
g
t
r
a
n
sf
orm
a
t
i
ons
o
n
t
h
e si
g
n
al
fl
o
w
gra
p
h
rep
r
ese
n
t
a
t
i
o
n
of t
h
e del
a
y
e
d LM
S
alg
o
rith
m
.
W
i
t
h
th
e u
s
e of carry-sav
e arithmetic, th
e sy
sto
lic fo
ld
ed
p
i
pelin
ed
arch
itectu
r
e can
sup
port v
e
ry
hi
g
h
sam
p
l
i
ng
rat
e
s rem
ovi
n
g
o
n
l
y
by
t
h
e
de
l
a
y
of a
f
u
l
l
ad
der
[
16]
.
An
ot
he
r i
m
por
t
a
nt
im
pl
em
entat
i
on
by
B
a
san
t
K. M
o
ha
nt
y
,
Prom
od
K.M
e
her
,
D
e
layed Blo
c
k
LMS
Algo
rith
m
an
d co
n
c
urren
t
arch
itectu
r
e
for
h
i
gh
-sp
e
ed
im
p
l
em
en
tatio
n
of Ad
ap
tiv
e FIR Filter. In
t
h
i
s
p
a
p
e
r,
pr
o
pose
d
t
h
e
DB
LM
S al
g
o
ri
t
h
m
whi
c
h t
a
k
e
s a bl
oc
k o
f
L
i
n
p
u
t
sam
p
l
e
s and y
i
el
ds a
bl
oc
k o
f
L
out
put
s i
n
every trai
ning
cycle. The sim
u
lation
r
e
su
lt sh
ow
s t
h
at th
e
p
e
rf
or
m
a
n
ce of
DB
LMS algorith
m
is eq
u
i
v
a
len
t
to
that of t
h
e DL
MS algorithm
.
Howe
ver
,
the
DBLM
S alg
o
ri
thm
offers
L
fold
h
i
gh
er p
a
rallelis
m
co
m
p
ared
wi
t
h
th
e DLMS algo
rith
m
.
W
e
h
a
v
e
u
tilized
the in
h
e
ren
t
p
a
ral
l
elis
m
in
DBLMS alg
o
rith
m to
d
e
riv
e
a
hig
h
l
y
co
n
c
urren
t
systo
lic-lik
e arch
i
t
ectu
r
e for h
i
gh
-sp
e
ed
i
m
p
l
emen
tatio
n
o
f
ad
ap
tiv
e FIR
filter. Th
e prop
o
s
ed
structure ca
n
provide
L
tim
es
h
i
gh
er th
rou
ghp
u
t
co
m
p
ared
with
th
e ex
isti
n
g
p
i
p
e
lin
ed
st
ru
ct
u
r
es [1
7
]
.
An
ot
he
r i
m
por
t
a
nt
im
pl
em
ent
a
t
i
on by
Hes
a
m
Ari
y
ado
o
st
, Y
o
u
s
ef S
.
K
a
vi
an,
Ka
ri
m
Ansa
ri
-
A
s,
Perform
a
n
ce Ev
alu
a
tion
o
f
LMS and
DLM
S
Di
g
ital Ad
ap
tiv
e FIR Filters
b
y
Realizati
o
n on
FPGA.
In
t
h
is
pape
r im
pl
em
ent
t
h
e ada
p
t
i
v
e di
gi
t
a
l
Least
M
ean Sq
uare
(
L
M
S
) an
d del
a
y
e
d-LM
S (
D
L
M
S) Fi
ni
t
e
Im
pul
se
Resp
on
se (FIR)
filters o
n
Field
Prog
ram
m
ab
le
Gate
Array (FPGA)
ch
ip
s
fo
r typ
i
cal n
o
i
se can
c
ellatio
n
appl
i
cat
i
o
ns and c
o
m
p
are t
h
e be
havi
or o
f
LM
S and
D
L
M
S
adapt
i
v
e
al
gori
t
h
m
s
i
n
t
e
r
m
s of chi
p
area
u
tilizatio
n
an
d th
e filter criti
cal p
a
th
ti
m
e
o
r
filter fre
qu
en
cy. Th
e d
i
rect FIR arch
itectu
r
e is con
s
id
ered
for
f
ilter
d
e
si
g
n
i
n
g
and
th
e VHDL h
a
r
d
w
a
r
e
d
e
scr
i
p
tion
languag
e
is
u
s
ed
for alg
o
r
ith
m
m
o
d
e
llin
g
.
D
e
m
o
n
s
tr
ate
th
at th
e
DLMS alg
o
rith
m
wh
ich
h
a
s a
p
i
p
e
li
n
e
arch
itect
u
r
e is faster t
h
an
LMS algo
rithm
wh
ile it u
s
es m
o
re
chip a
r
ea
due t
o
using e
x
tra
registers.
3.
PROP
OSE
D
WORK
Propose
d
work use Systolic Array arc
h
itectur
e,
wh
ich co
nsist o
f
no
of
processi
ng elem
ent
connected to one a
not
her,
bas
i
c processi
ng e
l
e
m
ent of
syst
olic architecture
is
as s
h
o
w
n i
n
Fi
gu
re
4.
Fi
gu
re
4.
PE
o
f
sy
st
ol
i
c
A
r
chi
t
ect
ure
Whe
r
e
A, B
a
nd C
a
r
e t
h
e
m
a
t
r
i
ces wi
t
h
or
der m
x k
,
k
x
n, a
nd m
x
n res
p
ect
i
v
el
y
.
Each P
E
o
f
systo
lic array
co
nsist m
u
lt
ip
lier and
accu
m
u
l
ato
r
un
it wh
i
c
h
p
e
rform
m
u
ltip
licatio
n
o
f
ele
m
en
ts co
m
e
s as an
in
pu
t to
th
e PE an
d
accu
m
u
l
ates to
th
e co
rrespo
n
d
i
ng
resu
lt in
to
th
e sa
m
e
PE an
d
th
en
elem
en
ts
will b
e
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
RES I
S
SN
:
208
8-8
7
0
8
Design
an
d Imp
l
emen
ta
tion
of Ada
p
tive FIR
filter u
s
in
g
S
y
sto
lic Arch
itectu
r
e
(Ra
v
i H
Bailma
r
e)
58
p
a
ssed
to
n
e
igh
bor PE in
t
h
e
systo
lic array.
First ele
m
en
ts
α
i,j
in
row i of m
a
trix
A are
in
j
ected
first into
PE
as pi
pel
i
n
e
wi
t
h
t
h
e se
que
nce
α
i,k
o
f
and
the in
pu
t ti
m
e
to
th
e ele
m
en
t o
f
α
i+1
,
j
is
o
n
e ti
m
e
u
n
it later
th
an
α
i,j
.
Similarly
ele
m
en
ts b
i
,j
in
co
lu
m
n
j
o
f
matrix
B are in
j
ected
first in
to PE as p
i
p
e
lin
e with
th
e seq
u
e
n
ce o
f
b
k
,j and
the in
pu
t tim
e to
t
h
e elem
en
t o
f
th
e seq
u
e
n
c
e o
f
bk
,j
+1
is on
e tim
e u
n
it l
a
ter th
an
of
bk
,j
. The
arch
itecture o
f
PE in
th
is app
r
o
ach
is shown
in
Fi
g
u
re 4
which
p
e
rform
s
th
e Mu
ltip
licatio
n
and
Accu
m
u
latio
n
on
dat
a
.
Fig
u
re 5
sh
ows th
e d
i
rect form
s o
f
DLMS FIR filte
rs, wh
ich
m
a
in
ly
co
nsists o
f
sh
i
f
t reg
i
sters,
ad
d
e
rs an
d
m
u
ltip
liers. Th
e sig
n
a
l sam
p
les are m
u
ltip
lied
b
y
filter co
effi
cien
ts and
are
g
a
th
ered
t
o
g
e
t
h
er
i
n
th
e add
e
r
b
l
o
c
k
.
Th
e DLM
S
FIR filter con
s
i
s
ts o
f
so
m
e
registers in
feedb
a
ck
lin
e.
Figure
5
. Th
e
d
i
rect form
o
f
DLMS ad
ap
tive FIR
filter
Figure
6 s
h
ows
efficie
n
tly realizab
le
systo
lic arch
itecture o
f
th
e
DLMS
ad
ap
tiv
e d
i
g
ital
fil
t
er. Wh
ere
uni
t
del
a
y
i
s
d
e
not
e
d
by
z
-1
,
we in
sert a
u
n
i
t d
e
lay ele
m
en
t in
th
e
feedb
a
ck
p
a
th
so
as to
m
a
in
tain
th
e
lo
west
critical period. And obse
rve t
h
at whe
n
p
is equal to zero, this architecture
can be re
duced to a fully pipelined
architecture.
On t
h
e ot
her
hand, i
f
p
i
s
great
er t
h
a
n
z
e
ro
, t
h
i
s
arc
h
i
t
ect
ure pe
rf
o
r
m
s
bet
t
e
r conver
g
e
n
ce
with
ou
t sacrifi
c
in
g
systo
lic featu
r
es.
Figure
6. Systolic architecture
with ca
scade
d
systolic-tree PEs
Arch
itectu
r
e fo
r realizatio
n
o
f
Ad
ap
tiv
e FIR
filte
r u
s
i
n
g DLMS algorith
m
co
n
s
ist o
f
n
o
. of PE’s
co
nn
ected
to
on
e ano
t
h
e
r. No
o
f
PE’s is eq
u
a
l to
n
o
of
Tap
s
of an
FIR filter, Prop
o
s
e
work
d
e
sign
for 4
-
Tap
Fir filter t
h
erefo
r
e
no
PE’s equ
a
l to
4
.
If Taps of filter
i
n
crease th
en
n
o
of
PE’s i
n
crease.
Th
is arch
itecture is
use f
o
r
o
b
t
a
i
n
i
ng m
ean sq
uar
e
err
o
r
.
Thi
s
M
S
E i
s
agai
n
us
e fo
r o
b
t
a
i
n
i
n
g
up
dat
e
d
val
u
e
of
wei
g
ht
coe
f
fi
ci
ent
an
d
the p
r
o
c
edu
r
e is con
tinu
o
u
s
un
til we g
e
t
m
i
n
i
m
u
m
MS
E. Shows d
i
fferen
t sim
u
latio
n
resu
lt and
find
ou
t
t
i
m
e
requi
re
f
o
r
obt
ai
ni
ng
m
i
ni
m
u
m
M
S
E for
di
f
f
ere
n
t
i
n
p
u
t
,
a
n
d
de
si
red
out
put
c
o
m
b
i
n
at
i
on.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
089
-48
64
IJR
E
S V
o
l
.
3, No
. 2,
J
u
l
y
20
1
4
:
5
4
– 61
59
4.
SIMULATION RESULT
Th
e sim
u
latio
n
resu
lts for
realizatio
n
of ad
aptiv
e
d
i
g
ital FIR
filters u
s
i
n
g DLMS algo
rithm
o
n
FPGA
ch
ip
are
presen
ted
and
t
h
e
perfo
r
m
a
n
ces of DLMS algo
rit
h
m
is o
b
t
ain
i
n
term
s o
f
ch
i
p
area
u
tilizati
o
n and
ti
m
e
r
e
q
u
i
r
e
fo
r
m
i
n
i
m
u
m
MSE.
Th
e d
i
g
ital ad
ap
tiv
e f
i
lter
s w
e
r
e
m
o
d
e
led
b
y
VHDL and
im
p
l
e
m
en
ted
on
Spa
r
t
a
n
3 FP
G
A
fam
i
l
y
. The Xi
l
i
nx a
nd m
o
del
s
i
m
soft
war
e
was
used
f
o
r
sy
nt
hesi
ze an
d
sim
u
l
a
t
i
on o
f
VH
DL
code
s.
In
itially th
e filt
er weigh
t
s w0
, w1
,
w2, and
w3
are assu
m
e
d
to
b
e
zero
and
ob
tain
th
e upd
ated
v
a
lu
e
fo
r
red
u
cin
g
t
h
e err
o
r
usin
g t
h
e in
p
u
ts info
rmatio
n
and
er
ro
r v
a
lu
es. In
t
h
ese sim
u
latio
n
resu
lts t
h
e learn
i
n
g
fact
or
was ass
u
m
e
d t
o
be µ=0.
5. Si
m
u
l
a
t
i
o
n res
u
l
t
for
d
i
fferen
t in
pu
t and
d
e
sired
ou
tpu
t
co
m
b
in
atio
n are as
sho
w
n i
n
t
h
e
F
i
gu
res
7-
1
0
.
Fi
gu
re
7.
Si
m
u
l
a
t
i
on res
u
l
t
f
o
r Xi
n=
8 a
n
d
Di
n=1
8
Fi
gu
re
8.
Si
m
u
l
a
t
i
on res
u
l
t
f
o
r Xi
n=
20
an
d
Di
n=
40
Fi
gu
re
9.
Si
m
u
l
a
t
i
on res
u
l
t
f
o
r Xi
n=
30
an
d
Di
n=
60
Fi
gu
re 1
0
. Si
m
u
l
a
t
i
on res
u
l
t
f
o
r
Xi
n=4
0
a
n
d Di
n=
90
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
RES I
S
SN
:
208
8-8
7
0
8
Design
an
d Imp
l
emen
ta
tion
of Ada
p
tive FIR
filter u
s
in
g
S
y
sto
lic Arch
itectu
r
e
(Ra
v
i H
Bailma
r
e)
60
5.
CO
NCL
USI
O
N
Systo
lic arch
itectu
r
e is use
fo
r d
e
si
gn
o
f
mu
ltip
lier, m
a
tri
x
m
u
ltip
licatio
n
& m
a
n
y
DSP app
lication
i.e. RLS algo
ri
th
m
,
LMS algo
rith
m
an
d FIR filter.
Low
ad
ap
tion d
e
lay
arch
itectu
r
e
fo
r im
p
l
e
m
en
tatio
n
o
f
DLMS ad
ap
tive filter is ach
iev
e
d
b
y
u
s
i
n
g
an
efficien
t im
p
l
e
m
en
tatio
n
o
f
systo
lic arch
itectu
r
e. By inv
o
l
vi
ng
t
h
e
co
ncept
of pi
pel
i
n
i
n
g
a
nd paral
l
e
l
pr
oces
si
ng
i
n
t
o
sy
st
ol
i
c
archi
t
ect
ure hi
g
h
l
y
red
u
ce adapt
i
o
n del
a
y
,
chi
p
area an
d p
o
w
e
r
co
ns
um
pt
i
on.
Desi
g
n
o
b
se
rv
es di
ffe
re
nt
ad
apt
i
on
del
a
y
chi
p
ar
ea an
d p
o
we
r co
ns
um
pt
i
on f
o
r
di
ffe
re
nt
i
n
p
u
t
and
desi
re
d o
u
t
p
ut
com
b
i
n
at
i
on. T
h
e
pr
o
p
o
s
ed st
r
u
ct
u
r
e s
i
gni
fi
ca
nt
l
y
i
nvol
ves l
e
ss ad
apt
i
o
n
delay chip are
a
and powe
r consum
ption as com
p
ared
to
th
e ex
istin
g
stru
ctures.
Sys
t
olic architecture
of
DLM
S
al
go
ri
t
h
m
i
s
im
pl
em
en
t
e
d an
d
o
b
t
a
i
n
im
pro
v
ed
res
u
l
t
i
n
com
p
are
d
wi
t
h
c
o
n
v
e
n
t
i
o
nal
m
e
t
hod.
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Evaluation Warning : The document was created with Spire.PDF for Python.