Intern
ati
o
n
a
l
Journ
a
l of
Re
con
f
igur
able
and Embe
dded
Sys
t
ems
(I
JRES)
V
o
l.
4, N
o
. 3
,
N
o
v
e
m
b
er
2
015
, pp
. 17
3
~
17
7
I
S
SN
: 208
9-4
8
6
4
1
73
Jo
urn
a
l
h
o
me
pa
ge
: h
ttp
://iaesjo
u
r
na
l.com/
o
n
lin
e/ind
e
x.ph
p
/
IJRES
A New-High Sp
eed-Low Power-
Carry S
e
lect Ad
der Usin
g
Modified GDI Technique
M
.
A
n
it
ha
,
J
.
Prin
cy
Jo
ice, Rexlin Sheeba.
I
Dept of
ECE, Sath
y
a
bama Univ
er
si
ty
,
Che
nna
i,
Ta
milnadu, India
Article Info
A
B
STRAC
T
Article histo
r
y:
Received
Ja
n 15, 2015
Rev
i
sed
Jun
9
,
2
015
Accepte
d
J
u
l 12, 2015
Adders are of fundamental imp
o
rtance in
a wid
e
variety
of digital s
y
stems.
This paper pres
ents a novel bit block
structure which computes propagate
signals as carr
y
strength. Power
consum
ption is one of the most significan
t
parameters of carr
y
sele
ct adder.The proposed
method aims on
GDI (
G
ate
Diffusion Input) Techniqu
e. Modified
GDI is
a novel techniq
u
e for low
power digital
circu
its design
further
to red
u
ce th
e swing
degrad
atio
n
problem. This techniqu
es allow
s
re
duction in power
consumption, car
r
y
propagation delay
and transistor count
of th
e carr
y
select
adder.This
techn
i
que can b
e
used to reduce the number o
f
transistors co
mpared to
conventional CS
LA and made
compar
ison with known conventional add
e
rs
which giv
e
s that the usage of
car
r
y
-str
ength sign
als allows high-sp
eed
adders
to be real
is
ed at
lower cos
t
as
well
as consuming
lower power than previous
des
i
gns
. Henc
e,
this
paper
we ar
e conc
entr
ating
on the
area
lev
e
l &we
are
reducing
the po
wer using modif
i
ed GDI log
i
c.
Keyword:
Fast Adder
Lo
w po
wer
de
si
gn
M
odi
fi
e
d
GD
I
Copyright ©
201
5 Institut
e
o
f
Ad
vanced
Engin
eer
ing and S
c
i
e
nce.
All rights re
se
rve
d
.
Co
rresp
ond
i
ng
Autho
r
:
M. An
ith
a,
PG
Student,
Dept of ECE
,
Sa
thyaba
m
a
Un
iversity, Ch
en
n
a
i
,
Tam
iln
ad
u
.
Em
a
il: an
ita_
v
e
l
m
u
r
ug
an@yah
oo
.co
m
1.
INTRODUCTION
Lo
w p
o
we
r ar
i
t
h
m
e
t
i
c
ci
rcui
t
s
have b
eco
m
e
very
im
port
a
nt
i
n
VL
SI
i
ndu
st
ry
.D
ue
t
o
t
h
e ra
pi
d
gr
owt
h
of
p
o
rt
abl
e
el
ect
ro
ni
c
com
pone
nt
.
A
dde
r ci
rc
ui
t
i
s
t
h
e m
a
i
n
bui
l
d
i
n
g
bl
ock
i
n
DS
P p
r
oce
sso
r.
A
dde
r i
s
t
h
e m
a
i
n
com
pone
nt
of
ari
t
h
m
e
t
i
c
uni
t
.
A
C
o
m
p
l
e
x DS
P
sy
st
em
i
nvol
ve
s seve
ral
a
d
der
s
. T
h
e
Desi
gne
rs a
r
e
forced wit
h
m
o
re co
n
s
t
r
ain
t
s are
h
i
gh
sp
eed
,
h
i
gh
th
ro
ugh
pu
t, sm
all silico
n
area an
d low po
wer con
s
u
m
p
tion.
M
a
ny
desi
g
n
st
y
l
es of ad
de
rs
exi
s
t
.
Al
t
h
o
u
g
h
,
R
i
ppl
e ca
rry
adde
rs a
r
e t
h
e
sm
al
l
i
n
desi
gn
st
ruct
u
r
e
but
i
t
s
very
slowe
r
. M
o
st recently, carry
-skip a
d
ders
[1, 2,
3] are
use
d
popularly due
to their
pe
rformance of hi
gh spee
d
and sm
al
l
si
ze. Gene
ral
l
y
, i
n
an N
-
bi
t
car
ry
-
s
ki
p a
dde
r di
vi
ded i
n
t
o
M
-
bi
t
num
ber o
f
bl
ock
s
[
1
, 4]
, a l
o
n
g
-
ran
g
e o
f
carry
si
gnal
st
art
s
at
a bl
ock B
i
, w
h
i
c
h ri
ppl
i
n
g t
h
r
o
ug
h som
e
bi
t
s
i
n
t
h
at
bl
ock, t
h
e
n
i
t
ski
p
s
som
e
bl
oc
ks, a
n
d e
n
ds
wi
t
h
a
bl
oc
k B
j
. C
a
r
r
y
-
l
o
ok
-a
head
an
d
carry
-sel
ect
a
d
ders
are
ve
ry
f
a
st
but
far
l
a
r
g
er an
d
co
nsu
m
e
m
u
ch
m
o
re po
wer th
an
ripp
le o
r
carry-sk
i
p
add
e
rs. Two
o
f
th
e fastest k
n
o
w
n ad
d
ition
circuits are
t
h
e Ly
nc
h-
Sw
art
z
l
a
nde
r’s
[
5
]
and
Ka
nt
ab
u
t
ra’s
[6]
hy
bri
d
car
ry
-l
o
o
k
-a
head
ad
de
rs. T
h
ey
are
base
d
on
t
h
e
usa
g
e o
f
a ca
rr
y
t
r
ee t
h
at
p
r
o
duce
s
car
ri
es i
n
t
o
a
p
p
r
op
ri
at
e bi
t
p
o
si
t
i
ons
w
i
t
hout
bac
k
p
r
o
p
agat
i
o
n.
I
n
or
der
t
o
obt
ai
n
t
h
e
val
i
d s
u
m
bi
t
s
as s
o
o
n
a
s
pos
si
bl
e, i
n
b
o
t
h
Ly
n
c
h-
Swa
r
t
z
l
a
nd
er’s
an
d
Ka
nt
abut
ra’s
ad
der
s
t
h
e s
u
m
bits are
com
p
uted
by m
eans of ca
rry-select
blocks
,
whic
h
are
ab
le to
p
e
rfo
r
m th
eir o
p
e
ratio
n
s
in
p
a
rallel with
the car
ry
-tree
.
Thi
s
pape
r
pre
s
ent
s
t
w
o
ne
w
fam
i
li
es of a
d
ders
,
bot
h
bas
e
d
on
a
new
b
i
t
carry
Sel
ect
& adi
a
bat
i
c
structure that
com
putes propagate si
g
n
a
ls
called
“carry-streng
t
h
”
in
a
ripp
le fash
i
o
n. Th
e first fam
ily o
f
ad
d
e
rs is a famil
y
o
f
n
e
w carry-select adders th
at are
sign
ifican
tly faster th
an
trad
itio
nal carry-select ad
d
e
rs
while
not m
u
ch larger. T
h
e s
econd
fam
i
ly of adde
rs is
a
famil
y
o
f
h
ybrid lo
ok
ah
ead add
e
rs similar to
th
o
s
e
p
r
esen
ted
in
[5, 6
]
b
u
t
sign
ifi
can
tly s
m
al
ler an
d
still co
m
p
arab
le in
sp
eed. Carry Se
lect Add
e
r (CSLA) is o
n
e
of t
h
e fa
st
est
adde
r use
d
i
n
m
a
ny
dat
a
-
p
r
o
ce
ssi
ng
pr
ocess
o
rs t
o
pe
rf
orm
fast
ari
t
h
m
e
t
i
c
f
unct
i
o
ns
.Thi
s
wo
rk
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
089
-48
64
I
J
RES Vo
l. 4
,
N
o
. 3
,
No
v
e
m
b
er
201
5
:
1
73
–
17
7
17
4
uses a
sim
p
le and efficient
gate-lev
el m
o
d
i
ficatio
n
t
o
si
gn
ifican
tly re
duce the a
r
ea a
n
d
powe
r
of t
h
e
CSLA.
Th
ere is scop
e to
redu
ce th
e
p
o
wer con
s
u
m
p
tio
n in
t
h
e reg
u
l
ar CSLA.
Mu
ltip
le p
a
irs
o
f
Ri
p
p
l
e Cary Ad
ders
(RCA) a
r
e use
d
in CSLA structure.
He
nce, the CSLA is not area efficien
t.
W
e
proposed a m
odified CSL
A
d
e
sign
.
Th
is
p
a
p
e
r
presen
ts n
e
w fam
ilies o
f
ad
d
e
rs, bo
th
b
a
sed
o
n
a n
e
w
b
it carry Select & ad
iab
a
tic stru
ctu
r
e
that com
putes propagate signals called
“carry
-st
r
en
gt
h” i
n
a ri
ppl
e fas
h
i
o
n. The f
a
m
i
l
y
of a
dde
rs i
s
a fam
i
ly
o
f
n
e
w carry-select ad
d
e
rs that are
sig
n
i
fican
tly faster th
an
trad
ition
a
l carry-select add
e
rs
wh
ile no
t
m
u
ch
larg
er.
Mu
ltip
le p
a
irs
o
f
Ripp
le Cary
Ad
d
e
rs (RCA) are
u
s
ed in C
S
LA stru
cture. Hen
ce, th
e CSLA is
n
o
t
area
efficient. CSLA gene
rat
e
s
m
a
ny
carriers and
partial sum
.
Many arch
itecture is t
e
sted under
di
ffe
rent
co
nd
itio
ns wh
ich
po
ssib
l
y resu
lt in
v
a
rian
t perfo
r
m
a
n
ce even
i
m
p
l
e
m
en
ted
with
th
e same alg
o
r
ith
m
,
C
S
LA is
pr
o
v
ed t
o
have
go
o
d
per
f
o
r
m
a
nce
usi
n
g i
n
h
i
gh s
p
ee
d a
dde
r. C
L
A i
s
pr
ov
ed t
o
ha
ve
go
o
d
per
f
o
r
m
a
nce whi
c
h
i
s
usi
ng i
n
hi
g
h
spee
d ad
de
r.
Si
nce, t
h
i
s
arc
h
i
t
ect
ure are
u
s
ed com
m
onl
y
i
n
m
a
ny
paper
s
. STC
L
A
– S
p
an
ni
n
g
Tree Usi
n
g C
L
A uses a t
r
e
e
of 4
-
bi
t
M
a
nche
st
er C
a
rry
-Lo
o
k
ahea
d c
h
ai
ns (M
C
C
)
t
o
gene
rat
e
carry
fo
r
d
i
fferen
t
b
it po
sitio
n. RCLCSA
–
Recursive CLA/CSA
Ad
d
e
r
u
s
es th
e
sam
e
co
n
cep
tio
n
as STCLA
ex
cept
t
h
e
l
e
n
g
t
h
s o
f
i
t
s
carry
chai
n
s
are vari
a
n
t
,
not
fi
xe
d. HS
AC
–
Hi
gh Sp
eed Ad
der
Usi
n
g
C
L
A uses
Li
ng
’s
ad
d
e
r
wh
ich
solv
es th
e transitio
n of carry
p
r
op
ag
ation
d
e
lay.
Fi
gu
re
1.
C
o
nv
ent
i
onal
C
a
rry
Sel
ect
Ad
de
r
u
s
i
n
g
R
C
A
Ad
de
rs
usi
n
g
di
ffe
re
nt
i
m
plem
ent
a
t
i
on t
h
a
t
i
s
t
h
e m
o
st
cri
t
i
cal
one
. F
o
r
exam
pl
e, S
T
C
L
A
a
n
d
R
C
L
C
S
A
uses
dy
nam
i
c C
M
OS
desi
gn
w
h
i
l
e
HS
AC
us
i
ng
st
at
i
c
C
M
OS.
A
ge
ne
ra
l
archi
t
ect
u
r
e
i
s
t
o
i
m
p
l
e
m
en
t fo
r
measu
r
ing
th
is th
ree d
i
fferen
t
alg
o
r
ith
m
that
m
eans we can use both
dyna
mic CMOS as
well
as th
e static C
M
OS to
im
p
l
e
m
en
t th
ese alg
o
r
ith
m
s
for c
o
m
p
ari
s
on.
A N
e
w arc
h
i
t
ect
ur
e im
prove
d f
r
o
m
t
h
e
ori
g
i
n
al
pape
r.
Ori
g
i
n
al
i
m
pl
em
ent
a
t
i
on whi
c
h
i
s
base
d o
n
t
h
e Adi
a
bat
i
c
l
ogi
c,
but
i
t
t
a
k
e
s
m
o
re
ad
va
nt
age o
n
th
e ch
ar
acter
ist
i
cs o
f
CMO
S
cir
c
u
it. G
e
n
e
r
a
lly, w
e
d
o
n
’
t u
s
e “b
ar
” (
i
nv
er
t
e
d
)
as w
e
condu
ct ev
er
y equ
a
tio
n.
Bu
t in
reality, “b
ar” is added
at the
o
u
t
p
u
t
of log
i
c
circu
its au
to
matically. So
, t
h
ey use th
is
sp
ecial
characte
r
istic to
reduce t
h
e c
a
rry
prop
agat
i
o
n
t
i
m
e
. Gat
e
Di
ff
usi
o
n
I
n
p
u
t
(G
DI
) i
s
an
a
dva
nce
d
t
e
c
hni
que
f
o
r
l
o
w
p
o
we
r
di
g
i
t
a
l
desi
gn.
T
h
i
s
t
echni
q
u
e c
a
n
be u
s
ed t
o
red
u
ce
po
we
r
con
s
um
pt
i
on,
del
a
y
an
d n
u
m
b
er
o
f
t
r
ansi
st
o
r
s co
m
p
ared t
o
C
o
nve
nt
i
o
nal
C
M
OS
desi
g
n
. T
h
e st
anda
rd C
M
OS a
nd se
ve
ra
l
di
ffe
r
ent
t
ech
ni
q
u
es
fo
r circ
uit desi
gn
is c
o
m
p
ared
with M
o
dified
G
D
I tec
h
niq
u
e
.
2.
PROPOSE
D
GDI
B
A
SE
D CSLA
ARCHITECTURE
B
a
si
c GDI C
e
l
l
:
The B
a
si
c GDI
desi
g
n
[
5
]
i
s
as sh
ow
n i
n
Fi
gu
re 2
,
w
h
i
c
h can
be i
m
pl
em
ent
e
d usi
n
g
twin
-well CMOS or SOI tech
no
log
y
. Basic GDI cell con
s
ists
of 3 i
n
put
t
e
rm
i
n
al
s G, P
and
N. Fr
om
Fi
gu
re
2
,
source a
n
d
drai
n c
o
nnected wi
th P a
n
d
N terminal.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
RES
I
S
SN
:
208
8-8
7
0
8
A New-Hi
g
h
Sp
eed-Lo
w
Po
w
e
r-Ca
rry Sel
ect
Add
e
r Using
Mod
ified
GDI Techn
i
qu
e
(M. An
itha
)
17
5
Figure
2. Ba
sic GD
I Cell
Po
wer
di
ssi
p
a
t
i
on
bec
o
m
e
s m
o
st
im
port
a
nt
l
i
m
i
t
a
t
i
o
n i
n
hi
gh
p
e
rf
orm
a
nce a
ppl
i
cat
i
o
ns.
Opt
i
m
i
zati
ons of B
a
si
c l
ogi
c
gat
e
s are f
u
nd
am
ent
a
l
const
r
ai
nt
i
n
or
der t
o
get
bet
t
e
r t
h
e
per
f
o
r
m
a
nce of [6]
a
vari
et
y
of l
o
w
po
wer a
n
d hi
gh
per
f
o
rm
ance devi
ces.
A
hi
gh
-s
peed l
ogi
c
st
y
l
e for l
o
w
po
wer el
ect
r
o
ni
cs
desi
g
n
i
s
kn
o
w
n
as
Gat
e
Di
ff
usi
o
n
In
p
u
t
(
G
D
I
)
wi
t
h
l
e
ss
p
o
we
r
di
ssi
pa
t
i
on, l
e
ss
desi
g
n
a
r
ea, a
n
d e
f
f
i
ci
ent
im
pl
em
ent
a
t
i
o
n o
f
hu
ge
vari
et
y
of l
o
gi
c f
u
nct
i
o
n
s
. B
u
t
t
h
i
s
basi
c
Gat
e
Di
ff
usi
on
I
n
p
u
t
(
G
D
I) l
ogi
c
st
y
l
e
suf
f
ers
fr
om
som
e
of t
h
e p
r
act
i
cal
l
i
m
i
t
a
t
i
ons l
i
k
e swi
n
g de
gr
adat
i
o
n,
fab
r
i
cat
i
on c
o
m
p
l
e
xi
t
y
and bul
k
con
n
ect
i
o
ns. T
h
ese l
i
m
i
t
a
ti
on
s can be
o
v
erc
o
m
e
s by
m
odi
fi
ed gat
e
di
ff
usi
on i
n
p
u
t
(M
od
-G
DI
) l
o
gi
c [
5
]
.
Thi
s
m
odi
fi
ed gat
e
di
ff
usi
on i
n
p
u
t
(M
od
-
G
D
I) l
ogi
c al
l
o
ws re
duct
i
o
n i
n
po
wer c
ons
um
pt
i
o
n
,
del
a
y
an
d area o
f
d
i
g
ital circu
its. Figu
re 3 shows th
at th
e b
a
sic Mo
d-GDI cell
.
Fi
gu
re 2.
M
o
di
fi
ed G
D
I
C
e
l
l
C
o
m
p
ari
s
on
m
a
de
wi
t
h
basi
c
GD
I cel
l
,
M
odi
fi
ed
G
D
I cel
l
c
ont
ai
n
s
,
i.
a lo
w vo
ltag
e
term
in
al (SP) co
nfigu
r
ed
t
o
b
e
con
n
ected
t
o
su
pp
ly
v
o
ltag
e
ii.
a h
i
gh
vo
ltag
e
ter
m
in
al (
S
N)
co
nf
igu
r
ed
t
o
be con
n
ected
t
o
g
r
ou
nd
.
Incl
udi
ng term
inals, we can
ens
u
res that the M
o
d
-
GDI cell can
b
e
i
m
p
l
e
m
en
ted
with
all cu
rren
t
C
M
OS t
ech
nol
ogi
es
.I
n M
o
d-
GD
I cel
l
,
t
h
e
b
u
l
k
no
de
of al
l
PM
OS t
r
a
n
si
st
ors a
r
e c
o
n
n
ect
ed t
o
VD
D a
n
d
bul
k
node of all NMOS transistors are
connected to GND.
Mod-GDI cell
uses standa
rd 4
termin
al NMOS and
PM
OS t
r
a
n
si
st
ors a
n
d i
t
pr
ov
i
d
es ease o
f
i
m
pl
em
ent
a
t
i
on i
n
al
l
t
y
pe of st
anda
r
d
C
M
OS
t
echn
o
l
o
gy
. T
a
bl
e 1
rep
r
ese
n
t
s
[
8
]
t
h
e
vari
ous
l
o
gi
c fu
nct
i
o
ns
w
h
i
c
h can
be
i
m
plem
ent
e
d wi
t
h
hel
p
of
M
O
D-
GD
I cel
l
f
o
r
di
ffe
rent
i
n
p
u
t
co
nfi
g
u
r
at
i
on. T
h
i
s
ar
r
a
ngem
e
nt
of
m
odi
fi
ed G
D
I
cel
l
pro
v
i
d
e
s
red
u
ct
i
o
n i
n
b
o
t
h
s
u
b-t
h
res
h
ol
d a
n
d
leakage
power [17] c
o
m
p
ared to static CMOS
gate.
M
o
d
-
G
D
I
i
s
m
o
re s
u
i
t
a
bl
e
w
h
i
l
e
desi
gni
ng
o
f
hi
g
h
spee
d, l
o
w
p
o
w
er ci
rcui
t
s
by
usi
n
g
red
u
ce
d
num
ber
of t
r
an
si
st
ors as
wel
l
as i
m
prove
d s
w
i
n
g
deg
r
adat
i
o
n
an
d
static p
o
wer characteristics.This lo
g
i
c allows sim
p
le t
o
p
-
d
o
wn d
e
sign
b
y
usin
g a sm
all cell lib
rary
[8
].
Mo
d -
GD
I l
o
gi
c pe
rf
orm
a
nce i
s
t
e
st
abl
e
, so t
h
at
M
o
d
-
G
D
I l
ogi
c and l
ogi
c ci
r
c
ui
t
desi
g
n
m
e
t
h
o
d
s i
s
h
ope
f
u
l
fo
r
desi
g
n
a
l
o
w
p
o
we
r a
n
d
hi
g
h
per
f
o
r
m
a
nce appl
i
cat
i
o
ns.
Tabl
e
1.
Vari
o
u
s
l
o
gi
c f
unct
i
o
n
i
m
pl
em
ent
a
t
i
on
wi
t
h
M
o
d-
GD
I l
o
gi
c
N
Ss
P Sp G
D
FUNCTI
ONS
0 0
1
1 A
A’
I
NVE
R
T
E
R
A A
0
A
B
AB
AND
1 0
A
D
B
A+B
OR
A’
0
A
1
B
A’B+AB’
XOR
A 0
A’
1
B
AB+A’B
XNOR
0
0 B B
A
A’B
FUNCTI
ON
1
B 0
1
1
A
A’+B
FUNCTI
ON
2
C 0
B
1
A
A’B+AC
MUX
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
089
-48
64
I
J
RES Vo
l. 4
,
N
o
. 3
,
No
v
e
m
b
er
201
5
:
1
73
–
17
7
17
6
In
Fi
g
u
re
1,
L
ogi
c
gat
e
s ca
n
be re
pl
ace
d b
y
M
od-
G
D
I c
e
l
l
t
o
achi
e
ve
hi
g
h
s
p
eed e
f
f
i
ci
ent
carry
sel
ect
adde
r wi
t
h
l
o
w
p
o
w
er c
ons
um
pt
i
on a
n
d l
e
ss l
a
y
o
u
t
ar
ea.Each l
ogi
c
gat
e
s i
n
c
o
n
v
e
n
t
i
onal
C
S
LA
base
d
on RC
A is re
placed by m
odifi
ed GDI l
ogic c
e
lls.Perfo
rm
ance com
p
arison
also done
with
conve
n
tional C
S
L
A
and
M
o
d-
G
D
I
base
d C
S
L
A
.
3.
POWER
& D
ELAY C
A
LC
ULATIO
N
A.
(1
) P
o
wer
co
ns
um
pt
i
on o
b
t
a
i
n
ed
fo
r C
o
n
v
e
n
t
i
onal
16
bi
t
C
S
LA
base
d R
C
A a
r
chi
t
ect
u
r
e:
i.
V
d
d
Gn
d fr
o
m
ti
m
e
0
to
1e-0
06
ii.
A
v
er
ag
e
p
o
w
e
r con
s
u
m
ed
-
>
8
.
8
517
21
e-
002 w
a
tts
iii.
Max
p
o
w
e
r 6.64
332
3
e
-0
01
at
ti
m
e
4
.
0
293
8e-0
07
iv
.
M
i
n p
o
w
e
r
1.
4
4
8
5
29e
-
0
0
1
at
t
i
m
e
3.11e
-
0
0
7
(2)
Delay ob
tain
ed fo
r Conv
en
tio
n
a
l
16
b
it
CSLA
b
a
sed
RCA arch
itectu
r
e:
TRAN
_
M
easu
r
e
_D
elay_
1
= 5.289
2
e
-0
08
B.
(
1
)
Pow
e
r
ob
tain
ed
fo
r
Prop
osed
M
o
d-
GDI
b
a
sed
1
6
b
it
C
S
LA
ar
ch
itectur
e
i.
V
d
d
Gn
d fr
o
m
ti
m
e
0
to
1e-0
06
ii.
A
v
er
ag
e
p
o
w
e
r con
s
u
m
ed
-
>
4
.
5
431
97
e-
003 w
a
tts
iii.
Max
p
o
w
e
r 5.68
658
8
e
-0
02
at
ti
m
e
4
.
0
075
6e-0
07
iv
.
M
i
n p
o
w
e
r
9.
3
7
8
4
97e
-
0
0
8
at
t
i
m
e
4.2e-
0
07
(
2
)
D
e
lay ob
tain
ed fo
r Pr
opo
sed
M
o
d-
GD
I based
16
b
it CSLA
ar
ch
itecture
TRAN_
M
easu
r
e_D
e
lay_1
= 4
.
70
00
e-
009
.
4.
PERFORMANCE
ANAL
YSIS T
A
BLE FOR
16
BIT-CARRY SELE
CT
ADDE
R
Table 2. Performance
analysis
table
S.No
Type
Area
Pow
er consu
m
p
t
i
o
n
Delay
1.
E
x
isting
CSL
A
864T
8.
87
m
W
52.
8ns
2.
Pr
oposed
CSL
A
352T
0.
445
m
W
4.
7ns
From
Tabl
e 2,
Perf
orm
a
nce C
o
m
p
ari
s
on m
a
de wi
t
h
t
h
e c
o
n
v
e
n
t
i
onal
1
6
b
i
t
-
C
S
L
A
an
d M
O
D
-
G
D
I
base
d 1
6bi
t
-
C
S
LA.
T
he si
gni
fi
cant
pa
ram
e
ter of l
o
w
po
w
e
r vl
si
desi
g
n
suc
h
as area, p
o
we
r co
ns
um
pt
i
on as
wel
l
as t
h
e
del
a
y
can
be
hi
g
h
l
y
red
u
ce
d
by
u
s
i
n
g
M
o
d-
GD
I
l
ogi
c i
n
C
a
rry
Se
lect Adde
r a
r
chitecture.
5.
CO
NCL
USI
O
N
The
new i
m
pl
em
ent
a
t
i
on i
s
ba
sed
on t
h
e o
r
i
g
i
n
al
archi
t
ect
u
r
e, so i
t
can
be
use
d
i
n
bot
h st
at
i
c
C
M
OS
and
dy
nam
i
c
C
M
OS ci
rcui
t
s
. An
d t
h
ro
u
gh
m
y
prop
ose
d
archi
t
ect
u
r
e, I c
a
n re
duce
po
w
e
r,area c
o
nsum
pt
i
o
n
but
s
acri
f
i
ce s
o
m
e
t
i
m
i
ng (
w
hi
c
h
ca
n
be
negl
ect
e
d
).B
y
t
h
i
s
i
m
pl
em
ent
a
t
i
on,t
h
e
p
r
op
ose
d
M
o
d-
G
D
I
b
a
se
d
1
6
b
it-CSLA
will p
r
ov
e t
h
at is really b
e
tter
th
an
t
h
e
C
o
nven
tio
n
a
l C
S
LA b
a
sed
RC
A.
After refer, I realize
t
h
at
im
provi
n
g
t
h
e per
f
o
r
m
a
nce of a
dde
r i
s
very
di
ffi
cul
t
n
o
w
beca
use o
f
t
h
e t
r
ansi
st
o
r
l
e
vel
.
I
f
t
o
get
hi
g
h
er
perform
a
nce we
m
u
st reduce t
h
e com
p
lex
ity
in
tran
sistor lev
e
l, it can
b
e
a
c
hi
eve
d
by
G
D
I
l
ogi
c.B
u
t
t
h
e
basi
c
GDI log
i
c suffers
fro
m
swin
g
d
e
g
r
ad
ation
prob
lem
an
d
flex
i
b
ility, so
th
at th
e Mod
-
GDI log
i
c can
b
e
prese
n
ted in t
h
is pa
pe
r.
He
nce, t
h
e proposed ca
rry
sele
ct adde
r archit
ecture e
n
s
u
res
that the less
powe
r
con
s
um
pt
i
on a
n
d
re
d
u
ced
n
o
.
o
f
t
r
a
n
si
st
o
r
s
wi
t
h
negl
ect
i
n
g
of
del
a
y
s
.
REFERE
NC
ES
[1]
Basan
t
Ku
m
a
r and
Suj
it Ku
m
a
r Patel, “Area–
delay-powe
r efficient
carry sele
ct adde
r”,
IEEE
Tran
sa
ctio
n on circu
its and
system
s II
, 201
3.
[2]
Kore
n I, “C
ompute
r
arithm
e
tic algorithm
s
”,
Prentice-Hall
, 1
993
.
[3]
Kant
a
but
ra, V
,
“Desi
g
ni
n
g
o
p
t
i
m
u
m
one-l
e
v
el
carry
-
s
ki
p adde
rs”,
IEEE
Trans.
on C
o
mp
., 199
3, Vol.
42
, no
6
,
pp
.7
5
9
-
7
64
.
[4]
C
h
an
P.K
,
Sc
h
l
ag M
.
D
.
F, T
h
om
bors
on C
.
D
,
O
k
l
o
bdzi
j
a V
.
G, “
Dela
y
op
timiza
tion
o
f
carry-skip
ad
d
e
rs
an
d bl
ock
ca
rr
y-l
o
ok-
ahe
a
d
a
dde
rs
”,
Pro
c
. of In
t’l
Sym
p
o
s
iu
m
o
n
C
o
m
p
u
t
er
Arith
m
e
tic, 1
991
,
pp
.
15
4-
16
4.
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I
J
RES
I
S
SN
:
208
8-8
7
0
8
A New-Hi
g
h
Sp
eed-Lo
w
Po
w
e
r-Ca
rry Sel
ect
Add
e
r Using
Mod
ified
GDI Techn
i
qu
e
(M. An
itha
)
17
7
[5]
Nage
ndra
, C., Ir
win, M.J
., O
w
ens
,
R.M, “
A
re
a-ti
m
e
-p
ower trad
eo
ffs
in p
a
rallel ad
d
e
rs”,
IEEE Tr
ans.
CAS
-
II,
4
3
,
(10)
, pp
. 68
9-
702
.
[6]
Pakkiraiah cha
k
ali et al, “
A
Novel l
o
w power an
d a
r
ea
efficient ca
rry
look ahea
d a
dde
r
using
GDI
technique”
,
IJ
ARCET
,
Vo
lume
1
,
I
s
su
e 5
,
Ju
ly
201
2.
[7]
Balakrishna Batta et al, “Energy effi
cie
n
t Full adde
r using GDI technique”,
IJRCCT
, V
o
l
u
m
e
1, Issue
6,
No
vem
b
er 20
1
2
.
[8]
Pooja
Va
rm
a and Racha
n
a
Mancha
nda, “
R
eview
Of
Va
rio
u
s
GD
I Tec
hni
que
s f
o
r L
o
w P
o
wer
Digit
a
l
Circu
its”,
IJ
ET
AE Jour
nal
, V
o
l
u
m
e
4, Iss
u
e 2, Feb
r
uary
20
14
.
[9]
B. Ra
m
k
u
m
ar an
d
H.M.
Kittu
r, “Low-power and
area-effi
cien
t carry select ad
d
e
r”,
I
E
EE Tr
ans
act
i
o
n
on
Very La
rge
Scal
e I
n
t
e
gr
at
i
o
n
Sy
st
ems
, vol. 20
,
no
.
2
,
pp
. 37
1–3
75
, Feb
r
u
a
r
y
20
12
.
[10]
B. Ram
k
u
m
ar, Harish
M
Kittu
r, P. Mah
e
sh
Kann
an
, “ASIC Im
p
l
e
m
en
tat
i
o
n
o
f
Mod
i
fied
Faster Carry
Save Ad
de
r”,
Eu
ro
p
e
an
Jo
u
r
n
a
l
o
f
S
c
ien
tific Resea
r
ch
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450
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16
X
,
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ol. 42 No.
1 (2010), pp. 53-
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[11]
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h
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~zimmi
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