Internati
o
nal
Journal of P
o
wer Elect
roni
cs an
d
Drive
S
y
ste
m
(I
JPE
D
S)
V
o
l.
6, N
o
. 1
,
Mar
c
h
20
15
,
pp
. 16
0
~
16
7
I
S
SN
: 208
8-8
6
9
4
1
60
Jo
urn
a
l
h
o
me
pa
ge
: h
ttp
://iaesjo
u
r
na
l.com/
o
n
lin
e/ind
e
x.ph
p
/
IJPEDS
A Simple Strategy of Controllin
g a Balanced Voltage Capacitor
in Single Phase Five-Level Inverter
L. Heru Pratomo*
,
**
, F. Dana
ng
Wija
ya*,
Eka
Firma
n
sy
ah*
* Depart
em
ent o
f
El
ectr
i
c
a
l
Engi
neering
and
Info
rm
ation T
echno
l
o
g
y
, Gadj
ah M
a
da Univers
i
t
y
** Departement
of Electr
i
cal
Eng
i
neer
ing,
Soegij
a
p
ranat
a
C
a
thol
ic
Universit
y
Article Info
A
B
STRAC
T
Article histo
r
y:
Received Dec 4, 2014
Rev
i
sed
Jan 20, 201
5
Accepte
d
Fe
b 3, 2015
The f
i
ve-level inverter
has b
e
en used
for
many
applications
in renew
a
ble
energ
y
s
y
s
t
ems. Even though
its harmonic dis
t
ortion was low
e
r than
the
conventional two-level inv
e
rter. Th
e fiv
e
-level conv
erter
has so
me
disadvantages such as incr
easing
power
semiconductor,
complex p
u
lse width
modulation control methods, and problem
with
the voltag
e
balan
c
ing of th
e
capacitor
.
Th
is paper aims to propose a
modified five-level inver
t
er
based
o
n
sinusoidal pulse width modulation using
phase shifted carrier
to enhancing
the c
a
pac
itor vo
l
t
age b
a
lan
c
ing
.
This
m
odified fi
ve-lev
el inv
e
rt
er
reduces
th
e
overall cost
and
the complex
i
ty
of
the pulse wid
t
h modulator.
Thus making
the proposed control s
y
stem highl
y
simple. The performance and
its
controll
er wer
e
valid
ated b
y
m
e
ans
of
standard
laborator
y
equip
m
ents. Th
e
analy
s
is, simulation and im
plementation
result sh
owed better perf
ormance of
five-level inv
e
rter.
Keyword:
Fi
ve l
e
vel
i
n
ve
rt
er
Po
wer sem
i
conduct
o
r
Pu
lse wid
t
h
mo
du
latio
n
R
e
newa
bl
e e
n
e
r
gy
sy
st
em
Vo
ltag
e
b
a
lan
c
in
g
Copyright ©
201
5 Institut
e
o
f
Ad
vanced
Engin
eer
ing and S
c
i
e
nce.
All rights re
se
rve
d
.
Co
rresp
ond
i
ng
Autho
r
:
L. Heru
P
r
atom
o,
Depa
rt
em
ent
of El
ect
ri
cal
E
n
gi
nee
r
i
n
g a
n
d
I
n
f
o
rm
at
i
on Te
chn
o
l
o
gy
,
Gad
j
a
h
M
a
da
Uni
v
ersity
,
Jl
.
G
r
afi
k
a No
2. Kam
pus UG
M
,
Y
ogy
a
k
art
a
,
5
5
2
8
1
,
I
n
do
n
e
si
a.
Em
a
il: h
e
ru
.s3
t
e1
2@m
a
il.u
g
m
.ac.id
1.
INTRODUCTION
Mu
ltilev
e
l in
verters hav
e
recen
tly b
een
dev
e
lop
e
d
t
o
ob
tain
goo
d
power
q
u
a
lity. Th
e gen
e
ral
co
n
c
ep
t
o
f
th
is in
v
e
r
t
er
is t
o
u
s
e the pow
er
semico
n
d
u
c
tor sw
itch
e
s to
p
e
r
f
o
r
m
th
e conver
s
ion
p
o
w
e
r
.
W
h
en
com
p
ared to c
o
nve
n
tional pow
er conversi
on approac
h
es,
there are s
o
m
e
adva
nt
ages s
u
ch as a hi
ghe
r
po
we
r
p
r
od
u
c
tion
wav
e
fo
rm
q
u
a
lity an
d
th
e
redu
ced
th
e vo
ltag
e
stress on
lo
ad, h
i
gh
-vo
ltag
e
cap
ab
ility, an
d lo
w
electro
m
a
g
n
e
tic co
m
p
atib
ilit
y. Mu
ltilev
e
l v
o
ltag
e
so
urce i
n
v
e
rters h
a
ve b
e
en
b
r
o
a
d
l
y classified
into
three
main
g
r
o
u
p
s
[1]: Th
e d
i
od
e-cl
a
m
p
e
d
m
u
ltile
v
e
l in
v
e
rter
o
r
th
e m
u
lt
i p
o
i
n
t
-clam
p
ed
co
nverter [2
], th
e fl
yin
g
-
cap
acito
r m
u
lti
lev
e
l co
nv
erter o
r
m
u
lti
cell
i
n
v
e
rter [3
], [4
] an
d
th
e cascad
e
m
u
lt
ilev
e
l i
n
v
e
rter sep
a
rat
e
d
DC
so
urce
o
r
cascad
e
d
H-bridg
e
m
u
l
tilev
e
l in
v
e
rter [5
]. Ot
h
e
r
m
u
l
tilev
e
l in
v
e
rter top
o
l
o
g
i
es, su
ch
as t
h
e mo
du
lar
m
u
l
tilev
e
l in
v
e
rter em
p
l
o
y
in
g h
a
lf bridg
e
[6
]
,
and
h
ybrid
com
b
in
atio
n
s
of t
h
ree b
a
sic grou
p
s
,
h
a
v
e
also
b
e
en
p
r
op
o
s
ed
i
n
the literatu
re si
nce th
e last years [7
]-[9
]
Th
e
d
i
sad
v
a
n
t
ag
e
o
f
m
u
ltilev
e
l po
wer con
v
e
rsio
n is in term
s of the
h
i
gh
er
n
u
m
b
e
r
of sem
i
co
nd
u
c
t
o
r
switch
e
s. Ano
t
h
e
r d
i
sadv
an
tag
e
is t
h
at th
e
sm
a
ll v
o
lta
ge
st
eps a
r
e t
y
pi
c
a
l
l
y
pro
d
u
ced
by
i
s
ol
at
i
n
g
v
o
l
t
a
ge
sources
or a s
e
ries of ca
paci
tor. T
h
e isolat
ed voltage s
o
urces usi
ng a s
e
ries of ca
paci
tors are
re
quired for
v
o
ltag
e
b
a
lan
c
i
n
g
[2
], [4
], [7-9
]. For certain
co
nd
itio
ns, th
e v
o
ltag
e
b
a
lancin
g
is p
o
ssib
l
e to
b
e
o
v
e
rcome b
y
u
s
ing
a
red
und
an
t switch
state. For a com
p
le
te so
lu
tion
to th
e
p
r
ob
le
m
s
o
f
vo
ltage-b
alan
cing
, an
o
t
h
e
r
m
u
l
tilev
e
l in
v
e
rter m
i
g
h
t
,
h
o
wev
e
r, b
e
req
u
ired
[3
].
So
m
e
ap
p
licatio
n
s
fo
r t
h
ese
new m
u
ltilev
e
l i
n
v
e
rters i
n
clude flex
ib
le
AC tran
sm
issio
n
sy
ste
m
s an
d
h
i
gh
p
o
wer med
i
u
m
-v
o
ltag
e
m
o
to
r d
r
i
v
es
[10
]
, [11
]
.
One area
wh
ere
m
u
l
tilev
e
l in
v
e
rters are
p
a
rticu
l
arl
y
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
PED
S
I
S
SN
:
208
8-8
6
9
4
A
Si
mpl
e
St
rat
e
gy of
C
o
nt
rol
l
i
ng a Bal
ance
d
Vol
t
a
ge
C
a
p
a
c
i
t
o
r
i
n
Si
n
g
l
e
Ph
ase…
(
L
. He
ru
Pr
at
om
o)
16
1
su
itab
l
e is th
at
o
f
ren
e
wab
l
e en
erg
y
su
ch
as Pho
t
ov
o
ltaic, wind
tu
rb
in
e i
n
wh
ich
efficien
cy an
d
p
o
wer q
u
a
lity
are of great
concerns of
re
sea
r
che
r
s [1
2]
, [1
3]
.
Th
e au
tho
r
s in
th
eir article [1
4
]
, t
h
e so
urce
vo
ltag
e
is
n
o
t efficien
t i
n
gen
e
ratin
g
out
put
vol
t
a
ge
l
e
vel
.
The t
o
p
o
l
ogy
, f
o
r i
n
st
an
ce can o
n
l
y
pr
od
uce fi
ve l
e
v
e
l
s
of
out
put
w
i
t
h
fo
ur
DC
so
urce
s
,
whi
l
e
t
h
e c
o
n
v
e
nt
i
onal
m
u
l
t
ilevel
i
n
vert
e
r
c
a
n
pr
o
duce
up
t
o
ni
ne
l
e
vel
s
wi
t
h
t
h
e sam
e
am
ount
o
f
t
h
e
sam
e
po
we
r su
ppl
y
.
The ne
w fi
ve
-l
evel
i
n
v
e
rt
er
usi
n
g si
x
po
wer sem
i
cond
uct
o
r swi
t
c
hes
,
t
w
o
di
o
d
es a
nd t
w
o
capaci
t
o
rs i
s
p
e
rf
orm
e
d t
o
acqui
re fi
ve
-l
eve
l
s, but
wi
t
h
a
very com
p
licated use
of
cont
rol system
[15]. This
syste
m
can be
eliminated by
chan
gi
n
g
t
h
e c
ont
rol
m
odel
int
o
an o
p
e
r
at
i
n
g m
odel
based up
o
n
si
nu
soi
d
a
l
pul
se
width m
odulat
ion
usi
n
g pha
s
e shi
f
te
d ca
rrier signal. T
h
i
s
m
odulation
technique
ena
b
les the
equilibri
um
v
o
ltag
e
on
th
e
cap
acito
r t
o
always b
e
p
r
op
erly
m
a
in
tain
ed
with
ou
t an
y
need
s
o
f
sen
s
o
r
an
d
co
m
p
lex
co
n
t
ro
l
sy
st
em
. The
pe
rf
orm
a
nce o
f
p
r
o
p
o
sed
t
o
pol
o
g
y
an
d i
t
s
c
o
nt
rol
l
e
r
we
re
val
i
d
at
ed
wi
t
h
l
a
b
o
rat
o
ry
e
xpe
ri
m
e
nt
s.
2.
R
E
SEARC
H M
ETHOD
In
co
n
v
ent
i
o
n
a
l
m
u
l
t
i
l
e
vel
i
nve
rt
ers
,
po
we
r sem
i
cond
uct
o
r
swi
t
c
hes a
r
e use
d
t
o
ge
n
e
rat
e
hi
gh
-
freq
u
e
n
c
y waveform
in
p
o
s
itiv
e and
n
e
g
a
ti
v
e
po
larity.
Ho
wev
e
r, th
e
u
t
ilizatio
n
o
f
all
th
e switch
e
s
is n
o
t
req
u
i
r
e
d
t
o
p
r
o
duce
t
h
e l
e
vel
of
bi
pol
ar
as
pr
act
i
ced. T
h
i
s
i
d
ea has
bee
n
pra
c
t
i
ced by
t
h
e
n
e
w t
o
p
o
l
o
gy
.
Thi
s
t
o
pol
ogy
i
s
a hy
bri
d
m
u
l
t
i
l
e
vel
t
opol
ogy
, w
h
i
c
h se
parat
e
s t
h
e o
u
t
p
ut
v
o
l
t
a
ge i
n
t
o
t
w
o
part
s. T
h
e
first p
a
rt is call
e
d
as lev
e
l g
e
neratio
n
at p
o
sitiv
e p
o
l
ar
ity, req
u
i
ring
h
i
gh
-freq
u
e
n
c
y switch
e
s to
g
e
n
e
rate th
ree
l
e
vel
s
. T
h
e
p
o
l
ari
t
y
gene
rat
i
o
n
i
s
a
not
her
part
a
s
, t
h
e
l
o
w
-
f
r
e
qu
en
cy
par
t
op
er
atin
g at lin
e fr
equ
e
n
c
y. Th
is
to
po
log
y
refers to
a co
m
b
in
atio
n
o
f
two
p
a
rts. To
g
e
n
e
rate a co
m
p
lete
mu
ltilev
e
l o
u
t
p
u
t, th
e po
sitiv
e
lev
e
ls
are ge
nerat
e
d
by
t
h
e hi
gh
-f
re
que
ncy
pa
rt
an
d t
h
i
s
p
a
rt
su
b
s
eq
uent
l
y
i
s
fe
d t
o
a
n
H
-
b
r
i
d
ge i
n
vert
er
w
h
i
c
h wi
l
l
g
e
n
e
rate th
e req
u
i
red po
larity of th
e ou
tpu
t
[1
5
]
.
Fi
gu
re 1 de
pi
ct
s t
h
e fi
ve-l
evel
i
nvert
er t
o
p
o
l
ogy
, t
h
e
pri
n
ci
pal
i
d
ea of w
h
i
c
h as a
m
u
l
t
i
l
e
vel
i
nve
rt
e
r
is th
at th
e left
stag
e in Figure 1 g
e
n
e
rates th
e three
o
u
t
p
u
t
lev
e
ls and th
e ri
g
h
t
ci
rcu
it d
ecid
e
s abo
u
t
t
h
e
pol
a
r
i
t
y
of t
h
e
out
put
v
o
l
t
a
ge.
Fig
u
re
1
.
Th
e
m
u
l
tilev
e
l in
v
e
rter topo
log
y
i
n
fiv
e
lev
e
ls
Th
e
fiv
e
-lev
el
in
v
e
rter
h
a
s two
cycles and
al
ways ong
o
i
n
g
work fluctu
atin
g
i
n
p
o
s
itiv
e
an
d n
e
g
a
tive
v
a
lu
es. Here is a fiv
e
-lev
el in
v
e
rter
work
ing
prin
ci
p
l
e. The p
o
s
itiv
e
h
a
lf
cycle o
ccu
rs i
n
th
e curren
t
flow as
sho
w
n i
n
Fi
gu
r
e
2
(a-
d
).
1.
Th
e m
o
d
e
o
f
op
eration
1
:
m
a
x
i
m
u
m
p
o
s
itiv
e o
u
t
p
u
t
(+
V
in
):
S
1
, S
3
is ON, co
nn
ecting
the lo
ad
po
sitiv
e
termin
al to
V
in
, and
S
6
, S
2
is ON, conn
ectin
g
th
e l
o
ad n
e
g
a
tiv
e termin
al to
g
r
oun
d. All
o
f
o
t
h
e
r
co
n
t
ro
lled
switch
e
s are
OFF;
th
e v
o
ltag
e
ap
p
lied
t
o
th
e lo
ad
term
in
als is
V
in
. Fi
gure
2 (a) s
h
ows t
h
e
cu
rren
t
p
a
ths t
h
at are activ
e at th
is stag
e. M
o
d
e
op
eratio
n
1
h
a
s an
equ
a
tio
n as
fo
llows:
o
L
i
V
V
V
,
on
o
i
t
V
V
i
L
(
1
)
2.
Th
e
m
o
d
e
o
f
o
p
e
ration
2
and
3
:
A h
a
lf po
sitiv
e
ou
tpu
t
(+
½ V
in
):
S
1
, S
3
is ON, conn
ectin
g th
e load
p
o
s
itiv
e term
in
al, and
S
4
, D
2
i
s
ON, conn
ectin
g th
e lo
ad
n
e
g
a
tiv
e term
in
al to
g
r
ou
nd
t
h
rou
g
h
t
h
e
C
2
(
V
C2
= ½ V
in
).
All of o
t
h
e
r co
n
t
ro
lled
switches are OFF; th
e
v
o
l
tag
e
app
lied
to th
e lo
ad
term
i
n
als is
½ V
in
or
D
1
, S
3
is ON,
co
nn
ecting
th
e lo
ad
po
sitiv
e
termin
al, an
d
S
6
, S
2
is ON,
co
nn
ecting
th
e lo
ad
n
e
g
a
tiv
e
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-86
94
I
J
PED
S
Vo
l. 6
,
No
. 1
,
Mar
c
h
2
015
:
16
0
–
16
7
16
2
termin
al to
g
r
ou
nd
.
All o
f
o
t
her con
t
ro
lled
switch
e
s are
OFF; th
e v
o
ltag
e
ap
p
lied
t
o
th
e lo
ad
term
in
als is
½ V
in
. Fi
g
u
r
e
2(
b)
an
d 2(
c) sho
w
th
e cur
r
e
n
t
p
a
ths th
at
a
r
e
active at this st
age. M
o
de
ope
ration 2 and
3
have
an
eq
uat
i
on
as
fol
l
o
ws:
1
c
i
o
V
V
dt
di
L
V
,
off
i
o
t
V
V
i
L
2
1
.
(
2
)
M
ode
o
p
erat
i
o
n
3
has a
n
e
q
u
a
t
i
on:
2
c
i
o
V
V
d
t
di
L
V
,
on
i
o
t
V
V
i
L
2
1
.
(
3
)
3.
The m
ode
o
f
o
p
erat
i
o
n
4
and
5:
Zer
o
out
put
:
T
h
i
s
l
e
vel
ca
n
be
gene
rat
e
d
by
t
w
o
swi
t
c
hi
ng
co
m
b
in
atio
n
s
; switch
e
s
D
1
, D
2
, S
3
a
nd
S
6
ar
e O
N
,
o
r
D
1
, D
2
, S
4
and
S
5
are
ON
, an
d al
l
o
f
ot
he
r co
nt
r
o
l
l
e
d
switch
e
s are
OFF; term
in
al ou
tpu
t
is a short circu
it,
and
t
h
e vo
ltag
e
app
lied
to th
e lo
ad
t
e
rm
in
als is zero
.
Fi
gu
re
2(
d) a
n
d Fi
g
u
r
e 2
(
e)
s
h
o
w
t
h
e
cu
rre
n
t
pat
h
s t
h
at a
r
e
active at this s
t
age. Mode
operation
4 a
n
d 5
have
an
eq
uat
i
on
as
fol
l
o
ws:
dt
di
L
V
o
,
off
o
t
V
i
L
(
4
)
4.
The m
ode
of
o
p
erat
i
o
n
6,
7
,
8
an
d
9 a
r
e a
hal
f
negat
i
v
e
o
u
t
p
ut
.
(a)
(b
)
(c)
(d
)
Lege
nd:
C
u
rre
nt fl
ow
Fi
gu
re
2.
The
m
ode of
o
p
erat
i
on:
(a)
V
o
= V
in
(b
)
V
o
= ½
V
in
(c)
V
o
= ½ V
in
(d
)
V
o
=
0
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
PED
S
I
S
SN
:
208
8-8
6
9
4
A
Si
mpl
e
St
rat
e
gy of
C
o
nt
rol
l
i
ng a Bal
ance
d
Vol
t
a
ge
C
a
p
a
c
i
t
o
r
i
n
Si
n
g
l
e
Ph
ase…
(
L
. He
ru
Pr
at
om
o)
16
3
Thu
s
, m
a
trix
eq
u
a
tion
ob
tained
in th
e area
of
o
p
e
ratio
ns
1
2
1
1
D
can be prese
n
ted as
follows,
i
i
o
o
V
V
D
V
V
2
1
1
0
0
1
1
.
(
5
)
And t
h
e a
r
ea
of
ope
rations,
2
1
0
2
D
co
me
s
to
b
e
,
0
2
1
1
0
0
1
2
i
o
o
V
D
V
V
.
(
6
)
Th
us t
h
e
o
v
e
r
a
l
l
m
a
t
r
i
x
equat
i
ons
ca
n
be
pres
ent
e
d a
s
f
o
l
l
o
w
s
,
0
2
1
2
1
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
2
1
i
i
i
o
o
o
o
V
V
V
D
D
V
V
V
V
.
(7
)
Whe
r
e:
,
2
1
D
D
D
,
inf
V
V
D
c
D: the
m
odula
tion in
de
x.
c
V
: The am
plitude of
the carrier
signal.
inf
V
: The am
plitude of the
signal inform
ation.
From
the
m
o
d
e
of
ope
ratio
n
that occu
rs,
an eq
uatio
n o
u
tp
ut cur
r
e
n
t r
i
pple can
be
deri
ved
.
A
n
inverter out
put
signal ca
n be
considered as a DC signal that
fluctu
ates i
n
the positive an
d negative val
u
e if the
carrier
f
r
eq
ue
n
c
y
is very
hig
h
.
I
f
the
s
w
itching
pe
rio
d
is e
x
press
e
d
as:
off
on
t
t
f
T
1
.
(
8
)
The operation m
ode
1
and 2, e
quation
output current ri
pple will work
at
the first level to the second level as
prese
n
ted
bel
o
w:
f
L
V
V
V
V
V
V
i
o
i
o
o
i
i
4
3
2
3
2
2
.
(
9
)
The eq
uatio
n
of the
o
u
tp
ut cur
r
ent ri
ppl
e (9) is valid
at the interval
ti
m
e
,
2
1
1
1
D
. The
operation m
o
de 3 and
4, equa
tion
out
put current
ripple
will work at t
h
e second level to the t
h
ird l
e
vel as
presented as
follows:
f
L
V
V
V
V
i
i
o
o
i
2
1
2
1
.
(
1
0
)
The e
quatio
n
o
f
the o
u
tp
ut cu
rre
nt rip
p
le
(10) is
valid at the interval ti
me,
0
2
1
2
D
. At the tim
e
of
ne
gative
flu
c
tuations
, the
v
a
lue o
n
t
h
e
oth
e
r
han
d
bec
o
m
e
s ne
gative.
Where:
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN:
2
088
-86
94
I
J
PEDS
Vo
l. 6
,
No
. 1
,
Mar
c
h
2
015
:
16
0
–
16
7
16
4
:
i
Out
put c
u
rre
nt
rip
p
le
:
f
Switchi
ng
f
r
e
que
ncy
:
L
Inductance
of
the induct
o
r
A
five
-level
inverter
requires
two ca
pacitors
as th
e
linke
d s
e
ries. B
o
th ca
pacitors
are
the
n
c
o
nnecte
d
to a
DC
voltage source. Beca
use the capacitor
voltage m
u
st be in
balance, t
h
is
equilibrium
is determ
ined by
the cha
r
gin
g
a
n
d
disc
har
g
in
g
thr
o
u
g
h
the
p
o
we
r s
w
itches.
Th
us t
h
e am
ount
of
ene
r
gy
s
t
ore
d
in t
h
e ca
pacito
r
will be equal t
o
t
h
e am
ount
of ener
gy st
ored in the in
duct
o
r
.
The val
u
e of the
cap
acitor can
be determ
in
ed as
follows:
L
C
W
W
,
2
2
V
I
L
C
.
(
1
1
)
From
the m
o
de operation i
n
Figu
re 2,
two cycles
can occur
in
operating m
odes in
cludi
n
g positive
and
ne
gative c
y
cles. In this
w
a
y
,
an inv
e
rter
out
put
voltage
(+
V
i
,+½ V
i
, 0,
- ½V
i
, -
V
i
).
Based
on
th
e
op
er
atin
g
m
ode, cha
r
gi
n
g
a
n
d
disc
ha
rg
e occ
u
r
r
ed
in
the ca
pacitor
,
t
hus
creating a
n
a
u
tom
a
tic balance of t
h
e ca
pacitor
voltage
.
A sim
p
le pulse width m
o
d
u
lation tech
ni
que t
o
m
a
ke
the balance
voltage
on capacitor
was
in
tr
odu
ced to
gen
e
r
a
te th
e switch
in
g sign
als
b
a
sed
u
pon
Tab
l
e 1. Th
e r
e
f
e
r
e
n
c
e sign
als
(
V
ref
) were com
p
are
d
with a carrier
signal (
V
carrier
).
Figu
re
3 s
h
o
w
s the
res
u
lti
ng switching pattern. Switches
S
1
, a
nd
S
2
wo
uld b
e
switchin
g
at the rate of the c
a
rrier si
gnal f
r
e
que
ncy
,
w
h
e
r
eas
S
3
,
S
6
and
S
4
,
S
5
would
operate at a fre
que
ncy
that was e
q
uivalent to the
fundam
e
ntal fre
quency. The pr
o
pos
ed
schem
e
of a
m
u
ltilevel inve
rter t
o
p
o
l
ogy
i
n
five levels is shown in Figure 4.
Figu
re
3.
S
w
itchin
g
pattern
f
o
r the
sin
g
le-
p
h
a
se five
-level i
nve
rter
Figu
re 4.
The
pr
o
pose
d
s
c
he
m
e
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
PEDS
I
S
SN:
208
8-8
6
9
4
A
Si
mple Strat
e
gy of
C
o
ntroll
ing a Bal
ance
d
Volta
ge C
a
p
a
c
itor in
Sin
g
le
Ph
ase…
(
L
.
He
ru Pr
at
om
o)
16
5
3.
R
E
SU
LTS AN
D ANA
LY
SIS
Verification
of the analysis and sim
u
lati
on that
have
been
co
n
ducte
d was per
f
o
r
m
e
d,
th
ro
u
g
h
laboratory testing. Table 2
presents
the
parameters used i
n
the sim
u
lat
i
on
and im
plem
entation. T
h
is sc
hem
e
(Fig
ure
4) wa
s
im
plem
ented with ATM
E
G
A
8
5
3
5
m
i
cro-cont
roller u
s
in
g data loo
k
up t
a
bles. M
ean
wh
ile, the
si
m
u
lation of t
h
e control circuit as shown in Figure
4 wa
s im
plem
ented with a
Power Sim
u
lator Software
.
The
sim
u
lation results
s
howed
a num
be
r of switchi
ng functions
on each sem
i
co
nductor s
w
itch
device
.
Com
putational si
m
u
lation resulted in the
form of a switc
hi
ng
function later in the
pr
ogra
m
and inserted into
a
me
m
o
r
y
in
clud
ed in th
e m
i
cr
o-
con
t
ro
ller
8
535
(
F
igu
r
e
5
(
a)
an
d
5
(
b
)). Figur
e
6
(
a)
an
d 6(b
)
show the
im
plem
entatio
n
result
pulse
width
m
odulation
switc
hin
g
si
gnals
f
o
r
switc
hes
S
1
–
S
6
i
n
m
i
cro-controller.
Table
2.
Param
e
ters of sim
u
lation and im
ple
m
entation
V
in
: 300 Volt DC
Capasitor
: 220 uF/450V
I
nductor
:
2
m
H
, 5
m
H
Resistif L
o
ad
: 100 Oh
m
Switching fr
equen
c
y
:
5
KHz, 20KHz
(a)
(b
)
Figu
re
5.
Sim
u
lated wa
ve
fo
rm
s
:
(
a
)
Sw
itch
i
n
g
on
S
1
- S
2
(b)
Switch
i
ng
on
S
3
-S
6
, an
d
S
4
- S
5
(a)
(b
)
Figu
re
6.
Im
plem
ented wa
ve
f
o
rm
s: (a) s
w
itchin
g
on
S
1
- S
2
(b
) Sw
itch
i
ng
on
S
3
-S
6
, an
d
S
4
- S
5
Figu
re 5
(
a) a
n
d 6
(
a) s
h
o
w
a s
i
nus
oidal
p
u
lse
width m
odulat
ion u
s
ed to s
w
i
t
ch
S
1
and
S
2
. Figu
re
5 (b
)
and
6(
b)
m
eanwhile s
h
ow
a
pulse
s
h
ape
r
p
o
larity inverter at 50 Hz used to
switch
S
3
-S
6
and
S
4
- S
5
. In this
strategy, the
power switch
S
1
and
S
2
use
d
a
hig
h
switchi
ng
fre
que
ncy
.
F
o
r this reas
on t
h
e po
wer s
w
itch that
was use
d
m
u
st have a
high s
w
itching
capa
b
ility. Conve
rse
l
y the powe
r
s
w
itch on
S
3
-S
6
and
S
4
- S
5
ca
n use the
po
we
r s
w
itch
with a l
o
w
s
w
itchin
g
fre
que
nc
y
.
Figu
re 7
(
a) s
h
ows t
h
e sim
u
lation res
u
lt of
five-le
v
el v
o
ltag
e
s of in
ve
rter
out
puts
.
The m
a
gnitu
de
of
the first, sec
o
nd
, thir
d, f
o
ur
th, an
d fift
h
voltage
lev
e
ls wer
e
at +300
V, +15
0
V,
0V, -15
0
V and -
3
0
0
V
respectively; whereas to
obt
ain the fu
ndamental value of the f
ilter inductor voltage
has been used. Figure 7
(a) s
h
ow
s the
s
i
gnifica
nt val
u
e of
the
fu
n
d
a
m
ental harm
on
ic voltage
. T
h
e
m
a
gnitude
of t
h
e
voltage
ha
r
m
onics
was related to the ripple current in
Eq
uati
on (
9
) an
d (1
0
)
, ena
b
lin
g to m
i
nim
i
ze the
voltage
harm
onics by
enlarging the
filter indu
ctor (Figure 7(b))
or switching frequency (F
i
g
ure 7(c))
or bot
h
of them
(Figure 7
(d)),
Figu
re
8 s
h
ows
the im
plem
entation
result
of
f
i
ve-level v
o
ltages of
in
verter
out
puts
Figu
re
9 s
h
ow
s the sim
u
lation a
n
d
im
ple
m
e
n
tation result
of voltage
i
n
capacitor, th
e
m
a
gnitu
de
o
f
the first, second, were at 150V. Th
is control strategy is possi
ble equ
ilibrium
voltage on the capacitor.
Balancing t
h
e voltages of DC capacito
rs is very im
portant in controllin
g the
m
u
ltilevel
inverter. The
voltage
balance of DC
capacitor voltages
V
C1
and
V
C2
can be controlled by the powe
r electronic switches
S
1
and
S
2
easily using phase shi
f
ted carrier.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN:
2
088
-86
94
I
J
PEDS
Vo
l. 6
,
No
. 1
,
Mar
c
h
2
015
:
16
0
–
16
7
16
6
(a)
(b
)
(c)
(d
)
Figu
re
7.
Sim
u
lated wa
vef
o
r
m
s of o
u
tp
ut v
o
ltage:
(a
)
f =
5K
Hz,
L =
2m
H (
b
) f
=
5K
H
z
, L =
5m
H (c
)
f =
10K
H
z,
L =
2m
H (d)
f =
10KHz
, L
=
5m
H
Figu
re
8.
Im
plem
ented wa
ve
f
o
rm
s of
o
u
tp
ut
voltage:
f =
5
K
Hz,
L =
2m
H
(a)
(b
)
Figu
re
9.
C
a
pa
citor
voltage:
(
a
) Sim
u
lated w
a
vef
o
rm
s betw
een the
val
u
e
o
f
V
c1
and
V
c2
(b
)
I
m
p
l
e
m
en
ted
wave
f
o
rm
s between
the
valu
e
o
f
V
c1
and
V
c2
4.
CO
NCL
USI
O
N
A
p
r
o
p
o
s
ed
inv
e
r
t
er top
o
l
o
gy h
a
s m
o
r
e
advan
t
ag
es co
m
p
ar
ed
to
th
e conven
tio
n
a
l
on
e in ter
m
s o
f
the
equilibrium
voltage on the capacitor, DC
isolation, control requirem
ents, cost
, and reliabilit
y. It is shown that
this top
o
lo
gy
c
a
n
be a
go
o
d
c
a
ndi
date f
o
r c
o
nve
rters
use
d
i
n
power
applications as i
n
Photovoltaic syste
m
s,
UPS, etc. In the m
e
ntioned
topolo
gy
, the
switchin
g
o
p
e
r
ation was se
pa
rated into
hig
h
and lo
w f
r
e
q
uency
parts.
Pulse
width m
odulatio
n f
o
r t
h
e
inve
r
t
er had
sim
p
licity
requirin
g
n
o
v
o
ltage
balance in the ca
p
acitor.
Furt
her
,
the p
r
op
ose
d
to
pol
o
g
y
can ef
fectiv
ely
wor
k
as
a f
i
ve-level in
vert
er with
a
ne
w carrier fo
r
m
odulation
strategy.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
PEDS
I
S
SN:
208
8-8
6
9
4
A
Si
mple Strat
e
gy of
C
o
ntroll
ing a Bal
ance
d
Volta
ge C
a
p
a
c
itor in
Sin
g
le
Ph
ase…
(
L
.
He
ru Pr
at
om
o)
16
7
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BIOGRAP
HI
ES
OF AUTH
ORS
L. Heru Pratom
o
was born in
Am
barawa, Indonesia,
in 1976
. He receiv
ed th
e B.S. degre
e
fr
om
Chatoli
c Univer
sit
y
, Sem
a
rang,
Indonesia in 19
94 and M
.
Eng degree from
Ba
ndung Institute
of
Techno
log
y
, (ITB)-Bandung, In
donesia in 2004. At a
recent, he is stud
y
i
ng at Ph.D Progra
m
at
Gadjah M
a
d
a
Universit
y
. His c
u
rrent r
e
sear
ch
is focused on m
u
ltil
evel
inve
rter
topolog
y
,
ac
tiv
e
pow
er fil
terin
g a
nd P
V
-
G
r
id S
y
s
t
em
s
.
F. Danang W
i
jay
a
was born in
Yog
y
ak
arta, Ind
one
sia, in 1974
. He receiv
ed th
e B.E.E
and M.E.E
degrees from
Gadjah Mad
a
Univ
ersity
, Yog
y
akarta, Indonesia,
in 1997 and
2001. In 2009,
he
rece
ived Dr.
En
g degree in
ener
g
y
sci
e
nc
es from
Tok
y
o Institu
te of Te
chnolog
y
,
Tok
y
o, Jap
a
n. He
has
been a
le
c
t
urer and r
e
s
e
a
r
cher a
t
the
El
ectr
ica
l Engin
e
ering D
e
par
t
m
e
nt, G
a
dj
ah M
a
da
University
since 1998. His research
inter
ests are
in th
e ar
ea of energ
y
con
v
ersion, electrical
m
a
chines
,
and
p
o
w
e
r el
ec
tronics
Eka Firm
ans
y
ah
was born in Yo
g
y
ak
arta, Indon
esia,
in
1979. He received
the B.E.E from
Gadjah
Mada University
, Yog
y
akarta, Indonesi
a,
in
2001 and M. Eng degr
ee from
Nanyang
Technol
ogical
University
Singapore, in
20
05. In 2010
, h
e
receiv
ed Ph.D degree in
po
wer
ele
ctroni
c from
K
y
us
hu U
n
ivers
i
t
y
, Tok
y
o
,
J
a
pa
n. H
e
has
been a lecture
r and res
e
arch
er at th
e
Ele
ctri
cal Eng
i
n
e
ering Depar
t
m
e
nt, Gadjah M
a
d
a
Un
iversit
y
sin
c
e 2002. His research in
ter
ests are
in th
e
area of po
wer
electronics
and robotics
Evaluation Warning : The document was created with Spire.PDF for Python.