Inter national J our nal of P o wer Electr onics and Dri v e Systems (IJPEDS) V ol. 6, No. 4, December 2015, pp. 693 – 702 ISSN: 2088-8694 693 On the Impact of T imer Resolution in the Efficiency Optimization of Synchr onous Buck Con v erters P edr o Amaral * , C ˆ andido Duarte **,* , and P edr o Costa *** * F aculty of Engineering, Uni v ersity of Porto, Portug al ** INESC TEC - INESC T echnology and Science, Porto, Portug al *** Infineon T echnologies A G, Neubiber g, German y Article Inf o Article history: Recei v ed Aug 27, 2015 Re vised Oct 31, 2015 Accepted No v 14, 2015 K eyw ord: Synchronous b uck con v erter Dead time Sensorless optimization DC/DC con v erter Ener gy ef ficienc y T imer resolution Digital controller ABSTRA CT Excessi v e dead time in complementary switches causes significant ener gy losses in DC-DC po wer con v ersion. The optimization of dead time pre v ents the de gradation of o v erall ef fi- cienc y by minimizing the body diode conduction of po wer switches and, as a consequence, also re duces re v erse reco v ery losses. The present w ork aims at analyzing the influence of one of the most important characteristics of a digital controller , the timer resolution, in the conte xt of dead-time optimization for synchronous b uck con v erters. In specific, the analysis quantifies the ef ficienc y dependenc y on the timer resolution, in a parameter set that com- prises duty-c ycle and dead-time, and also con v erter frequenc y and analog-to-digital con- v erter accur ac y . Based on a sensorless optimization strate gy , the relationship between all these limiting f actors is described, such as the number of bit s of timer and analog-to-digital con v erter . T o v alidate our approach e xperimental results are pro vided using a 12-to-1.8V DC-DC con v erter , controlled by lo w- and high-resolution pulse -width modulation signals generated with an XMC4200 microcontroller from Infineon T echnologies. The measured results are consistent with our analysis, which predicts the po wer ef ficienc y impro v ements not only with a fix ed dead time approach, b ut also with the increment of timer resolution. Copyright c 2015 Institute of Advanced Engineering and Science . All rights r eserved. Corresponding A uthor: Pedro Costa Infineon T echnologies A G Am Campeon 1-12 85579 Neubiber g German y Email: pedro.costa@infineon.com 1. INTR ODUCTION Digital control has been making inroads in the design of lo w-po wer dc-dc con v erters. Besides the benefits brought by digital processing on nonlinear control capabilities, reconfigurability , and reduced noise susceptibility [1, 2], other useful functions become feasible with a digitally-controlled po wer con v erter . F or instance, the ability to further optimize the ener gy ef ficienc y , while k eeping track of it, is of great v alue for an y po wer con v erter system. The present w ork addresses specifically t his issue, by implementing an algorithm for minimizing specific po wer losses on a synchronous b uck-con v erter , and in v estig ating the influence of the main resources on the optimization performance. In a synchronous b uck-con v erter , a minimum dead t ime is often required to pre v ent the occurrence of shoot- through currents. Ho we v er , this short time has the side ef fect of forw ard bias ing the internal body diode in the synchronous switch, causing high conduction losses. These ener gy losses can be described as [3] P loss = V D I out t d,r + t d,f T s (1) where V D is the diode v oltage drop, I out the output current, T s the switching peri od, and t d,r and t d,f the rising and f alling edge dead times, respecti v ely . Fig. 1 illustrates these control signals together with the schematic for the b uck topology used in thi s w ork. A single feedback loop is applied for v oltage mode control, with a digital proportional- inte gral (PI) controller . The proposed ef ficienc y optimization tak es place in the digital domain, follo wing the PI controller , without the need for significant changes in the feedback structure. Evaluation Warning : The document was created with Spire.PDF for Python.
694 ISSN: 2088-8694 [] V in con trol la w PI ADC t on t d,f v H v L PWM digital V dd V dd V ref optimization dead-time t d,r V out [] t on T s v H v L t d,r t d,f t o Figure 1. Synchronous b uck con v erter (a) block diagram; and (b) PWM signals with dead time. Numerous solutions can be adopted for dead-time opt imization. The simplest approach relies on a fix ed dead time t d . Most g ate dri ving inte grated circuits (ICs) and microcontrollers already ha v e complementary PWM modes with fix ed dead time. Ne v ertheless, as the optimum ef ficienc y v aries according to operation conditions (e.g. load, input v oltage, temperature, aging, etc.), the w orst condition i s often used to define t d to a v oid shoot-through, thus the ef ficienc y is not k ept maximized. Alternati v es to define an optimum dead time imply detecting body-diode conduction [4], or pre v enting its occurrence by emulating a diode beha vior in the control [ 5, 6], or by zero crossing detection of the switching-node v oltage ( v DS ) on the synchronous switch [7]. Although s uch adapti v e methods can be quite f ast – about one switching c ycle – their main dra wback is the additional hardw are required to sense v DS , and in some cases the control signal v GS as well. If some speed can be sacrificed, an interesting impro v ement is the so called predicti v e delay [3, 4], in which information from the pre vious c ycle is also included in deciding the present dead time. Most of the optimization approaches just mentioned mak e use of supplementary circuitry to sense the v oltage at the switching node. In contrast, sensorless approaches rely only on e xistent hardw are [8, 9, 10]. These methods mak e use of parameters being already sensed, such as the output v oltage usually acquired for re gulation purposes, or the input current, which is sometimes sensed for current-mode control or circuit protection. In [10], the authors emplo y input current sensing to k eep track of the maximum ef ficienc y . Optimum condi tions for the dead ti me are achie v ed at a minimum input current. Similarly , in [11, 12] the dead times are v ari ed until the duty c ycle gets its minimum v alue. At this particular point, the losses at t he body diode should be minimized, which as a consequence reduce also the re v erse reco v ery losses. This w ay the peak ef ficienc y can be track ed without actually measuring it. In this paper , the impact of the digital controller resources on the ef ficienc y impro v ement is s tudied, namely the timer resolution that af fects the dead time and duty c ycle accuracies, the resolution of the analog-to-digital con- v ersion (ADC), input and reference v oltages, and the switching period. A dead-time optimization algorithm similar to [11] is adopted here, for its simplicity and the relati v ely lo w computation o v erhead. The remainder of this paper is or g anized as follo ws. Ne xt section presents the dead-time optimization analysis of the proposed digitally-controlled synchronous b uck-con v erter , in terms of digital resource usage, opera tion limits, and attainable impro v ement. Prac- tical implementation and prototype measurements are presented in the third section, and final rem arks are follo wing presented, concluding this paper . IJPEDS V ol. 6, No. 4, December 2015: 693 – 702 Evaluation Warning : The document was created with Spire.PDF for Python.
IJPEDS ISSN: 2088-8694 695 t d t on t k V out t t k 1 t k +1 re gulated updated changed Figure 2. Dead time optimization algorithm steps. 2. AN AL YSIS OF DEAD-TIME OPTIMIZA TION The proposed b uck con v erter with dead-time optimization is depicted in Fig. 1. The v oltage at the output is sensed by an ADC channel and the feedback control loop is completely performed in the digital domain, whereas the duty c ycle is set by a digital PI controller . When the output is stable, its v alue is determined by a function of the dead time and duty c ycle, such as follo ws V out = V in t on T s V D t d,r + t d,f T s (2) where V in is the input v oltage and t on =T s the duty c ycle. In f act, the dead time has an opposite ef fe ct to the duty c ycle on the output v oltage. Ne v ertheless, if V out is constant, changing one of these parameters automatically af fects the other . This is actually the essence of some dead-time algorithms [8, 9, 10, 11, 12]. Fig. 2 depicts the three main steps of a generic algorithm, which can be summarized as follo ws 1 1. At a gi v en time instant t k-1 , the dead time t d is changed (for simplicity let us assume t d,r + t d,f = t d ). Prior to an y compensation in the duty c ycle, t on = 0 , this change in t d will disturb the output v oltage, introducing some v ariation V out gi v en by V out = V D t d T s ; t on = 0 (3) 2. At t k , the controller detects the output v oltage v ariation and compensates this de viation by changing the duty c ycle accordingly t on = T s V out V in ; t d = 0 (4) 3. At t k+1 , the output returns to its re gulated v alue, with the con v erter no w operating with ne w v alues both for the duty c ycle and dead time t d = V in V D t on ; V out = 0 (5) The three equations (3)–(5) ha v e been deri v ed deri v ed from (2) and define the set of possible operation points for the algorithm. This set of points is represented by r = ( t on ; t d ; V out ) = t on (1 ; V in =V D ; V in =T s ) (6) which, geometrically , represents a straight line in I R 3 . Naturally , r is limited in domain because the algorithm is running on a microcontroller with finite resources, in specific the ADC and timer . 2.1. Operation limits The output v oltage v ariation is only detectable if it is lar ger than one least-significant bit of the ADC. The duty c ycle and dead time are defined by the PWM signals produced by the timer , which also has a limited resolution. These constraints can be represented in terms of ADC and timer bits, respecti v ely N ADC and N timer , gi v en by V out V ref 2 N ADC (7) t d ; t on T s 2 N timer (8) 1 The time instants relati v e to t k are merely indicati v e of the algorithm states rather than true sequential sample times. Impact of T imer Resolution in the Ef ficiency of Sync hr onous Buc k Con verter s (P edr o Amar al) Evaluation Warning : The document was created with Spire.PDF for Python.
696 ISSN: 2088-8694 -0.06 -0.05 -0.05 -0.04 -0.04 -0.03 -0.03 -0.02 -0.02 -0.01 -0.01 0 0 0 0.01 0.01 0.02 0.02 0.03 0.03 0.04 0.04 0.05 0.05 0.06 0.06 N timer 2 4 6 8 10 12 14 N ADC 2 4 6 8 10 12 14 Figure 3. Contour plot of ' for V ref =V in = 0 : 275 V in terms of number of bits for the timer ( N timer ) and ADC ( N ADC ). T aking such limitations into account, the minimum dead time v ariation, t d,min , can be e xpressed as t d,min = T s V in V D max 1 2 N timer ; V ref V in 1 2 N ADC (9) where the minimum operation point guarantees the maximum algorithm resolution. Graphically , the minimum op- eration point can be determined by simply finding the intersection between the line containi ng the set of all possible solutions with one of the three planes that impose the aforementioned constraints. 2.2. Resour ce utilization The algorithm operation point is defined by one of tw o ar guments of function max( ) gi v en in (9). Let us no w define the param eter ' as the dif ference between the tw o ar guments so that one ca n e v aluate the usage of resources in the algorithm ' = 1 2 N timer V ref V in 1 2 N ADC (10) Fig. 3 depicts the contour plot of ' gi v en by (10). When ' is positi v e, the minimum dead-time v ariation t d,min is defined by the first ar gument in (9) and the optimization is limited by the timer resolution. Con v ersely , if ' is ne g ati v e, t d,min is defined by the second ar gument and the optimization is limited by the ADC. Such limit ation means that, no matter ho w much the other resource is im pro v ed, t d,min will not decrease and the optimization will not impro v e. Ideally , in this conte xt, ' is null and there are no unused resources, which implies N ADC = N timer log 2 V in V ref (11) Thus, typically , N ADC > N timer . 2.3. P o wer efficiency impr o v ement Considering the minimum algorithm operati on point, which yiel ds a dead-time v ariation of t d,min , the po wer losses caused by an initial dead time t d,ini , P loss,ini , can be eliminated in po wer steps P loss,min = V D I out t d,min T s (12) IJPEDS V ol. 6, No. 4, December 2015: 693 – 702 Evaluation Warning : The document was created with Spire.PDF for Python.
IJPEDS ISSN: 2088-8694 697 γ 0 2 4 6 8 10 12 14 16 18 20 Ψ  [in percentage] 0 10 20 30 40 50 60 70 80 90 100 Exact, (15) Approximation, (16) Figure 4. Plots of ( ) using the floor function and its approximation. The number of steps necessary to fully eliminate the initial losses can be e xpressed as = P loss,min P loss,ini = t d,min t d,ini (13) Since only an inte ger number of steps can be tak en, i.e. b c , the ratio between eliminated and initial losses, , can be e xpressed as = P loss,elim P loss,ini = b c (14) The parameter as a function of is depicted in Fig. 4. Note that when is an inte ger , e v en at small v alues, theoretically the losses are completely eliminated. Ho we v er , this only happens at v ery precise points. If suf fers a slightest v ariat ion, the impro v ement will drop significantly . An a v erage v alue can be computed with an approximation of the floor function bc , i.e. b x c = x 1 2 + 1 P 1 k =1 1 k sin (2 k x ) ' x 1 2 . By substitution of , (14) ends up as ' 1 t d,min 2 t d,ini (15) If (9) is replaced in (15) it is possible to predict the amount of po wer loss es that will be eliminated by a duty c ycle minimizing algorithm, running in a controller with defined resources. Naturally , the loss elimination is closer to 100 % as the resolution of the ADC and timer increase. Fig. 5 illus trates the possible impro v ements attainable under a realist scenario. 3. IMPLEMENT A TION The hardw are implementation consists of a synchronous b uck con v erter with input-to-output v oltage 12-to- 1.8 V and maximum current of 5 A (9 W peak po wer). A fix ed load of 0.5 w as used in the e xperi ments. F or the control and dead-time algorithm implementation, an XMC4200 microcontroller unit w as adopted, featuring both lo w- and high-resolution PWM generation peripherals – the lo w resolution has a time step of 8.3 ns and high resolution has a time step of 150 ps . These features allo w for a comparison between tw o dif ferent timer resolutions, as well as their influence in the po wer ef ficienc y optimization to be performed. A duty-c ycle minimizing algorithm w as designed in the microcontroller . Fig. 6 sho ws the prototype boards used for the e xperimentation purpose. 3.1. Output v oltage contr ol law The control loop that re gulates the output v oltage is not only essential to k eep the con v erter oper ating within the desired set point, b ut also because the dead optimization algorithm depends on the minimization of the duty c ycle, Impact of T imer Resolution in the Ef ficiency of Sync hr onous Buc k Con verter s (P edr o Amar al) Evaluation Warning : The document was created with Spire.PDF for Python.
698 ISSN: 2088-8694 16 14 12 N timer 10 8 6 4 5 10 N ADC 15 100 80 60 40 20 0 Ψ  [in percentage] Figure 5. Dependenc y of the ef ficienc y impro v ement f actor with ADC and timer resolutions for t d,ini = 400 ns , V in = 12 V , V D = 0 : 8 V , V ref = 3 : 3 V and T s = 1 = 320 kHz . Buck 12V input card connectors load connectors XMC4200 Figure 6. Buck con v erter and XMC prototype boards. which is defined by this loop. Therefore, the performance of the output v oltage control la w , namely the settling speed and the resolution of the duty-c ycle v alue, is reflected directly on the dead-time optimization algorithm. Firstly , the ADC measures the output v oltage and con v erts it into a 12-bit v alue. This is fed to a PI controller that outputs a ne w duty c ycle, a decimal v alue. The duty c ycle is then written to the re gisters, with possible loss of precision, depending on the timer resolution. This loop is e x ecuted e v ery 20 s . In each iteration, the a v erage duty c ycle D [ n ] is calculated using an e xponential mo ving a v erage filter D [ n ] = D [ n 1] + 1 M d [ n ] D [ n 1] (16) where d [ n ] is the current duty-c ycle v alue and M is a weighting f actor gi v en to the most recent samples – a lar ge IJPEDS V ol. 6, No. 4, December 2015: 693 – 702 Evaluation Warning : The document was created with Spire.PDF for Python.
IJPEDS ISSN: 2088-8694 699 time/500us 0 1 2 3 4 5 6 7 8 9 10 dead time (ns) 0 50 100 150 200 ← ← → duty cycle (%) 19.0 19.5 20.0 20.5 t d,f t d,r duty cycle Figure 7. The results of the dead time optimization algorithm, running at slo w speed. M means a smoother b ut slo wer filtering, while a small v alue implies a noisier b ut f aster response [13]. In the ne xt subsection, the usefulness of this v alue will become clearer . 3.2. Dead-time optimization algorithm The dead-time optimization algorithm should only be e x ecuted when a change in duty c ycle is detected, because for a certain load there is only one optimal dead time ( t d,opt ). This load change is indicated by a v ariation in the a v erage duty c ycle. When the transient stops, the algorithm is triggered and the optimization can tak e place. The algorithm is e x ecuted a total of tw o times, i.e. one for the rising edge dead time and one for the f alling- edge dead time. The dead time is initially set to 200 ns and is decreased with a step t d . In e v ery iteration, a delay allo ws the duty c ycle to settle after the dead-time v ariation. Then, the gradient is calculated and compared to determine in which re gion the current dead time is, i.e. sign( D ) = sign( t d ) ) t d < t d,opt ) diode conduction (17) sign( D ) 6 = sign( t d ) ) t d > t d,opt ) shoot-through re gion (18) When the border between re gions is crossed, a finer search is initiated by in v erting the direction and decreasing the dead-time step. This is repeated until the stop condition D < " is fulfilled, where " is related to the minimum duty-c ycle v ariation imposed by hardw are limits early addressed. F or protection purposes, despite of the e xistence of current limiting circuitry , a minimum dead time constrain is included in the algorithm to a v oid too high currents in the shoot-through re gion. 3.3. Results In order to obtain the da ta from the microcontroller and illustrate the duty-c ycle minimization algorithm running, a fi rst v ersion has been emplo yed at slo w-speed operation. Fig. 7 sho ws the e v olution of the duty-c ycle optimization and respecti v e rising and f alling edge dead times. The duty c ycle decreases 1 % , while both dead times start from 200 ns and con v er ge to around t d,r = 26 : 5 ns and t d,f = 32 : 0 ns . First t d,r is processed and only then t d,f is optimized. It can be noticed that the duty-c ycle peaks, which indicate the instants when the algorithm enters the short circuit re gion, are small and do not pose risk to the hardw are. The algorithm w as then tested at 1 =T s = 320 kHz with tw o dif ferent resolutions in the PWM, a lo w resolution of 8 bits and 12.5 ns , and the high resolution of 14.3 bits and 150 ps . The same ADC has been used in both cases (12 bits and V ref = 3 : 3 V ). In terms of resources, referring to Fig. 3, the high resolution is closer to a null ' , i.e. ' ' 3 : 84 10 3 and ' ' 1 : 76 10 5 , respecti v ely for lo w and high resolutions. The optimum v alue achie v ed for lo w-resolution dead time is 25 ns , both for t d,r and t d,f . An equal v alue for the tw o cases denotes the timer limitation, because of a positi v e v alued ' . On the other hand, in the high resolution optimization the dead times con v er ge to dif ferent v alues, e v en though superior to the lo w resolution case. The initial dead time is set at 200 ns , which is about 80 and 20 times the turn-on and turn-of f times of the po wer switches, respecti v ely . In these conditions the losses are 368.6 mW on the body diode. Fig. 8 depicts proto- type measurements with and without the optimization procedure. It is possible to observ e the body diode conduction Impact of T imer Resolution in the Ef ficiency of Sync hr onous Buc k Con verter s (P edr o Amar al) Evaluation Warning : The document was created with Spire.PDF for Python.
700 ISSN: 2088-8694 (a) (b) Figure 8. Control switch (yello w , 1), synchronous switch (c yan, 2) and switching node v oltage (magenta, 3) – (a) fix ed dead time of 200 ns and (b) with the optimization algorithm. (Fig. 8a), i.e. the ne g ati v e v oltage drops close to the switching node transit ions, which is completely eliminated with dead time optimization (Fig. 8b). T able 1 summarizes the results that were obtained for the tw o v ersions. The mea- surement of the po wer dissipation at the body diode eliminated by the algorithm ( P elim,measure ) has been predicted with relati v e accurac y ( P elim,theory ) with our simplistic analysis. The absolute and incremental ef ficienc y of the con v erter ( con v erter and con v erter , respecti v ely) has been measured as well as the impact on o v erall ef ficienc y of the con v erter and microcontroller ( system ), denoting also significant impro v ements. Lastly , the temperatures were also measured for both the synchronous and control switch. On the fix ed dead time implementation, at 200 ns , the package ambient temperatures we re 43.5 C and 42.5 C , whereas at optimal dead time, when the losses are minimal, the temperatures of the MOSFET packages were the lo west, at 40 and 41 C in lo w and high resolution implementations, respecti v ely . When entering the short circuit re gion, both temperatures increased about 4 C . 4. CONCLUSION This w ork presents a study on the influence of timer and ADC resolutions in the dead-time optimization of b uck con v erters. An analysis of body diode losses and respecti v e minimization by means of digital control has been presented. This analysis includes the hardw are limitations of a sensorl ess algorithm for minimizing the duty- c ycle of digital PWM signals. In spite of the lo w comple xity and reduced computation requirements of the similar sensorless algorithms, most sol utions mak e use of ICs or FPGAs for the implementation of the digital control. The present approach is completely implemented in a microcontroller unit. The designed algorithm demonstrated about 5 % ef ficienc y impro v ement o v er a fix ed dead-time solution and 1 % impro v ements from using lo w- to high-resolution PWM signals. These results are significant and may influence the decision of choosing a controller with this kind of resources for the design of a po wer supply . IJPEDS V ol. 6, No. 4, December 2015: 693 – 702 Evaluation Warning : The document was created with Spire.PDF for Python.
IJPEDS ISSN: 2088-8694 701 T able 1. Experimental results using lo w- and high-resolution PWM. P arameter Resolution Units lo w high N ADC 12 12 bits N timer 8 14.3 bits t d,r ,opt 25 27.5 ns t d,f,opt 25 31.3 ns P elim,theory 76.5 99.6 % P elim,measure 72 98.6 % system 2.5 3.6 % con v erter 3.6 4.9 % con v erter 95.1 96.1 % REFERENCES [1] Y .-F . Liu, E. Me yer , and X. Liu, “Recent de v elopments in digital control strate gies for DC/DC switching po wer con v erters, ” IEEE T r ansactions on P ower Electr onics , v ol. 24, no. 11, pp. 2567–2577, No v 2009. [2] M. Shirazi, R. Zane, and D. Maksimo vi ´ c, “ An autotuning digital controller for DC-DC po wer con v erters based on online frequenc y-response measurement, ” IEEE T r ansactions on P ower Ele ctr onics , v ol. 24, no. 11, pp. 2578– 2588, No v 2009. [3] S. Mappus, “Predic ti v e g ate dri v e boosts synchronous DC/DC po wer con v erter ef ficienc y , ” T e xas Instruments, Application Report SLU A281, April 2003. [4] A. Zhao, A. A. F omani, and W . T . Ng, “One-step digital dead-time correction for DC-DC con v erters, ” in IEEE 25th Annual Applied P ower Electr onics Confer ence and Exposition (APEC’2010) , Feb 2010, pp. 132–137. [5] B. Ack er , C. Sulli v an, and S. Sanders, “Synchronous rectification with adapti v e timing control, ” in IEEE 26th Annual P ower Electr onics Specialists Confer ence (PESC’1995) , v ol. 1, Jun 1995, pp. 88–95. [6] P . Krein and R. M. Bass, “ Autonomous control technique for high-performance switches, ” IEEE T r ansactions on Industrial Electr onics , v ol. 39, no. 3, pp. 215–222, Jun 1992. [7] W . Lau and S. Sanders, “ An inte grated controller for a high frequenc y b uck con v erter , ” in IEEE 28th Annual P ower Electr onics Specialists Confer ence (PESC’1997) , v ol. 1, Jun 1997, pp. 246–254. [8] T . Reiter , D. Poleno v , H. Pr ¨ obstle, and H. G. Herzog, “PWM dead time optimization method for automoti v e multiphase DC/DC-con v erters, ” IEEE T r ansactions on P ower Electr onics , v ol. 25, no. 6, pp. 1604–1614, 2010. [9] A. Pizzutelli, A. Carrera, M. Ghioni, and S. Saggini, “Digital dead time auto-tuning for maximum ef ficienc y operation of isolated DC-DC con v erters, ” in IEEE 38th Annual P ower Electr onics Specialists Confer ence (PESC’2007) , 2007, pp. 839–845. [10] J. Ab u-Qahouq, H. M. H. Mao, H. Al-Atrash, and I. Batarseh, “Maximum ef ficienc y point tracking (MEPT) method and digital dead time control implementation, ” IEEE T r ansactions on P ower Electr onics , v ol. 21, no. 5, pp. 1273–1281, 2006. [11] V . Y ousefzadeh and D. Maksimo vi ´ c, “Sensorless optimization of dead times in dc-dc con v erters with syn- chronous rectifiers, ” IEEE T r ansactions on P ower Electr onics , v ol. 21, no. 4, pp. 994–1002, 2006. [12] H.-W . Huang, C.-Y . Hsieh, K.-H. Chen, and S.-Y . K uo, “Load dependent dead-times controller based on min- imized duty c ycle t echnique for DC- DC b uck con v erters, ” in IEEE 38th Annual P ower Electr onics Specialists Confer ence , Jun 2007, pp. 2037–2041. [13] H. T ajiri and T . K umano, “Input filtering of MPPT control by e xponential mo ving a v erage in photo v oltaic sys- tem, ” in IEEE International Confer ence on P ower and Ener gy (PECon’2012) , Dec 2012, pp. 372–377. Impact of T imer Resolution in the Ef ficiency of Sync hr onous Buc k Con verter s (P edr o Amar al) Evaluation Warning : The document was created with Spire.PDF for Python.
702 ISSN: 2088-8694 BIOGRAPHIES OF A UTHORS P edr o Amaral obtained hi s Bachelor and Master De grees in Electrical and Computer Engineering from F aculty of Engineering, Uni v ersity of Porto (Portug al). His researches are in fields of po wer electronics and microcontrollers. Since 2012 he is with the Microelectronics Student Group in the Department of Electrical and Computer Engineering. He has serv ed also as T eaching Assistant in the same institution. C ˆ andido Duarte recei v ed the Licenciatur a and PhD de grees in electrical and computer engineering from the F aculty of Engineering of the Uni v ersity of Porto (FEUP), Portug al. Since 2009 he has been with the Department of Electrical and Computer Engineering Department at FEUP as a lect urer in courses of electronics, sensors and instrumentat ion. He is also researcher at INESC TEC (formerly INESC Porto). His scientific interests include RF po wer amplifiers, wire- less transcei v er architectures, lo w-po wer mix ed-s ignal IC design, and CMOS circuits for mobile communication systems. P edr o Costa recei v ed the Licenciatur a in Electrical and Computer Enginee ring from the F aculty of the Uni v ersity of Porto, Portug al. He has w ork ed in se v eral semiconductor companies since 2005, in the field of inte grated circuit design and definition. Currently he w orks for Infineon T echnologies, in Munich, German y , in the area of product definition and architecture for industrial microcontrollers. His mai n tw o fields of e xpertise are digital po wer con v ersion and electrical motor control. IJPEDS V ol. 6, No. 4, December 2015: 693 – 702 Evaluation Warning : The document was created with Spire.PDF for Python.