Inter
national
J
our
nal
of
P
o
wer
Electr
onics
and
Dri
v
e
System
(IJPEDS)
V
ol.
11,
No.
3,
September
2020,
pp.
1449
1458
ISSN:
2088-8694,
DOI:
10.11591/ijpeds.v11.i3.pp1449-1458
r
1449
Using
sigma-delta
quantizer
based
PI
f
or
inducti
v
e
po
wer
transfer
systems
Dhafer
J
.
Almakhles
1
,
Aksh
ya
Swain
2
,
Hou
Y
uefeng
3
1
Rene
w
able
Ener
gy
Lab,
Communications
and
Netw
orks
Engineering,
Prince
Sultan
Uni
v
ersity
,
Saudi
Arabia
2
Department
of
Electrical
and
Computer
Engineering,
Uni
v
ersity
of
Auckland,
Ne
w
Zealand
3
Electric
and
Instrument
Section,
Beijing
Haunqiu
Corporation,
China
Article
Inf
o
Article
history:
Recei
v
ed
Aug
2,
2019
Re
vised
Dec
2,
2019
Accepted
Mar
21,
2020
K
eyw
ords:
Inducti
v
e
po
wer
transfer
(IPT)
Proportional
inte
gral
(PI)
Single-delta
quantizer
ABSTRA
CT
In
this
paper
,
a
Sigma-Delta
Quantizer
(
4
-Q)
based
Proportional
and
Inte
gral
control
is
proposed
for
a
wireless
po
wer
transfer
control
system,
namely
inducti
v
e
po
wer
transfer
system.
The
proposed
control
topology
emplo
ys
4
-Qs
to
con
v
ert
the
con
v
entional
signals
(analog/digital
signals)
into
bitsreatm
signals
(1-bit
per
sample
time).
Consider
ing
the
o
v
ersampling
feature
of
4
-Q,
field
programmable
g
ate
array
is
utilized
in
the
implementation
of
the
control
system.
T
o
e
v
aluate
the
ef
fecti
v
eness
of
the
presented
control
topology
,
it
is
compared
with
an
inducti
v
e
po
wer
transfer
control
system
using
the
con
v
entional
proportional
and
inte
gral
controller
.
F
or
the
sak
e
of
sim-
plicity
,
the
comparison
is
carried
out
using
hardw
are
in
Loop.
Both
control
systems
e
xhibit
almost
identical
responses.
Ho
we
v
er
,
the
bitstrea
m
feature
of
the
proposed
PI
controller
significantly
helps
in
reducing
the
hardw
are
resources
(logic
elements)
in
field
programmable
g
ate
array
.
In
addition,
less
wire
routing
and
computational
comple
xity
is
achie
v
ed
due
to
absence
of
multipliers.
This
is
an
open
access
article
under
the
CC
BY
-SA
license
.
Corresponding
A
uthor:
Dhafer
J.
Almakhles
Rene
w
able
Ener
gy
Lab,
Communications
and
Netw
orks
Engineering,
Prince
Sultan
Uni
v
ersity
,
P
.O.Box
No.
66833
Rafha
Street,
Riyadh
11586
Saudi
Arabia.
Email:
dalmakhles@psu.edu.sa
1.
INTR
ODUCTION
Due
to
the
lar
ge
consumption
of
fossil
fuel
in
the
w
orld,
man
y
countries
ha
v
e
acti
v
ely
in
v
olv
ed
in
the
usage
of
rene
w
able
ener
gy
for
sustainability
and
the
pollution
reduction.
The
weakness
of
using
rene
w
able
ener
gy
,
especially
solar
ener
gy
,
is
that
it
is
intermittent
and
v
ariable
[1].
This
intermittent
nature
requires
con
v
entional
po
wer
plants
or
massi
v
e
storage
f
acilities
such
as
battery
banks
as
reserv
ations.
W
ith
the
de
v
elopments
of
electric
v
ehicle
(EV),
a
no
v
el
technology
so-called
v
ehicle
to
grid
(V2G)
system
attract
the
attention
of
both
academia
and
the
industries
[2,
3].
W
ith
V2G
technology
,
the
ener
gy
can
be
stored
in
the
EVs’
battery
.
The
huge
amount
of
car
batteries
could
be
inte
grated
to
a
battery
bank
for
po
wer
grid.
In
order
to
achie
v
e
the
V2G
system,
the
EVs
ha
v
e
to
plug
in
and
out
v
ery
often
and
con
v
enient.
Dragging
char
ging
cables
e
v
erywhere
is
not
an
appropriate
solution.
W
ith
the
recent
de
v
elopment
of
po
wer
electronics
technologies,
a
f
ascinating
wireless
po
wer
transfer
system,
so-called
bidirectional
inducti
v
e
po
wer
transfer
(BIPT)
system
is
sho
wn
to
be
ideally
suited
for
the
V2G
systems.
Generally
speaking,
BIPT
can
be
operated
automatically
and
ef
fecti
v
ely
used
in
as
a
wireless
char
ger
and
dischar
ger
system.
In
the
li
terature,
it
is
recommended
to
mak
e
BIPT
systems
operate
at
a
range
of
frequenc
y
between
10
and
40
kHz
in
order
increase
the
ef
ficienc
y
of
the
J
ournal
homepage:
http://ijpeds.iaescor
e
.com
Evaluation Warning : The document was created with Spire.PDF for Python.
1450
r
ISSN:
2088-8694
entire
system
[4–8].
Further
,
the
performance
of
the
BIPT
system
could
be
enhanced
by
combining
it
with
compensations.
Ho
we
v
er
,
the
BIPTs
together
with
the
compensations
ine
vit
ably
become
more
complicated
with
high-order
resonant
netw
orks;
and
thus
a
rob
ust
controller
with
simple
topology
is
required.
T
ypical
discrete
controllers,
designed
for
po
wer
electronics,
are
often
implemented
on
field
programmable
g
ate
array
(FPGA)
due
to
the
high
speed
and
parallel
processing
FPGAs
of
fer
[9,
10].
Thus,
all
the
interf
acing
signals
with
BIPT
including
the
signals
in
the
processors
ha
v
e
to
be
con
v
ert
ed
to
digital
signals
with
8-bit
,
16-bit,
or
32-bit
signed
fix
ed-point
representation.
Mix
ed-signals
inte
grated
circuits
such
as
analog/digital,
referred
to
as
A/D
and
digital/analog,
referred
to
as
D/A
con
v
erters
are
important
to
be
used
the
proposed
BIPT
control
system.
Most
A/D
con
v
erters
consists
of
uniform
multi-le
v
el
static
quantizer
which
in
turn
require
multi-wires
to
transfer
data.
T
ransmission
of
multi-bit
w
ord
could
be
disordered
when
the
transmis-
sion
becomes
sophisticated.
Furthermore,
general
arithmetic
operation
including
summation
or
multiplication,
are
processed
simultaneously
(parallel
computing),
which
results
in
high
routing
consumption
in
FPGAs
and
complicated
signal
processing.
One
widely
dynam
ic
A/D
con
v
erters
equipped,
so-called
Sigma-Delta
modula-
tion
(
4
-Q)
has
attracted
the
mix
ed-signal
circuits
designers
due
to
its
feature
in
the
reduction
of
the
data
trans-
missions,
routing,
wiring
and
signal
process
ing
[11,
12].
One
of
the
main
adv
antages
of
using
4
-Q
is
that
it
con
v
erts
the
input
signals
to
single-bit
signals
(1-bit
per
sampling
time)
which
pro
vides
unique
features
o
v
er
in
an
y
digital
signal
processors
[13,
14].
In
the
signal
processing
field,
using
4
-Q
of
fers
man
y
important
adv
antages
including
the
nature
of
its
output
signals
which
is
represented
by
single-bit
(boolean
logic
signals).
Representing
signals
by
bitstream
signals
(one-bit
by
sampling
time)
highly
reduce
the
data-transmission
and
routing
to
single
wire
per
each
single-bit
signal.
Secondly
,
single-bit
signals
are
inherently
digital
signals
and
therefore,
signal
con
v
ersion
from
single-bit
signals
to
their
equi
v
alent
digital
signals
to
interf
ace
with
digital
signal
processor
is
not
needed
an
y
more.
Thirdly
,
the
single-bit
signal
processing
are
not
only
simpler
than
con
v
entional
Nyquist
rate
processor
b
ut
also
consumes
less
ener
gy
and
hardw
are
resource
s
(logic
g
ates)
[15-17].
In
the
control
filed,
se
v
eral
papers
[18,
19]
sho
wed
that
the
4
-Q
can
ef
fecti
v
ely
be
emplo
yed
to
control
po
wer
dri
v
ers
directly
as
a
replacement
of
PWM,
which
is
often
the
case
in
man
y
applications
such
as
DC-DC
con
v
erters
and
DC-A
C
in
v
erters.
Recent
researches
combing
con
v
entional
PID
and
generalized
proporti
onal
inte
grals
(GPI)
controllers
dri
v
en
by
single-
bit
signals
ha
v
e
been
studied
in
[20-23],
respecti
v
ely
.
The
stability
of
such
control
systems
has
been
analyzed
using
sliding
mode
theory
,
and
such
system
has
been
made
feasible
in
controlling
the
DC
motor
.
In
this
paper
,
moti
v
ated
by
the
abo
v
e
features
of
using
single-
bit
signal
processing,
a
proposed
PI
that
interf
ace
with
single-bit
signal
i.e.,
using
single-bit
signal
processing
technique,
is
programmed
on
so
called
field
programmable
g
ate
array
(generally
abbre
viated
as
FPGA)
to
control
a
the
po
wer
flo
w
in
typical
BIPT
system.
The
single-bit
feature
of
the
proposed
PI
controller
helps
in
reducing
the
hardw
are
resources
(logic
elements)
in
FPGA.
In
addition,
less
wire
routing
and
computational
comple
xity
is
achie
v
ed
due
to
absence
of
multipliers.
The
paper
is
presented
as
follo
ws:
Section
II
introduce
the
dynamic
of
typical
BIPT
system
and
its
control
problem.
Section
III
sho
w
ho
w
the
simple
system
of
4
-Q
to
deri
v
e
single-bit
PI.
In
the
result
section,
simulation
and
e
xperimental
results
of
the
closed-loop
BIPT
system
are
presented
shoing
the
adv
antages
of
using
4
-Q
in
the
hardw
are
reduction
with
some
conclusions
presented
in
the
final
part
of
the
paper
,
Section
V
.
2.
TYPICAL
BIPT
SUBSYSTEMS
The
topology
of
a
typical
BIPT
is
a
well-established
system
and
sho
wn
in
Figure
1.
As
can
be
seen,
the
BIPT
allo
ws
the
the
po
wer
to
flo
w
with
no
ph
ysical
contacts
from
the
prim
ary
subsystem
to
secondary
subsystem
and
vice
v
ersa.
The
secondary
subsystem
of
the
sho
wn
BIPT
is
connected
through
H-bridge.
When
the
po
wer
flo
ws
wirelessly
through
the
air
-g
ap
from
primary
subsystem
to
pickup
subsystem,
then
primary
subsystem
acts
as
an
in
v
erter
whereas
pickup-subsystem
acts
as
a
re
v
ersible
rectifier
.
Similarly
,
the
primary
subsystem
beha
v
es
as
the
re
v
ersible
rectifier
and
the
pickup
subsystem
operates
on
in
v
erting
mode
when
the
po
wer
wirelessly
transfers
from
the
pickup
subsystem
to
the
primary
subsystem.
The
objecti
v
e
of
t
he
primary
subsystem
con
v
erter
mainly
is
to
generate
a
const
ant
track
current
with
high-frequenc
y
in
windings
of
the
the
primary
subsystem
L
pt
whereas
the
main
goal
of
of
the
pickup
con
v
erter
is
to
manage
and
direct
the
po
wer
transmission
between
both
subsystems.
Note
that
both
sides
of
the
system
,
i.e.,
primary
and
pickup
subsystem
comprise
inductor
-capacitor
-inductor
LC
L
resonant
netw
orks
to
track
the
current
generated
by
the
the
con
v
erter
emplo
yed
in
the
primary
subsystem.
Furthermore,
the
parallel
compensation
for
the
BIPT
Int
J
Po
w
Elec
&
Dri
Syst,
V
ol.
11,
No.
3,
September
2020
:
1449
–
1458
Evaluation Warning : The document was created with Spire.PDF for Python.
Int
J
Po
w
Elec
&
Dri
Syst
ISSN:
2088-8694
r
1451
essentially
acts
as
the
ener
gy
source
with
ef
ficienc
y
reach
up
to
94%
[5].
S
1
+
S
2
+
S
1
-
S
2
-
S
1
+
S
2
+
S
1
-
S
2
-
P
r
i
m
ar
y
S
e
c
on
d
ar
y
P
r
i
m
a
r
y
C
o
n
t
r
o
l
l
e
r
S
e
c
o
n
d
a
r
y
C
o
n
t
r
o
l
l
e
r
M
Figure
1.
T
ypical
BIPT
system
2.1.
Operation
The
BIPT
system
illustrated
in
Figure
1
is
to
be
simplified
further
using
the
equi
v
alent
circuit
in
Figure
2.
In
the
equi
v
alent
circuit
,
it
is
often
considered
that
t
he
primary
subsysetm
is
connected
with
an
A
C
v
oltage
s
o
ur
ce
to
generate
sinusoidal
v
oltage
V
pi
\
0
with
!
frequenc
y
.
Similarly
,
the
pickup
con
v
erter
is
considered
to
be
connected
with
an
A
C
v
oltage
source
with
a
phase
angle
w
.r
.t
the
A
C
v
oltage
source
connected
with
the
primary
subsystem,
which
is
denoted
as
V
si
\
0
.
The
maximum
po
wer
transmission
between
the
primary
subsystem
and
secondary
subsystem
can
only
be
achie
v
ed
when
the
phase
dif
ference
equals
=
2
,
see
[24]
for
more
details.
In
the
normal
operation,
the
LCL
circuit
is
tuned
to
the
track
frequenc
y
!
,
such
that
L
pi
=
L
pt
and
L
si
=
L
st
.
Therefore
!
2
=
1
L
pi
C
pt
=
1
L
pt
C
pt
=
1
L
si
C
st
=
1
L
st
C
st
(1)
Under
these
assumptions,
the
simplified
system
s
ho
wn
in
Figure
2
can
be
represented
by
what
is
called
the
model,
see
Figure
3.
The
sho
wn
model
can
be
utilized
to
mainly
determine
and
accordingly
control
and
the
track
current
I
pt
in
primary
subsystem
and
the
input
current
I
si
in
the
the
pickup
subsystem.
Both
currents
are
e
xpressed
as:
I
pt
=
j
V
pi
!
L
pt
(2)
I
si
=
j
j
!
M
I
p
t
!
L
p
t
=
j
M
V
pi
!
L
pt
L
st
(3)
in
which
M
denotes
the
m
utual
inductance
between
the
the
track
coils
inductance
L
pt
and
pickup
inductance
L
st
,
gi
v
en
by
M
=
k
p
L
pt
L
st
(4)
where
k
denotes
coef
ficient
of
the
coupling
in
the
BIPT
considered
in
this
paper
.
It
is
also
kno
wn
t
h
a
t
the
con
v
erter
in
the
pickup
subsystem
generates
po
wer
e
xpressed
by
P
si
=
R
f
V
si
I
si
g
=
M
V
pi
j
V
si
j
!
L
pt
L
st
sin
(
)
(5)
Using
sigma-delta
quantizer
based
PI
for
...
(Dhafer
J
.
Almakhles)
Evaluation Warning : The document was created with Spire.PDF for Python.
1452
r
ISSN:
2088-8694
M
Figure
2.
Simplified
equi
v
alent
model
of
BIPT
system
M
Figure
3.
The
model
equi
v
alent
circuit
of
the
BIPT
system
From
(5),
it
implies
that
the
po
wer
transmission
can
can
be
ef
fecti
v
ely
optimized
by
controlling
the
phase
angle
and
the
output
v
oltage
V
si
.
F
or
e
xample,
the
maximum
po
wer
can
be
obtained
if
the
phase
equals
90
.
This
means
that
the
pickup
subsystem
is
functioning
at
po
wer
f
actor
(PF)
equals
1
.
F
or
BIPT
sys-
tems,
when
equals
90
,
then
the
po
wer
is
transferring
from
t
he
pickup
subsystem
to
primary
subsystem,
and
if
equals
90
,
then
the
BIPT
opertaes
in
the
re
v
erse
mode,
i.e.,
po
wer
is
transferring
from
the
prim
ary
sub-
system
to
the
pickup
subsystem,
See
[5]
for
more
details.
Thus,
the
output
po
wer
in
(5)
is
optimised
by
directed
by
controlling
the
phase
dif
ference
between
the
primary
subsystem
and
the
secondary
subsystem
in
which
V
pi
=
4
p
2
V
pdc
sin
D
2
=
4
p
2
V
pdc
sin
p
2
(6)
V
si
=
4
p
2
V
sdc
sin
D
2
=
4
p
2
V
sdc
sin
s
2
(7)
with
D
denotes
the
duty
c
ycle
of
D
=
p
=
=
s
=
.
Consider
(6)
and
(7),
by
substitute
both
equations
into
(5),
the
output
po
wer
from
the
primary
susb-
system
to
the
pickup
subsystem
can
be
measured
by
the
follo
wing
equation:
P
si
=
8
M
V
pdc
V
sdc
!
2
L
pt
L
st
sin
p
2
sin
s
2
sin
(
)
(8)
in
which
p
denotes
the
phase
shift
between
the
tw
o
con
v
erter
on/of
f
signals
connected
to
the
H-bridge
in
primary
subsystem.
Similarly
,
s
denotes
the
phase
shift
between
the
tw
o
con
v
erter
on/of
f
signals
connected
to
H-bridge
in
the
pickup
subsystem.
Consider
both
(5)
and
(8),
controlling
con
v
erter
in
the
pickup
subsystem
and
accordingly
output
v
oltage
V
si
is
to
be
used
to
re
gulate
(control)
the
lead/lag
phase
dif
ference
between
on/of
f
signals
that
used
to
switch
tw
o
le
gs
of
the
con
v
erter
.
Therefore,
the
main
objecti
v
e
of
the
proposed
controllers
in
BIPT
is
to
ef
fecti
v
ely
control
the
phase
dif
ference
between
the
on/of
f
signals
to
optimally
control
of
the
po
wer
transmission
between
the
tw
o
subsystems.
2.2.
Contr
ol
algorithm
f
or
BIPT
The
control
algorithms
for
the
considered
BIPT
systems
can
be
designed
to
control
the
duty
c
ycle
to
control
switch
of
the
H-bridge
[4,
24,
25]
and
the
phase
control
[5,
3].
The
controllers
for
both
control
problems
are
mainly
kno
wn
by
1)
the
controller
connected
to
the
primary
subsystem
and
2)
the
controller
connected
to
a
feedback
pickup
subsystem.
The
controller
for
the
duty
c
ycle
is
basically
designed
for
the
open
Int
J
Po
w
Elec
&
Dri
Syst,
V
ol.
11,
No.
3,
September
2020
:
1449
–
1458
Evaluation Warning : The document was created with Spire.PDF for Python.
Int
J
Po
w
Elec
&
Dri
Syst
ISSN:
2088-8694
r
1453
loop
primary
control
subsystem
and
the
same
switch
signals
are
used
to
the
same
H-bridge
connected
to
the
pickup
subsystem
controller
b
ut
without
a
feedback
loop
[24].
This
section
illustrates
the
control
design
for
duty
c
ycle
of
the
pickup
subsystem
controller
.
The
problem
of
designing
controller
for
the
duty
c
ycle
bas
ically
starts
from
considering
(8).
Thus,
the
control
la
ws
can
be
obtained
by
ef
fecti
v
ely
controlling
the
phase
shift
s
between
tw
o
switches
S
1
and
S
2
of
the
con
v
erters
in
pickup
subsystem.
Indeed,
changing
the
duty
c
ycle
of
the
switching
signals
connected
to
the
con
v
erter
directly
changes
output
v
oltage
and
accordingly
control
the
po
wer
transferring
from
the
primary
subsystem
to
the
pickup
subsystem
in
return.
The
phase
delay
between
the
primary
subsystem
and
pickup
subsystem
is
fix
ed
at
either
90
based
on
the
desired
direction
of
the
po
wer
transferring.
The
controller
for
primary
subsystem
should
be
designed
to
control
the
phase
shift
p
in
order
to
sustain
a
constant
sinusoidal
track
current.
Ho
we
v
er
,
to
reduce
the
distortion
of
the
harmonics
at
the
minimum,
the
phase
shift
is
fix
ed
to
p
=
120
.
Figure
4
illustrates
controller
schematic
designed
for
the
duty
c
ycle.
Since
we
used
a
FPGA
for
our
controller
design,
the
all
the
input
s
ignals
must
be
con
v
erted
to
digital
s
ignals.
Therefore,
we
used
A/D
to
con
v
ert
the
continuous-time
input
v
oltage
and
current
connected
to
the
pickup
subsystem
to
digital
signal.
Ne
xt,
both
digital
signals
(v
oltage
and
current)
are
multiplied
by
e
ach
other
to
get
the
po
wer
v
alue.
The
measured
input
po
wer
will
be
compared
by
the
reference
signal
(desired)
and
the
results
(error)
will
be
by
the
controller
to
generate
control
signal.
A
phase
lock
ed
loop
(PLL)
is
ef
fecti
v
ely
designed
as
a
clock
that
generated
by
FPGA
and
utilized
for
system
synchronization
by
measuring
the
phase
of
the
output
v
oltage
of
the
primary
subsystem.
The
phase
shift
s
between
the
tw
o
switches
S
1
and
S
2
of
the
con
v
erter
connected
to
the
pickup
subsystem
changes
between
180
;
in
which
180
gi
v
es
in
the
optimal
po
wer
transfer
in
forw
ard
direction;
and
180
gi
v
es
in
the
optimal
po
wer
transfer
in
the
other
direction.
P
L
L
s
y
n
c
h
r
o
n
i
s
e
d
W
i
t
h
p
r
i
m
a
r
y
o
u
t
p
u
t
v
o
l
t
a
g
e
Con
tro
lle
r
Power
Ref
ere
nce
ADC
Output
V
&
I
0
.
5
+
+
+
-
Signal
Conditio
ner
Sin
()
Signal
Conditio
ner
Sin
()
Phase
Shifter
T
o
s
e
c
o
n
d
a
r
y
C
o
n
v
e
r
t
e
r
+
+
Figure
4.
Control
schematic
for
the
duty
c
ycle
3.
SINGLE-BIT
B
ASED
CONTR
OLLER
Single-bit
based
control
design,
which
uses
4
-Q
significantly
contrib
utes
in
the
reduction
of
the
routing
area
and
hardw
are
resources
(logic
elements
consumption)
since
there
is
no
multiplier
needed
to
design
the
controlle
r
.
This
se
ction
presents
the
concept
of
single-bit
signals
generated
by
4
-Q,
and
the
design
of
single-bit
based
proportional
and
inte
gral
controller
for
BIPT
system.
3.1.
Single-bit
signal
and
4
-Q
The
single-bit
signal
is
switching
signal
which
represented
by
ON
or
OFF
quanta
denoted
by
+
Q
and
Q
.
It
could
also
represents
an
y
bipolar
time
domain
signal.
The
singl
e-bit
signals
are
generated
by
v
arious
types
of
tw
o-le
v
el
quantizers
including
4
-Q,
which
con
v
erts
its
input
signals
to
switching
signals
(called
here
single-bit)
signal.
Figure
5
illustrates
a
typical
fir
st
order
4
-Q.
The
dark
line
sho
ws
the
input
signal
to
be
con
v
erted
to
single
bit
signals
(
dotted
line).
As
can
be
seen,
the
output
of
the
quantizer
is
e
xpressed
by
k
=
1
2
(1
+
sgn
(
s
k
))
=
(
1
8
s
k
0
0
8
s
k
<
0
(9)
Using
sigma-delta
quantizer
based
PI
for
...
(Dhafer
J
.
Almakhles)
Evaluation Warning : The document was created with Spire.PDF for Python.
1454
r
ISSN:
2088-8694
since
sgn
(
s
k
)
=
(
+1
8
s
k
0
1
8
s
k
<
0
:
The
quantizer
sensiti
vity
is
represented
here
by
Q
.
[15].
See
the
BIPT
system
in
Figure
1.
As
mentioned
earlier
,
the
steady
state
error
is
the
dif
ference
between
the
measured
po
wer
and
the
desired
po
wer
,
i.e.,
e
=
P
r
ef
P
sdc
in
which
P
r
ef
and
P
sdc
denote
the
desired
and
measured
po
wer
of
the
pickup
subsystem,
respecti
v
ely
.
The
get
an
optimal
performance
and
guarantee
stability
of
both
4
-Q
and
BIPT
system,
the
quantizer
g
ain
Q
should
be
carefully
set
lar
ger
than
input
signals
to
be
con
v
erted,
in
our
case
e
.
The
condition
can
be
written
as
j
e
j
Q
:
Ho
we
v
er
,
the
v
alue
of
Q
should
sel
ected
as
cl
ose
to
the
maximum
v
al
ue
of
e
as
much
possible
as
we
can
to
a
v
oid
unnecessary
quantization
noise
during
quantisation
process
[21].
Optimally
,
Q
should
be
set
just
equal
the
maximum
boundary
of
e
.
k
e
0
k
ˆ
k
s
k
e
ˆ
Q
1
1
z
Q
Figure
5.
Delat-sigma
quantizer
3.2.
Single-bit
based
contr
oller
The
controller
schematic
dri
v
en
by
single-bit
can
be
designed
using
either
single-bit
blocks
with
in-
put/output
single-bit
signals
or
recently
h
ybrid
PI
controller
[15].
Emplo
ying
se
v
eral
single-bit
blocks
to
e
x-
ecute
an
y
mathematical
operations
requires
man
y
4
-Qs
(double
number
of
the
blocks)
and
thus,
requires
v
ery
careful
deign
process
in
selecting
the
proper
Q
v
alues
used
in
each
block.
As
an
y
quantizer
,
4
-Qs
introduce
quantization
noise
and
therefore,
the
proportional
and
the
inte
gral
using
single-bit
blocks
ha
v
e
to
be
carefully
designed
in
order
to
minimize
the
quantization
noise.
F
or
this
reason,
the
h
ybrid
single-bit
PI,
which
is
proposed
to
control
BIPT
system,
is
gi
v
en
by
^
u
k
=
Qk
p
sgn
(
s
k
)
+
k
i
Q
Z
t
sgn
(
s
k
)
dt
(10)
where
k
p
and
k
i
denote
the
proportional
and
inte
gral
g
ains,
respecti
v
ely
.
The
controller
dri
v
en
single-bit
based
is
often
designed
u
s
ing
input-output
interf
ace
in
boolean
logic
(on-of
f)
format.
In
other
w
ords,
a
4
-Q
is
designed
to
con
v
ert
the
input
signals
to
single-bit
signal
which
in
turn
,
will
be
applied
to
the
digital
processor
to
e
x
ecute
the
control
la
w
,
see
[15,
17]
for
more
details.
In
this
paper
,
PI
controller
embedded
with
4
-Q
is
implemented
on
FPGA.
Firs,
we
con
v
ert
the
continuous-time
system
into
its
discrete-time
approximat
ion
using
Euler’
s
discretization
method.
The
discrete-time
transformation
of
(10)
sho
wn
in
Figure
6,
is
e
xpressed
by
^
u
k
=
^
u
p
k
+
^
u
i
k
in
which
^
u
p
k
=
(
K
U
p
=
+
Qk
p
8
^
k
=
1
K
Lp
=
Qk
p
8
^
k
=
0
and
^
u
i
k
=
(
K
U
i
1
8
^
k
=
1
K
Li
1
8
^
k
=
0
Int
J
Po
w
Elec
&
Dri
Syst,
V
ol.
11,
No.
3,
September
2020
:
1449
–
1458
Evaluation Warning : The document was created with Spire.PDF for Python.
Int
J
Po
w
Elec
&
Dri
Syst
ISSN:
2088-8694
r
1455
with
=
z
1
and
K
U
i
=
QT
s
k
i
,
K
Li
=
QT
s
k
i
,
T
s
denote
the
sampling
period.
The
dark
line
is
the
con
v
entional
signal
whereas
the
thin
line
represents
the
single-bits
signal,
see
[15].
Up
K
Lp
K
k
ˆ
Ui
K
Li
K
1
i
k
u
ˆ
k
u
ˆ
p
k
u
ˆ
Figure
6.
Hybrid
single-bit
PI
4.
SIMULA
TION
AND
EXPERIMENT
AL
RESUL
TS
T
o
in
v
estig
ate
the
performance
of
the
proposed
controller
dri
v
en
by
single-bit,
the
controller
is
designed
and
used
to
ef
fecti
vle
y
control
the
po
wer
transferring
in
a
BIPT
system
.
The
v
alidation
and
v
erifica-
tion
are
carried
out
though
simulations
and
e
xperiment.
Since
the
PI
control
strate
gy
had
a
good
performance
in
simulations,
the
single-bit
controller
w
ould
use
PI
format,
too.
The
system
parameters
of
bidirectional
IPT
system
is
gi
v
en
in
T
able
1.
T
able
1.
P
arameters
of
e
xperimental
prototype
Symbol
V
alue
and
SI
unit
Symbol
V
alue
and
SI
unit
V
dc
125
V
C
T
2
:
48
F
L
pi
46
:
68
H
C
s
2
:
47
F
L
T
22
:
66
H
M
8
H
L
si
23
:
45
H
R
pi
0
:
0163
L
so
46
:
5
H
R
T
0
:
0159
C
pi
2
:
53
F
R
si
0
:
0166
C
so
2
:
53
F
R
so
0
:
0155
4.1.
Simulation
The
main
objecti
v
e
of
this
w
ork
is
to
replace
the
con
v
entional
PI
by
the
a
PI
controller
dri
v
en
by
single-bit
signals.
F
or
BIPT
,
the
des
igned
controller
will
be
used
mainly
to
control
duty
c
ycle
which
will
result
in
modifying
the
phase
dif
ference
between
con
v
erter
switches.
Thus,
the
single-bit
signal
should
switch
with
constant
frequenc
y
.
Since
4
-Q
generates
single-bit
signals
with
v
ariable
frequencies,
then
these
signals
can
be
used
to
dri
v
e
the
BIPT
con
v
erters.
Therefore,
4
-Q
is
replaced
with
con
v
entional
PWM
for
this
purpose.
As
can
be
seen
in
Figure
6,
the
control
signal
is
con
v
entional
signal
to
be
con
v
erted
through
PWM
in
order
deri
v
e
H-bridge
switches.
Figure
7
compares
the
performances
of
PI
controller
dri
v
e
by
single-bit
signals
and
the
con
v
entional
PI
controller
.
Both
controllers
were
used
to
control
and
direct
the
po
wer
transferring
in
both
forw
ard
and
re
v
erse
modes.
It
is
v
ery
clear
that
PI
controller
with
the
single-bit
signal
interf
ace
can
be
used
as
a
replacement
for
the
con
v
entional
PI
controller
for
the
po
wer
flo
w
between
the
BIPT
subsystem.
It
is
also
e
vident
that
there
is
oscillations
in
the
tra
n
s
ferred
po
wer
when
the
BIPT
is
operated
at
steady-state.
At
high
po
wer
rating,
the
oscillations
is
acceptable
in
single-bi
t
PI
in
comparison
with
con
v
entional
PI
controller
.
Ho
we
v
er
,
it
is
noted
that
as
the
magnitude
of
the
po
wer
transferred
between
the
primary
and
backup
subsystem
becomes
less,
the
amplitude
of
oscillations
increases.
The
oscillations
are
ob
viously
caused
by
the
quantization
noise
generated
by
4
-Q.
In
this
e
xperiment,
the
quantizer
g
ain
Q
w
as
set
to
1210
which
is
ob
viously
,
lar
ge
enough
Q
to
introduce
more
noise
to
the
s
ystem
at
lo
wer
po
wer
ratings.
T
o
partially
mitig
ate
the
high
os
cillation
and
impro
v
e
the
performance,
simulations
with
v
ariable
Q
numbers
(fine
Q
settings)
were
carried
out
in
the
literature,
see
[26].
Using
sigma-delta
quantizer
based
PI
for
...
(Dhafer
J
.
Almakhles)
Evaluation Warning : The document was created with Spire.PDF for Python.
1456
r
ISSN:
2088-8694
Figure
7.
The
performances
of
po
wer
flo
w
control
using,
(a)
Con
v
entional
PI,
(b)
single-bit
based
PI
with
fix
ed
Q
and
(c)
single-bit
based
PI
with
v
ariable
Q
.
In
this
w
ork,
the
PI
controller
is
programmed
using
DE0-nano
FPGA.
T
able
2
sho
ws
FPGA
hardw
are
consumption
for
both;
the
con
v
entional
PI
controller
and
the
PI
controller
embedded
with
4
-Q.
The
con-
sumption
of
hardw
are
resources
by
the
PI
controller
embedded
with
4
-Q
are
586
LEs
and
154
dedicated
Logic
Re
gisters
(LRs).
IHo
we
v
er
,
the
con
v
entional
PI
controller
consumes
1302
LEs,
182
dedicated
LEs
and
24
9-bit
multipliers.
It
is
e
vident
that
the
single-bit
based
PI
controller
dramatically
reduces
hardw
are
resources,
routing
and
no
multipliers
needed
by
the
processor
.
T
able
2.
Hardw
are
resources
consumption
Hardw
are
Resources
Con
v
entional
PI
Bitstream
based
PI
Multipliers
2
0
Multiple
x
ers
0
2
DSP
-
Logic
Elements
1302
586
Re
gisters
182
154
DSP
9
9
24
0
Int
J
Po
w
Elec
&
Dri
Syst,
V
ol.
11,
No.
3,
September
2020
:
1449
–
1458
Evaluation Warning : The document was created with Spire.PDF for Python.
Int
J
Po
w
Elec
&
Dri
Syst
ISSN:
2088-8694
r
1457
5.
CONCLUSION
In
this
paper
,
a
ne
w
PI
schematic
with
4
-Q
has
been
designed
and
tested
on
a
prototype
BIPT
system.
The
usefulness
of
this
PI
has
been
v
erified
in
both
simulation
and
HIL
en
vironment.
W
ith
a
proper
design,
the
proposed
controller
achie
v
e
a
good
performances
in
comparison
with
con
v
entional
PI
controller
.
The
single-bit
signals
representation
and
multiplier
-less
s
chematic
significantly
simplified
the
design
of
the
controller
on
hardw
are
le
v
el.
The
compilation
reports
generated
by
FPGA
s
oftw
are
has
sho
wed
a
dramatic
reduction
in
hardw
are
resources
that
consumed
by
PI
controller
embedded
with
4
-Q.
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