Inter
national
J
our
nal
of
P
o
wer
Electr
onics
and
Dri
v
e
Systems
(IJPEDS)
V
ol.
9,
No.
1,
March
2018,
pp.
443
–
456
ISSN:
2088-8694
443
I
ns
t
it
u
t
e
o
f
A
d
v
a
nce
d
Eng
ine
e
r
i
ng
a
nd
S
cie
nce
w
w
w
.
i
a
e
s
j
o
u
r
n
a
l
.
c
o
m
Side
Effects
of
Damping
Element
Insertion
in
LCL
Filter
f
or
DC/A
C
In
v
erter
F
aizal
Arya
Samman,
Ma’arif
Hasan,
T
irza
Damayanti
Department
of
Electrical
Engineering,
F
aculty
of
Engineering
Uni
v
ersitas
Hasanuddin,
Indonesia
Article
Inf
o
Article
history:
Recei
v
ed
Aug.
18,
2017
Re
vised
Dec.
11,
2017
Accepted
Dec.
28,
2017
K
eyw
ord:
Po
wer
Con
v
erter
DC/A
C
In
v
erter
P
assi
v
e
Filter
Harmonics
Resonance
Damping
Circuit
ABSTRA
CT
The
ne
g
ati
v
e
impacts
or
side
ef
fects
of
a
damper
circuit
insertion
in
an
LCL
passi
v
e
filter
util
ized
to
filter
DC/A
C
in
v
erters
output
v
oltage
is
presented
in
this
pa
per
.
F
or
comparati
v
e
study
,
this
paper
discusses
tw
o
damping
configurations,
namely
series
and
parallel
damping,
as
well
as
the
LCL
filter
without
dampi
ng
element.
F
our
cri-
teria
are
used
to
e
xplore
the
impacts
of
the
damper
circuits,
i.e.
their
total
harmonic
distortions
(THDs),
the
output
v
oltage
amplitude,
the
output
po
wer
and
the
po
wer
ef
fi-
cienc
y
.
Theoretic
ally
and
empirically
sho
wn
by
pre
vious
studies,
the
damper
element
insertion
in
the
filte
r
circuit
can
indeed
reduce
the
peak
resonance
frequenc
y
of
the
fil-
ter
in
its
frequenc
y
response
curv
e.
Ne
v
ertheless,
the
damper
insertion
can
potentially
decrease
the
in
v
erters
po
wer
output
and
po
wer
ef
ficienc
y
,
v
oltage
output
amplitude,
and
in
circumstances
cannot
impro
v
e
its
THD
reduction.
The
analysis
results
ha
v
e
sho
wn
that
the
side
ef
fects
depends
also
on
the
load
conditions,
which
are
dif
ferent
for
each
damping
circuit
configuration.
Copyright
c
2018
Institute
of
Advanced
Engineering
and
Science
.
All
rights
r
eserved.
Corresponding
A
uthor:
F
aizal
Arya
Samman
Uni
v
ersitas
Hasanuddin,
F
aculty
of
Engineering,
Dept.
of
Electrical
Engineering
Kampus
Go
w
a,
Jl.
Poros
Malino
Km.
6,
Bontomarannu
92171,
Sula
wesi
Selatan,
Indonesia
Email:
f
aizalas@unhas.ac.id
1.
INTR
ODUCTION
No
w
adays,
the
increase
of
electricity
demands,
the
decrease
of
the
fossil
fuels
supply
and
the
need
for
cleaner
en
vironments
ha
v
e
catalyzed
the
ur
gent
need
for
rene
w
able
ener
gy
sources.
Rene
w
abl
e
ener
gy
sources
such
as
solar
or
sunlight
are
strate
gically
adv
antageous
for
countries
ha
ving
sunn
y
atmospheric
conditions,
i.e.
the
countries
lies
around
the
earth
equatorial
area.
Meanwhile,
researches
in
the
area
of
solar
-cells
or
photo
v
oltaic
(PV)
systems
ha
v
e
been
intensi
v
ely
made
with
special
intention
on
the
impro
v
ement
of
their
ener
gy
ef
ficienc
y
.
In
the
future,
the
higher
solar
ef
ficienc
y
impro
v
ement
will
boost
the
rapid
use
the
solar
cell
not
only
for
industries
b
ut
specially
for
home
scale
ut
ilization.
The
f
abrication
cost
of
solar
cells
should
also
be
decreased
to
reduce
their
cost
in
mark
ets.
Solar
-based
po
wer
plants
ha
v
e
been
established
in
man
y
areas
and
countries.
There
are
some
im
po
r
tant
components
of
a
solar
-based
po
wer
plant.
One
of
them
is
in
v
erter
,
beside
a
char
ge
controller
and
an
ener
gy
storage
unit
such
as
rechar
geable
battery
.
Figure
1a
presents
a
photo
v
oltaic
(PV)
system
wi
th
alternating
current
(A
C)
load.
The
char
ge
controller
consists
of
a
Maximum
Po
wer
Point
T
racer
(MPPT)
module
and
a
battery
char
ger
circuit.
The
MPPT
module
is
used
to
maximize
electric
ener
gy
or
po
wer
transfer
from
PV
panel
to
the
battery
unit.
Because
most
of
rene
w
able
ener
gies
ha
v
e
direct
current
(DC)
po
wer
outputs,
in
v
erters
becomes
an
important
component
in
a
rene
w
able-ener
gy-based
po
wer
plant.
In
v
erter
is
an
electric
de
vice
that
w
orks
to
change
or
con
v
ert
DC
to
A
C
v
oltages.
There
are
some
techniques
to
design
an
in
v
erter
.
One
of
them
is
by
using
a
full-bridge
circuit
incorporating
four
po
wer
electronic
switch
de
vices,
where
four
g
ate
terminals
of
the
switching
de
vices
are
controlled
by
an
electronic
control
unit.
J
ournal
Homepage:
http://iaescor
e
.com/journals/inde
x.php/IJPEDS
I
ns
t
it
u
t
e
o
f
A
d
v
a
nce
d
Eng
ine
e
r
i
ng
a
nd
S
cie
nce
w
w
w
.
i
a
e
s
j
o
u
r
n
a
l
.
c
o
m
,
DOI:
10.11591/ijpeds.v9.i1.pp443-456
Evaluation Warning : The document was created with Spire.PDF for Python.
444
ISSN:
2088-8694
M
P
P
T
M
o
d
u
l
e
B
a
t
t
e
r
y
C
h
a
r
g
e
r
B
a
t
t
e
r
y
U
n
i
t
D
C
/
A
C
I
n
v
e
r
t
e
r
+
F
i
l
t
e
r
L
o
a
d
2
2
0
V
/
5
0
H
z
/
6
0
H
z
S
o
l
a
r
A
r
r
a
y
V
D
C
2
V
D
C
3
V
D
C
1
V
A
C
V
D
C
0
C
h
a
r
g
e
C
o
n
t
r
o
l
l
e
r
U
n
i
t
D
i
s
c
u
s
s
i
o
n
D
o
m
a
i
n
(a)
Photo
v
oltaic
system
F
i
l
t
e
r
9
1
0
1
7
7
1
2
4
V
B
A
T
T
E
R
Y
M
1
M
2
M
3
M
4
5
3
7
8
6
0
N
M
O
S
D
r
i
v
e
r
N
M
O
S
D
r
i
v
e
r
N
M
O
S
D
r
i
v
e
r
N
M
O
S
D
r
i
v
e
r
L
o
a
d
E
l
e
c
t
r
o
n
i
c
C
o
n
t
r
o
l
U
n
i
t
(
E
C
U
)
D
1
D
2
D
4
D
3
C
A
A
(b)
in
v
erter
circuit
topology
Figure
1.
The
photo
v
oltaic
system
and
the
DC/A
C
in
v
erter
and
filter
topology
.
There
man
y
challenging
problems
in
designing
an
in
v
erter
.
Some
of
them
are
summarized
in
the
follo
wing
items.
Po
wer
ef
ficienc
y
and
switching
loss
due
e
xisting
switching
mechanism
Unbalance
v
oltage
due
to
unbalance
loads
in
3-phase
in
v
erter
applications
V
oltage
amplitude
and
po
wer
f
actor
shifting
due
to
loading
conditions
Grid
synchronizations
with
an
e
xisting
grid
for
h
ybrid
po
wer
generation
T
otal
harmonic
distortion
(THD)
due
to
the
used
PWM-based
switching
mechanism
to
control
the
in-
v
erter
output
Most
of
po
wer
losses
in
switched-mode
in
v
erter
circuits
are
due
to
the
e
xisting
switching
mechanism.
Switching
pulses
applied
to
the
g
ate
terminal
of
po
wer
switching
de
vices
will
partially
con
v
ert
electrical
ener
gy
to
be
thermal
ener
gy
.
No
w
adays,
ne
w
silicon
technologies,
such
as
Po
wer
MOSFET
based
on
Silicon
Carbide
(SiC)
technology
can
reduce
po
wer
losses
and
ha
v
e
longer
operating
lifetime
[1],
[2].
Beside
Po
wer
MOSFET
,
another
switching
de
vice
that
can
be
used
is
Insulated
Gate
Bipolar
T
r
ansistor
or
IGBT
.
Lik
e
po
wer
MOSFET
,
IJPEDS
V
ol.
9,
No.
1,
March
2018:
443
–
456
Evaluation Warning : The document was created with Spire.PDF for Python.
IJPEDS
ISSN:
2088-8694
445
the
IGBT
operations
can
also
induce
higher
conductance
losses
and
lo
wer
switching
performance
compared
to
SiC-based
MOSFET
[3].
The
switching
losses
as
well
as
electromagnetic
interference
can
be
a
v
oid
by
a
ne
w
concept
i.e.
by
controlling
the
current
and
v
oltage
slopes
indi
vidually
for
all
operating
conditions
of
the
IGBTs
[4].
V
oltage
balancing
is
also
a
problem
in
in
v
erter
design
especially
in
grid-connected
applications.
St
and-
alone
Micro
Grid
(MG)
tends
to
ha
v
e
unbalancing
v
oltage
af
fected
by
the
unbalanced
load
in
single
phase.
T
o
achie
v
e
the
balancing
of
phase
v
oltage,
each
single
phase
in
v
erter
can
be
controlled
independently
[5].
Other
important
aspects
in
in
v
erter
desi
g
n
are
the
output
v
oltage
amplitude,
po
wer
ef
ficienc
y
and
grid
synchroniza-
tion.
Grid
synchronization
is
especially
v
ery
important
in
3-phase
grid-connected
in
v
erter
applications
[6].
The
use
of
pulse
width
modulation
(PWM)
control
systems,
for
instance
in
A
C
motor
control
appli-
cations,
causes
the
appearance
of
common
mode
v
oltage
(CMV)
at
the
neutral
point.
CMV
suppression
and
elimination
without
influencing
the
in
v
erter’
s
output
v
oltage
and
better
THD
can
be
reached
by
using
a
special
technique
namely
P
artial
elimination
SVPWM
(PE-SVPWM)
and
full
elimination
SVPWM
(FE-SVPWM).[7].
The
used
of
a
coupled
inductor
multiplier
can
also
reduce
the
conduction
losses,
due
to
the
CMV
at
neutral
point,
and
raise
the
ef
ficienc
y
[8].
Z-source
T
-type
in
v
erter
is
an
e
xample
w
ay
to
raise
the
ef
ficienc
y
system
and
to
boost
v
oltage
le
v
el
without
an
y
additional
DC-DC
con
v
erter
or
transformer
.
The
method
mak
es
the
output
current
of
in
v
erter
are
sinusoidal
and
synchronous
with
the
grid
frequenc
y
and
its
phase
[9].
Leakage
current
is
the
dra
wbacks
of
grid-tied
transformerless
in
v
erter
systems.
It
produces
syst
em
losses
and
inject
harmonics
into
the
grid
[10],
[11].
Therefore,
the
use
of
passi
v
e
filter
is
important
to
imple-
ment.
The
THD
e
xistence
causes
the
in
v
erter
output
v
oltage
not
be
able
to
become
pure
sine
w
a
v
e
as
e
xpected.
T
o
suppress
the
harmonic
distortion,
a
passi
v
e
filter
is
coupled
to
the
output
terminal
of
the
in
v
erter
.
According
to
the
IEEE
Standard,
the
acceptable
THD
of
the
in
v
erter
output
v
oltage
should
be
belo
w
5%
[12].
There
are
man
y
filters
that
can
be
used
to
suppressed
the
THD,
such
as
L,
LC,
LCL,
LLCL,
etc
[13],
[14],
[15].
Among
the
aforementioned
filters,
the
LCL
filter
has
better
capability
to
suppress
harmonic
distortion
[16],
[15].
Adding
an
LCL
passi
v
e
filter
to
the
output
terminal
of
an
in
v
erter
can
cause
an
appearance
of
peak
resonance
frequenc
y
.
This
phenomena
can
mak
e
the
in
v
erter
system
unstable
and
its
performance
becomes
weak.
Therefore,
to
suppress
the
resonance
ef
fect
of
the
LCL
passi
v
e
filter
,
a
resistance
component
as
damper
is
inserted
into
the
filter
circuit.
The
resistance
component
inserted
to
the
LCL
pas
si
v
e
filter
is
called
as
a
resistance
damping
[17].
Multi-le
v
el
in
v
erters
are
also
another
type
of
in
v
erter
,
which
is
proposed
to
reduce
harmonics
[18],
[19]
[20].
Multi-le
v
el
in
v
erter
has
multiple
output
v
oltage
le
v
els,
which
is
enabled
by
the
use
of
multiple
DC
source.
In
rene
w
able
ener
gy
applications,
the
design
cost
of
a
multi-le
v
el
in
v
erter
is
higher
compared
to
a
single-le
v
el
in
v
erter
,
due
to
the
need
for
more
DC/DC
con
v
erters
to
maintain
the
v
olt
age
le
v
els
of
the
multiple
DC
sources.
Single-le
v
el
in
v
erters
are
still
f
a
v
orable,
since
the
y
are
more
simple
with
lo
wer
design
cost.
2.
RELA
TED
W
ORKS
AND
CONTRIB
UTION
This
paper
will
particularly
discuss
an
LCL
filter
analysis.
Since
the
use
of
LCL
passi
v
e
filter
c
auses
the
appearance
of
resonant
ef
fect,
a
damping
element
is
used.
By
using
the
damping
elem
ent,
the
ef
fect
of
resonant
can
be
suppressed
[17],
[21].
Ho
we
v
er
,
the
resonance
damping
resistor
will
raise
an
e
xtra
po
wer
loss,
reduce
maximum
v
oltage
amplitude
and
weak
en
the
high-frequenc
y
harmonic
reduction
capability
.
This
paper
will
sho
w
a
com
p
a
rati
v
e
study
on
a
fe
w
filter
circuit
with
and
without
damping
element.
The
LCL
passi
v
e
filter
with
and
without
the
resistance
damping
tested
with
resistance
loads.
The
criteria
used
in
this
study
are
the
capability
of
LCL
passi
v
e
filter
with
and
without
resistance
damping
in
reducing
the
harmonic
distortion,
maintaining
the
maximum
output
v
oltage
amplitude
and
a
v
erage
output
po
wer
as
well
as
the
po
wer
ef
ficienc
y
of
in
v
erters
and
filters.
T
o
the
best
of
the
author’
s
kno
wledge,
the
study
of
this
paper
,
which
is
based
on
concurrent
anal
ysis
of
those
four
criteria
with
v
ariable
(resistance)
loads,
has
not
been
e
xplored
by
the
pre
vious
w
orks.
The
w
ork
in
[17],
for
e
xample,
in
v
estig
ates
man
y
filters
with
acti
v
e
and
passi
v
e
damping
methods.
The
w
ork
in
[22]
proposes
dif
ferent
passi
v
e
damping
tuning
methods
and
its
analytical
damping
losses
estimation.
Ne
v
ertheless,
both
do
not
e
xpose
the
impact
of
the
resonance
damping
element
insertion
for
dif
ferent
load
conditions
with
e
xtra
side
ef
fects
analysis
on
the
THD,
po
wer
output,
po
wer
ef
ficienc
y
and
the
output
v
oltage
amplitudes.
V
ariable
loading
conditions
should
be
tak
en
into
account,
since
in
practical
conditions,
the
load
is
unkno
wn
and
can
potentially
af
fect
the
load
v
oltage
and
load
current
v
ariables.
Moreo
v
er
,
the
load
can
be
topologically
Side
Ef
fects
of
Damping
Element
Insertion
in
LCL
...
(F
aizal
Arya
Samman)
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446
ISSN:
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in
v
olv
ed
as
the
part
of
the
filter
.
3.
RESEARCH
METHOD
T
o
achie
v
e
the
research
objecti
v
e,
systematical
steps
are
used
to
e
xplore
the
filter
and
in
v
erter
circuit
characteristics.
The
filter
and
in
v
erter
are
modeled
in
(Simulation
Program
with
Inte
grated
Circuit
Emphasis).
The
transfer
function
of
the
filter
is
also
mathem
atically
modeled
and
then
numerically
modeled
to
obtain
the
frequenc
y
response
curv
es.
By
using
a
SPICE
simulator
,
the
in
v
erter+filter
circuits
are
simulated
for
dif
ferent
load
impedance
v
alues
to
measure
some
parameters
and
v
ariables,
i.e.
1.
The
THD
or
total
harmonic
distortion
of
the
filter
output
v
oltages.
The
analysis
is
made
for
100
harmonic
frequenc
y
v
alues,
where
50
Hz
is
set
as
the
base
frequenc
y
.
2.
The
v
oltage
amplitude
v
alues
at
the
in
v
erter’
s
input
and
output
terminals,
as
well
as
at
the
filter
output
terminal.
3.
The
a
v
erage
output
po
wers
at
the
in
v
erter’
s
input
and
output
terminals,
as
well
as
at
t
he
filter
output
terminal.
4.
The
po
wer
ef
ficienc
y
of
the
in
v
erter
output
po
wer
o
v
er
the
in
v
erter
input
po
wer
,
the
filter
output
po
wer
o
v
er
the
in
v
erter
output
po
wer
,
and
the
ef
ficienc
y
of
the
filter
output
po
wer
o
v
er
the
in
v
erter
input
po
wer
.
After
collecting
the
simulation
data,
t
he
characteristic
curv
es
of
all
four
aforementioned
sim
ulation
parameters
relati
v
e
to
the
changes
of
load
impedance
v
alues
are
plotted,
and
then
some
concluding
remarks
are
gi
v
en.
4.
FIL
TER
MODELING
AND
AN
AL
YSIS
The
simulated
in
v
erter
and
filter
circuit
is
presentedg
in
Figure
1b.
The
in
v
erter
as
well
as
the
filter
circuit
is
modelled
in
SPICE.
The
electronic
control
unit
(ECU)
as
sho
wn
in
the
figure
generates
four
sinusoidal
pulse
width
modulation
(SPWM)
signals.
The
v
oltage
le
v
el
of
the
SPWM
signals
is
amplified
using
NMOS
g
ate
dri
v
er
such
that
i
t
can
dri
v
e
the
n-channel
po
wer
MOSFET
at
the
points
3,
5
,
6
and
8,
respecti
v
ely
as
sho
wn
in
Figure
1b.
Each
tw
o
of
the
SPWM
signals
has
similar
p
ha
se
and
w
a
v
eform.
The
w
a
v
eform
of
SPWM
signals
at
the
points
3
and
8
is
similar
,
while
the
other
one
at
the
points
5
and
6
is
also
similar
.
The
NMOS
dri
v
er
increases
the
v
oltage
le
v
el
to
ef
fecti
v
ely
dri
v
e
the
NMOS
g
ate
terminal.
In
general
this
dri
v
er
separates
optically
the
po
wer
con
v
erter
circuit
(ha
ving
higher
po
wer)
wi
th
the
electronic
control
unit
(ha
ving
lo
wer
po
wer),
or
is
used
to
protect
the
ECU
from
the
higher
po
wer
circuit.
In
order
to
generate
a
sine
w
a
v
eform
from
the
output
terminal
of
the
in
v
erter
,
we
need
to
generate
some
signals
to
control
the
process.
Normally
,
this
process
is
m
ade
under
control
of
the
ECU.
The
ECU
should
be
programmed
to
generate
tw
o
sine-based
pulse
width
modulation
(SPWM)
as
presented
by
the
curv
es
at
the
second
and
third
line
plots
in
Figure
2.
In
order
to
generate
the
SPWM
signals,
there
are
some
techniques
that
can
be
used.
One
of
them
is
illustrated
from
the
curv
es
at
the
first
line
plot
in
the
Figure
2.
An
absolute
sine
w
a
v
e,
called
as
modulating
signal
(
V
mod
),
is
generated
ha
ving
50
Hz
frequenc
y
,
as
well
as
a
carrier
signal
(
V
car
r
)
in
sa
wtooth
w
a
v
eform.
The
figure
presents
the
carrier
signal
with
20
sa
wteeth
in
e
v
ery
half
period
of
the
sine
w
a
v
e
signal.
Both
signal
are
compared
each
other
to
generate
the
SPWM
using
the
follo
wing
rule.
When
V
car
r
>
V
mod
then
V
g
ate
=
0
,
else
V
g
ate
=
5
V
.
W
e
assume
that
the
logic
’1’,
generated
by
the
ECU,
is
related
to
5
V
.
During
the
first
half
period
of
the
sine
w
a
v
e
signal,
the
SPWM
signal
is
applied
to
the
g
ates
of
MOSFET
M1
and
M4.
Then,
du
r
ing
the
ne
xt
second
half
period,
the
SPWM
signal
is
applied
to
the
g
ates
of
MOSFET
M2
and
M3.
Consecuti
v
ely
applying
this
periodic
w
a
v
eform
to
the
MOSFET
g
ate
terminals,
then
we
will
ha
v
e
the
in
v
erter’
s
output
v
oltage
as
sho
wn
in
the
fourth
line
plot
in
the
Figure
2.
It
seems
that
the
in
v
erter
generates
A
C
signal
b
ut
with
lar
ge
total
harmonic
distortion
(THD).
Because,
the
output
v
oltage
of
the
in
v
erter
cont
ains
the
THD
v
alue
lar
ger
than
5%,
then
a
filter
circuit
is
required
to
decrease
the
THD
belo
w
5%.
There
man
y
types
of
filters
that
can
be
used
to
suppress
the
THD.
In
general,
the
filter
can
classified
as
acti
v
e
and
passi
v
e
filters.
Acti
v
e
filters
are
rarely
use
d
due
to
the
comple
xity
of
circuit,
especially
for
high
po
wer
applications.
P
assi
v
e
filters
are
most
ly
used
in
industries
because
of
their
IJPEDS
V
ol.
9,
No.
1,
March
2018:
443
–
456
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IJPEDS
ISSN:
2088-8694
447
0
0.005
0.01
0.015
0.02
0.025
0
0.5
1
Inverter Output without Filter (20 sawteeth per half period)
Vcarr Vmod (V)
Carrier Voltage
Modulator Voltage
0
0.005
0.01
0.015
0.02
0.025
0
2
4
6
Vgate1,4 (V)
0
0.005
0.01
0.015
0.02
0.025
0
2
4
6
Vgate2,3 (V)
0
0.005
0.01
0.015
0.02
0.025
−20
0
20
Inv. Vout (V)
Time (second)
Figure
2.
The
in
v
erter
output
signal
generation
without
filter
by
using
20
sa
wteeth
per
half
period
(The
THD
of
the
in
v
erter’
s
output
v
oltage
is
47.829%).
simple
use
and
lo
w
cost
utilizat
ion.
the
discussion
about
the
used
filters
to
suppress
the
THD
is
presented
in
the
follo
wing
sub
section.
R
d
s
L
1
C
L
2
Z
L
F
i
l
t
e
r
+
s
e
r
i
e
s
d
a
m
p
e
r
L
o
a
d
V
i
n
V
o
u
t
(
b
)
L
1
C
L
2
Z
L
F
i
l
t
e
r
w
i
t
h
o
u
t
d
a
m
p
e
r
L
o
a
d
V
i
n
V
o
u
t
(
a
)
R
d
p
L
1
C
L
2
Z
L
F
i
l
t
e
r
+
p
a
r
.
d
a
m
p
e
r
L
o
a
d
V
i
n
V
o
u
t
(
c
)
V
d
V
d
V
d
Figure
3.
The
circuit
configuration
of
the
filters
under
e
v
aluation:
(a)
filter
without
damping,
(b)(c)
filters
with
passi
v
e
series
and
parallel
damping
methods
[17].
4.1.
Filter
Model
without
Damper
The
filter
model
without
a
dam
per
element
is
presented
in
Figure
3(a).
The
transfer
function
of
the
V
out
(
s
)
V
d
(
s
)
is
as
follo
ws.
Side
Ef
fects
of
Damping
Element
Insertion
in
LCL
...
(F
aizal
Arya
Samman)
Evaluation Warning : The document was created with Spire.PDF for Python.
448
ISSN:
2088-8694
V
out
(
s
)
V
d
(
s
)
=
Z
L
sL
2
+
Z
L
(1)
The
transfer
function
of
the
V
d
(
s
)
V
in
(
s
)
is
as
follo
ws.
V
d
(
s
)
V
in
(
s
)
=
1
s
2
L
1
C
+
1
(2)
By
using
the
Laplace
T
ransform
Characteristic,
the
transfer
function
of
V
out
(
s
)
V
in
(
s
)
can
be
obtained
by
multiplying
Eq.
(1)
and
Eq.
(2),
which
results
in
the
follo
wing
equation.
V
out
(
s
)
V
in
(
s
)
=
Z
L
sL
2
+
Z
L
1
s
2
L
1
C
+
1
(3)
Simplifying
Eq.
(3),
we
will
ha
v
e
the
final
transfer
function
form,
i.e.
V
out
(
s
)
V
in
(
s
)
=
Z
L
s
3
L
1
L
2
C
+
s
2
Z
L
L
1
C
+
sL
2
+
Z
L
(4)
4.2.
Filter
Model
with
Series
Damper
The
filter
model
with
a
damper
element
inserted
in
series
with
the
C-element
of
the
filter
is
presented
in
Figure
3(b).
Z
ds
is
obtained
by
deri
ving
the
equi
v
alent
impedance
between
the
C-element
and
the
series
resistant
damper
R
ds
,
i.e.
Z
ds
=
R
ds
+
1
sC
=
sR
ds
C
+
1
sC
(5)
The
transfer
function
of
the
V
out
(
s
)
V
d
(
s
)
is
the
same
result
presented
in
Eq.
(1).
The
transfer
function
of
the
V
d
(
s
)
V
in
(
s
)
is
as
follo
ws.
V
d
(
s
)
V
in
(
s
)
=
Z
ds
sL
1
+
Z
ds
=
sR
ds
C
+
1
s
2
L
1
C
+
sR
ds
C
+
1
(6)
By
using
the
Laplace
T
ransform
Characteristic,
the
transfer
function
of
V
out
(
s
)
V
in
(
s
)
can
be
obtained
by
multiplying
Eq.
(1)
and
Eq.
(6),
which
results
in
the
follo
wing
equation.
V
out
(
s
)
V
in
(
s
)
=
Z
L
sL
2
+
Z
L
sR
ds
C
+
1
s
2
L
1
C
+
sR
ds
C
+
1
(7)
Simplifying
Eq.
(7),
we
will
ha
v
e
the
final
transfer
function
form,
i.e.
V
out
(
s
)
V
in
(
s
)
=
sZ
L
R
ds
C
+
Z
L
s
3
L
1
L
2
C
+
s
2
(
Z
L
L
1
C
+
R
ds
L
2
C
)
+
s
(
L
2
+
Z
L
R
ds
C
)
+
Z
L
(8)
4.3.
Filter
Model
with
P
arallel
Damper
The
filter
model
with
a
damper
element
inserted
in
parallel
with
the
C-element
of
the
filter
is
pres
ented
in
Figure
3(c).
Z
dp
is
obtained
by
deri
ving
the
equi
v
alent
impedance
between
the
C-element
and
the
series
resistant
damper
R
dp
,
i.e.
Z
ds
=
R
dp
1
sC
R
dp
+
1
sC
=
R
dp
sR
dp
C
+
1
(9)
The
transfer
function
of
the
V
out
(
s
)
V
d
(
s
)
is
the
same
result
presented
in
Eq.
(1).
The
transfer
function
of
the
V
d
(
s
)
V
in
(
s
)
is
as
follo
ws.
IJPEDS
V
ol.
9,
No.
1,
March
2018:
443
–
456
Evaluation Warning : The document was created with Spire.PDF for Python.
IJPEDS
ISSN:
2088-8694
449
V
d
(
s
)
V
in
(
s
)
=
Z
dp
sL
1
+
Z
dp
=
R
dp
s
2
R
dp
L
1
C
+
sL
1
+
R
dp
(10)
By
using
the
Laplace
T
ransform
Characteristic,
the
transfer
function
of
V
out
(
s
)
V
in
(
s
)
can
be
obtained
by
multiplying
Eq.
(1)
and
Eq.
(10),
which
results
in
the
follo
wing
equation.
V
out
(
s
)
V
in
(
s
)
=
Z
L
sL
2
+
Z
L
R
dp
s
2
R
dp
L
1
C
+
sL
1
+
R
dp
(11)
Simplifying
Eq.
(11),
we
will
ha
v
e
the
final
transfer
function
form,
i.e.
V
out
(
s
)
V
in
(
s
)
=
Z
L
R
dp
s
3
R
dp
L
1
L
2
C
+
s
2
(
L
1
L
2
+
Z
L
R
dp
L
1
C
)
+
s
(
Z
L
L
1
+
R
dp
L
2
)
+
Z
L
R
dp
(12)
4.4.
Fr
equency
Response
Characteristic
After
obtaining
the
transfer
function
of
the
filter
circuits
with
three
dif
ferent
damping
element
con-
figuration,
including
the
one
without
damping
element,
then
this
subsection
presents
the
frequenc
y
response
characteristic
of
the
filters.
Figure
4
presents
the
bode
plot
comparison
of
the
filter
circuits.
10
2
10
3
−20
0
20
40
60
Freq. Response of the Filters (Rds=3 Ohm, Rdp=300 Ohm)
Frequency (rad/s)
Magnitude
10
2
10
3
−200
−100
0
100
200
Frequency (rad/s)
Phase (deg.)
no damp.
series damp.
parallel damp.
Figure
4.
The
transfer
function
of
the
filter
with
and
without
damping.
5.
SIMULA
TION
RESUL
TS
AND
AN
AL
YSIS
The
steady-state
and
transient
analysis
or
simulation
results
of
some
important
measured
v
ariables
in
the
in
v
erter
plus
filter
configurations
are
presented
in
this
section.
the
simulations
are
made
using
SPICE
Side
Ef
fects
of
Damping
Element
Insertion
in
LCL
...
(F
aizal
Arya
Samman)
Evaluation Warning : The document was created with Spire.PDF for Python.
450
ISSN:
2088-8694
(Simulation
Program
with
Inte
grated
Circuit
Emphasis),
which
is
an
industry
standard
circuit
simulator
.
The
measured
parameters
are
in
v
erter’
s
and
filter’
s
output
v
oltages,
output
currents,
output
po
wers
including
the
a
v
erage
output
po
wers.
The
THD
and
po
wer
ef
ficienc
y
measurements
of
the
in
v
erter
and
filter
circuit
are
also
made
in
the
analysis.
5.1.
Steady-State
P
oint
Analysis
In
this
steady
state
point
analysis
or
simulation,
the
measured
parameters
are
THD,
v
oltage
and
current
amplitudes,
output
po
wer
and
po
wer
ef
ficiencies.
In
e
v
ery
simulation
run,
the
circuit
is
simulated
until
the
steady-state
condition
is
attained,
and
then,
the
parameters
are
observ
ed
from
the
SPICE
output
probe
windo
ws.
The
simulation
results
are
sho
wn
in
the
follo
wing
sub
sections.
5.1.1.
THD
and
V
oltage
Amplitude
Measur
ements
The
upper
section
of
Figure
5
sho
ws
the
THD
measurements
at
the
filter’
s
output
points.
Each
fig-
ure
presents
three
THD
curv
es
comparisons
between
the
in
v
erter+filter
circuits
without
damping,
with
series
damping
and
with
parallel
damping
for
dif
ferent
resistance
loads,
i.e.
from
10
0
until
10
5
.
As
sho
wn
in
the
figure,
the
filter
without
damping
element
presents
the
best
THD
v
alues,
when
the
load
impedance
is
abo
v
e
20
.
Belo
w
that
impedance
v
alue,
the
filters
with
damping
elements
ha
v
e
better
THD
v
alues,
b
ut
all
of
them
ha
v
e
THD
abo
v
e
5%,
the
standardized
THD
limit.
10
0
10
1
10
2
10
3
10
4
10
5
0
5
10
15
20
Resistive Load (Ohm)
THD (%)
THD Curves, Inverter and Filter Output Voltages
10
0
10
1
10
2
10
3
10
4
10
5
26
Inverter Vout (V)
10
0
10
1
10
2
10
3
10
4
10
5
0
100
200
300
Resistive Load (Ohm)
Filter Vout (V)
LCL without Damping
LCL with Series Damping
LCL with Parallel Damping
Figure
5.
The
THD
measurements.
The
middle
and
lo
wer
sections
of
Figure
5
sho
ws
the
v
oltage
amplitude
measurements
at
the
in
v
erter’
s
and
filter’
s
output
points.
Each
figure
presents
the
curv
es
comparisons
between
the
in
v
erter+filter
circuits
without
damping,
with
series
damping
and
with
parallel
damping
for
dif
ferent
resistance
loads,
i.e.
from
10
0
until
10
5
.
The
v
oltage
measurements
at
the
in
v
erter’
s
input
terminal
are
not
presented,
since
the
y
present
equal
v
alue,
i.e.
24
V
for
each
aforementioned
resistance
load
v
alue.
IJPEDS
V
ol.
9,
No.
1,
March
2018:
443
–
456
Evaluation Warning : The document was created with Spire.PDF for Python.
IJPEDS
ISSN:
2088-8694
451
The
filter
output
v
oltage
amplitudes
of
the
circuit
without
damping
element
presents
higher
v
al
ues
compared
to
the
filters
with
series
and
parallel
damping
element,
especially
for
the
load
impedance
abo
v
e
10
.
F
or
the
load
impedance
belo
w
10
,
all
filter
circuit
presents
almost
the
same
results.
5.1.2.
Curr
ent
Measur
ements
Figure
6
sho
ws
the
current
measurements
at
the
in
v
erter’
s
and
filter’
s
input-output
points.
Each
figure
presents
three
current
curv
es
comparisons
between
the
in
v
erter+filter
circuits
without
damping,
with
series
damping
and
with
parallel
damping
for
dif
ferent
resistance
loads,
i.e.
from
10
0
until
10
5
.
At
the
upper
part
of
the
figure,
the
current
measurements
at
the
in
v
erter’
s
input
terminal
are
presented.
At
the
middle
part
of
the
figure,
the
current
measurements
at
the
in
v
erter’
s
output
terminal
are
presented.
At
the
bottom
part
of
the
figure,
the
current
measurements
at
the
filter’
s
output
terminal
are
presented.
10
0
10
1
10
2
10
3
10
4
10
5
0
10
20
30
40
Inverter Iin (A)
LCL without Damping
LCL with Series Damping
LCL with Parallel Damping
10
0
10
1
10
2
10
3
10
4
10
5
0
5
10
Inverter Iout (A)
LCL without Damping
LCL with Series Damping
LCL with Parallel Damping
10
0
10
1
10
2
10
3
10
4
10
5
0
0.5
1
1.5
Resistive Load (Ohm)
Filter Iout (A)
LCL without Damping
LCL with Series Damping
LCL with Parallel Damping
Figure
6.
The
current
measurements.
As
sho
wn
in
Figure
6,
the
circuit
with
series
damping
element
has
better
in
v
erter
input
currents
com-
pared
to
the
circuit
without
damping
element
and
the
circuit
with
parallel
damping
element.
F
or
the
load
impedance
abo
v
e
50
,
the
circuit
without
damping
element
has
the
best
in
v
erter
output
currents.
The
almost
similar
v
alues
are
presented
for
the
load
impedance
belo
w
50
.
F
or
the
load
impedance
belo
w
5k
,
the
out
p
ut
current
of
the
filter
without
damping
element
has
the
highest
current
v
alues.
The
almost
similar
filter
output
current
are
presented
for
the
load
impedance
abo
v
e
5k
.
5.1.3.
P
o
wer
Measur
ements
Figure
7a
sho
ws
the
po
wer
measurements
at
the
in
v
erter’
s
and
filter’
s
input-output
points.
Each
figure
presents
three
po
wer
curv
es
comparisons
between
the
in
v
erter+filter
circuits
without
damping,
with
series
damping
and
with
parallel
damping
for
dif
ferent
resistance
loads,
i.e.
from
10
0
until
10
5
.
At
the
upper
part
of
the
figure,
the
po
wer
measurements
at
the
in
v
erter’
s
input
terminal
are
presented.
At
the
middle
part
of
the
figure,
the
curv
es
present
the
po
wer
measurements
at
the
in
v
erter’
s
output
terminal.
At
the
bottom
part
of
the
figure,
the
po
wer
measurements
at
the
filter’
s
output
terminal
are
presented.
Side
Ef
fects
of
Damping
Element
Insertion
in
LCL
...
(F
aizal
Arya
Samman)
Evaluation Warning : The document was created with Spire.PDF for Python.
452
ISSN:
2088-8694
10
0
10
1
10
2
10
3
10
4
10
5
0
20
40
60
Inverter Pin (W)
LCL without Damping
LCL with Series Damping
LCL with Parallel Damping
10
0
10
1
10
2
10
3
10
4
10
5
0
10
20
30
Inverter Pout (W)
LCL without Damping
LCL with Series Damping
LCL with Parallel Damping
10
0
10
1
10
2
10
3
10
4
10
5
0
10
20
30
Resistive Load (Ohm)
Filter Pout (W)
LCL without Damping
LCL with Series Damping
LCL with Parallel Damping
(a)
Po
wer
output
measurements
10
0
10
1
10
2
10
3
10
4
10
5
0
50
100
Efficiency 1 (%)
LCL without Damping
LCL with Series Damping
LCL with Parallel Damping
10
0
10
1
10
2
10
3
10
4
10
5
0
50
100
Efficiency 2 (%)
LCL without Damping
LCL with Series Damping
LCL with Parallel Damping
10
0
10
1
10
2
10
3
10
4
10
5
0
50
100
Resistive Load (Ohm)
Efficiency 3 (%)
LCL without Damping
LCL with Series Damping
LCL with Parallel Damping
(b)
Po
wer
ef
ficienc
y
measurements
Figure
7.
The
po
wer
output
and
po
wer
ef
ficient
measurements.
The
in
v
erter
input
po
wer
v
alues
of
the
circuit
without
damping
element
are
higher
than
the
in
v
erter
input
po
wer
of
the
circuit
with
damping
elements
for
all
load
impedance
v
alue.
F
or
the
load
impedance
belo
w
2k
,
the
in
v
erter
output
po
wer
v
alues
of
the
circuit
without
damping
element
are
higher
than
the
other
config-
urations.
Ho
we
v
er
,
for
the
load
impedance
v
alues
abo
v
e
2k
,
the
series
damping
element
circuit
configuration
presents
the
highest
in
v
erter
output
po
wer
v
alues.
The
filter
without
damping
element
has
the
higher
output
po
wer
compared
to
the
other
circuits
with
damping
elements.
5.1.4.
P
o
wer
Efficiency
Measur
ements
The
ef
ficienc
y
curv
es
for
the
in
v
erter
and
the
filter
are
presented
in
Figure
7b.
Each
figure
presents
three
ef
ficienc
y
curv
es
comparisons
between
the
in
v
erter+filter
circuits
wit
hout
damping,
with
series
damping
and
with
parallel
damping
for
dif
ferent
resistance
loads,
i.e.
from
10
0
until
10
5
.
Ef
ficienc
y
1
is
the
po
wer
ef
ficienc
y
of
the
in
v
erter
output
po
wer
o
v
er
t
h
e
in
v
erter
input
po
wer
,
as
presented
in
the
upper
part
of
the
Figure
7b.
In
this
case,
the
filters
with
damping
elements
ha
v
e
the
highest
po
wer
ef
ficienc
y
compared
to
the
po
wer
ef
ficienc
y
of
the
filter
without
damping
element
for
the
load
impedance
v
alues
about
80
.
F
or
the
load
impedance
v
alues
belo
w
80
,
po
wer
ef
ficienc
y
v
alues
of
the
circuit
without
damping
element
are
alm
ost
the
same
as
the
v
alues
of
the
circuit
with
series
damping
eleme
nt,
b
ut
higher
than
the
v
alues
of
the
circuit
with
parallel
damping
element.
Ef
ficienc
y
2
is
the
po
wer
ef
ficienc
y
of
the
filter
output
po
wer
o
v
er
the
in
v
erter
output
po
wer
,
as
pre-
sented
in
the
middle
part
of
the
Figure
7b.
In
this
case,
the
po
wer
ef
ficienc
y
of
the
circuit
without
damping
element
is
higher
than
the
circuits
with
series
and
parallel
damping
elements
for
all
load
impedance
v
alues.
Ef
ficienc
y
3
is
the
po
wer
ef
ficienc
y
of
the
filter
output
po
wer
o
v
er
the
in
v
erter
input
po
wer
,
as
presented
in
the
bottom
part
of
the
Figure
7b.
In
this
case,
the
po
wer
ef
ficienc
y
of
the
circuit
without
damping
element
is
higer
than
the
circuits
with
series
and
damping
elements.
The
highest
po
wer
ef
ficienc
y
is
sho
wn
to
be
around
10
until
100
.
5.2.
T
ransient
Analysis
In
this
subsection,
the
transient
responses
of
the
in
v
erter’
s
output
v
oltage,
current,
po
wer
and
a
v
erage
po
wer
are
presented.
The
transient
responses
for
the
three
filter
configura
tion,
i.e.
without
damping,
with
parallel
and
series
damping
are
presented
and
compared
directly
.
Figure
8
sho
ws
the
transient
response
curv
es,
from
upper
until
lo
wer
part
of
the
figure,
respecti
v
ely
for
the
output
v
oltage
the
output
current,
output
po
wer
and
the
a
v
erage
output
po
wer
of
the
filter
circuit
without
damper
and
with
damper
element.
The
load
impedance
is
set
to
500
for
both
simulations.
As
presented
in
IJPEDS
V
ol.
9,
No.
1,
March
2018:
443
–
456
Evaluation Warning : The document was created with Spire.PDF for Python.