Internati
o
nal
Journal of P
o
wer Elect
roni
cs an
d
Drive
S
y
ste
m
(I
JPE
D
S)
V
o
l. 5,
N
o
.
1
,
Ju
ly 20
14
, pp
. 63
~70
I
S
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: 208
8-8
6
9
4
63
Jo
urn
a
l
h
o
me
pa
ge
: h
ttp
://iaesjo
u
r
na
l.com/
o
n
lin
e/ind
e
x.ph
p
/
IJPEDS
A New Multilevel Inverter with
Reduced Number of
Switches
Gnana Pra
k
a
s
h M, B
a
la
muruga
n
M
,
U
m
asha
nka
r
S
School of
Electr
i
cal Engin
eer
ing,
VIT University
,
Vellore, Ind
i
a
Article Info
A
B
STRAC
T
Article histo
r
y:
Received Apr 10, 2014
Rev
i
sed
May 15
, 20
14
Accepted
May 27, 2014
In rec
e
nt
da
y’s
Multilev
e
l
inver
t
er (MLI)
t
echn
o
logies b
ecom
e
a in
cred
i
b
l
y
main choice in
the area of high power
medi
um voltage energ
y
contro
l.
Though m
u
ltilev
e
l inver
t
er has a num
ber of
advantages it has drawbacks in
the vein of high
er leve
ls becaus
e
of using m
o
re
num
ber of
semiconduc
tor
switc
he
s.
This may
le
a
d
s to va
st s
i
z
e
a
nd
pr
ice of
the inv
e
rter
is v
e
r
y
h
i
gh. So
in order to
over
c
om
e this probl
em
the new m
u
ltil
evel
inver
t
er
is proposed
with reduced nu
mber of switches. Th
e proposed method is
well suited for a
high
power appl
ica
tion and it
bu
ilt
wi
th
three
Dc
sources
and six
Switches
.
Multi carr
i
er pw
m
technique is u
s
ed for sine wave gener
a
tion
.
Th
e results ar
e
valid
ated throu
gh the harmonic spectrum of the FFT window by
usin
g
Matlab/simulink
.
The result of
the proposed MLI is compared with the
conventional MLI and
oth
e
r se
v
e
n level ex
isting
topologies
.
Keyword:
FFT
MLI
Multilev
e
l
inver
t
er
PW
M
THD
Copyright ©
201
4 Institut
e
o
f
Ad
vanced
Engin
eer
ing and S
c
i
e
nce.
All rights re
se
rve
d
.
Co
rresp
ond
i
ng
Autho
r
:
G
n
an
a
P
r
ak
a
s
h
M,
Sch
ool
o
f
El
ec
t
r
i
cal
En
gi
neer
i
ng,
VIT Un
iv
ersity,
V
e
llo
r
e
632
014
,
In
d
i
a.
Em
a
il: g
n
a
n
a
gst@g
m
ail.co
m
1.
INTRODUCTION
In
rece
nt
day
s
M
L
I
has
dra
w
n
l
a
rg
e i
n
t
e
r
e
st
i
n
hi
gh
pow
er
i
n
du
str
y
.
Th
ey
p
r
esen
t
a latest set of
aspects to facil
itate and
utilized in reactive
powe
r c
o
m
p
ensation
[3]. The
unique a
rra
nge
m
ent of m
u
lti
level
vol
t
a
ge s
o
urce
i
nvert
er
s al
l
o
w t
h
em
t
o
achi
e
ve hi
gh
vol
t
a
ges wi
t
h
t
h
e
l
o
w harm
oni
cs not
i
n
cl
u
d
i
ng t
h
e
u
tilizatio
n
of tran
sform
e
rs o
r
series co
nn
ect
ed
synchron
ized switch
i
n
g
d
e
v
i
ces [9
].
The
Diode cla
m
ped, Flying
capacitor, Cas
caded H-
br
idge in
v
e
r
t
er
ar
e th
e three m
a
in different
m
u
l
tilev
e
l in
v
e
rter stru
ctures wh
ich
are u
s
ed
in
i
n
du
stri
al ap
p
licatio
n
s
with
sep
a
rate
d
c
so
urces.
In flyin
g
capacitor a
n
d
diode-clam
ped inve
rter the
r
e
is a proble
m
o
f
cap
acitor
v
o
l
tag
e
b
a
lan
c
ing an
d th
is pro
b
l
e
m
is
ove
rc
om
e i
n
cascade
d
H-
bri
d
g
e
i
nve
rt
er
[
4
]
-
[
7
]
.
C
o
n
v
e
n
t
i
onal
c
a
scade
d
seve
n l
e
vel
m
u
l
t
i
l
e
vel
i
nvert
er re
qui
re t
w
el
ve swi
t
ches an
d t
h
ree
dc so
urces
sep
a
rately [8
]. Th
e m
a
in
d
r
awb
a
ck
in Conv
en
tion
a
l cas
c
a
ded is t
h
at when le
vels are
increasing it requi
res
m
o
re num
ber of sem
i
cond
uc
t
o
r s
w
i
t
c
hes.
A
s
a resul
t
s
o
m
e
altern
atio
ns are to
b
e
m
a
d
e
in
ord
e
r to
red
u
ce th
e
si
ze and s
w
i
t
c
h o
f
t
h
e i
n
ve
rt
er. T
h
e ne
xt
t
o
pol
ogy
i
s
m
a
de wi
t
h
t
h
r
ee so
urces a
n
d ni
ne
swi
t
c
hes a
nd i
t
y
i
el
ds
th
e stair case
wav
e
fo
rm
wit
h
th
e redu
ced to
tal h
a
r
m
o
n
i
c d
i
sto
r
tion
com
p
ared
to
co
nv
en
tion
a
l m
u
lt
ilev
e
l
inve
rter [1]
.
The
n
t
h
e
next
t
o
p
o
l
o
gy
i
s
fu
r
t
her re
duce
d
f
o
r
t
w
o
switch
e
s th
en
it co
n
s
ists
of
three dc s
o
urces and
seve
n swi
t
c
hes
whe
r
e t
h
e
ha
rm
oni
cs are re
duce
d
[
2
]
.
A
g
ai
n t
h
e seve
n
l
e
vel
i
nve
rt
er
i
s
red
u
ced
wi
t
h
o
n
e
switch
bu
t it al
so
lead
s to
in
crease in
o
n
e
of th
e d
c
sou
r
cesso
th
e to
po
log
y
is
m
a
d
e
o
f
fo
ur d
c
sou
r
ces and
six
swi
t
c
hes
[6]
.
B
u
t
i
n
creas
e i
n
one
dc s
o
urcei
s co
nsi
d
e
r
es as
one
o
f
t
h
e
dra
w
bac
k
of t
h
i
s
ci
rcui
t
.
B
y
ana
l
y
s
i
ng
t
h
e ad
va
nt
ages
and
d
r
aw
bac
k
s of
t
h
e e
x
i
s
t
i
n
g t
o
pol
o
g
i
e
s. T
h
e n
e
w t
o
p
o
l
o
gy
i
s
p
r
o
p
o
sed
and
di
sc
usse
d i
n
t
h
i
s
p
a
p
e
r
wh
ich
ov
er
co
m
e
s th
e dr
awb
a
ck
s
o
f
the ex
isting
topolo
g
i
es.
The
pr
op
ose
d
t
o
p
o
l
o
gy
i
s
de
si
gne
d wi
t
h
t
h
ree dc s
o
urces
and si
x swi
t
c
hes an
d al
s
o
i
t
consi
s
t
s
of
som
e
addi
t
i
ona
l
feat
u
r
es l
i
k
e
m
i
nim
u
m
num
ber
o
f
s
w
i
t
c
hes
co
n
duct
i
n
g at
a speci
fi
c i
n
t
e
r
v
al
of t
i
m
e, Fu
rt
he
r
t
h
e
m
u
l
t
i
carri
er pwm
m
e
t
hod [5]
.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
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:
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94
I
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Vo
l. 5
,
No
. 1
,
Ju
ly 20
14
:
63
–
70
64
2.
E
X
ISTING T
O
POLOGIES
2
.
1
.
Sev
e
n Lev
e
l
Nine Swit
ch
MLI To
po
logy
Thi
s
t
o
pol
o
g
y
i
s
desi
g
n
ed
wi
t
h
fi
ve s
w
i
t
c
hes
and
t
h
ree
dc s
o
u
r
ces al
on
g
w
i
t
h
on
e H
-
b
r
i
d
ge co
nsi
s
t
s
o
f
fou
r
switch
e
s wh
ich
is u
s
ed
for po
larity rev
e
rsal
to produce three
posit
ive a
nd three negative and one zero
v
o
ltag
e
lev
e
l
w
h
ich
is sh
own
in
Figu
r
e
1
.
Th
e sw
itch
i
ng
p
a
tter
n
of
th
e
sev
e
n
lev
e
l
n
i
n
e
sw
itch
topolo
g
y
is
sho
w
n i
n
Ta
bl
e 1.
Fi
gu
re
1.
C
o
nfi
g
u
r
at
i
o
n
of
sev
e
n l
e
vel
ni
ne s
w
i
t
c
h T
o
pol
og
y
Tab
l
e 1
.
Switch
i
ng
Pattern
for
sev
e
n
lev
e
ls n
i
n
e
switch
topo
log
y
S.No
Switches state
S1 S2 S7 S8
S9
Output voltage
1
Of
f On
On Of
f
On
Vdc
2
Of
f On Of
f On On
2Vdc
3
On Of
f
Of
f On On
3Vdc
2.
2.
Seven
L
e
vel
S
e
ven Sw
i
t
ch ML
I
T
o
p
o
l
o
g
y
Seve
n Le
vel
S
e
ven
S
w
i
t
c
h i
s
desi
gne
d
wi
t
h
o
n
e
H-
bri
dge
i
nve
rt
er al
on
g
wi
t
h
t
h
ree
sw
i
t
c
hes a
n
d
t
h
ree
dc s
o
urce
s has
sh
o
w
n i
n
Fi
g
u
re
2.
Swi
t
ches S
1
,
S
2
, S
3
,
S4 a
r
e
use
d
fo
r
pol
ari
t
y
re
v
e
rsal
f
o
r
ge
ner
a
t
i
n
g
th
e wav
e
form
s
in
p
o
s
itiv
e and
n
e
g
a
tiv
e cycles. Switch
e
s S5
, S6
, S7
are
used
fo
r g
e
n
e
ratin
g
th
e vo
ltag
e
lev
e
ls
upt
o
3V
dc.
T
h
e swi
t
c
hi
ng
co
nfi
g
u
r
at
i
o
n
o
f
t
h
i
s
t
o
p
o
l
o
gy
i
s
sho
w
n i
n
Ta
bl
e 2.
Fi
gu
re
2.
C
o
nfi
g
u
r
at
i
o
n
of
sev
e
n l
e
vel
se
ven
swi
t
c
h T
o
p
o
l
ogy
Evaluation Warning : The document was created with Spire.PDF for Python.
I
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8-8
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4
A New Multilevel Inverter with Re
duced Nu
mber of
Switches (Gnana Prakash M)
65
Tab
l
e 2
.
Switch
i
ng
Pattern
for
sev
e
n
lev
e
ls n
i
n
e
switch
topo
log
y
S.No
S
w
itch
e
s
state
S5 S6 S7
Output voltage
1 Of
f
On
On
Vdc
2
Of
f On Of
f
2Vdc
3 On
Of
f
Of
f
3Vdc
2.
3.
Seven
l
e
vel
si
x
sw
i
t
ch w
i
th
f
o
ur
dc s
o
urce
s ML
I
To
po
l
o
g
y
Thi
s
st
r
u
ct
ure i
s
desi
gne
d
wi
t
h
si
x s
w
i
t
c
hes
wi
t
h
o
u
t
H-
bri
d
ge a
n
d
f
o
ur
dc
so
urce
s i
s
use
d
.
Swi
t
c
he
s
S6
. S7
are used
for
g
e
n
e
rating
th
e pu
lses i
n
p
o
s
itiv
e an
d
n
e
g
a
tiv
e sequ
en
ces and
th
e switch
S1
is con
n
e
cted
to
th
e lo
ad
it is used
o
n
l
y
wh
en all th
e switches are
op
en
t
o
pr
o
duce
zer
o
v
o
l
t
a
ge l
e
vel
.
S
w
i
t
c
h S
2
,
S
3
,
S4 a
r
e
u
s
ed
to
g
e
n
e
rate th
e lev
e
ls
Vd
c, 2Vd
c
and
3Vd
c
in
bo
th
th
e
po
sitiv
e
an
d
t
h
e
n
e
g
a
ti
v
e
lev
e
ls. Th
e circu
it
arra
ngem
e
nt
i
s
sh
ow
n i
n
Fi
g
u
r
e
3. T
h
e
swi
t
c
hi
n
g
t
o
p
o
l
o
gy
of
seve
n l
e
vel
si
x s
w
i
t
c
hes i
s
sho
w
n i
n
Ta
bl
e 3.
Fi
gu
re
3.
C
o
nfi
g
u
r
at
i
o
n
of
7 l
e
vel
6
s
w
i
t
c
h T
o
p
o
l
o
gy
Tabl
e
3.
Swi
t
c
hi
n
g
Pat
t
e
r
n
fo
r se
ven
l
e
vel
si
x s
w
i
t
c
h t
o
p
o
l
ogy
S.No
S
w
itch
e
s state
S1 S2 S3 S4 S5 S6
Output
voltage
1
Of
f Of
f Of
f
On
On
Of
f
Vdc
2
Of
f
Of
f On Of
f On Of
f
2Vdc
3
Of
f On Of
f
Of
f On Of
f
3Vdc
4
On
Of
f Of
f Of
f Of
f Of
f
0
5
Of
f On Of
f
Of
f
Of
f On
-Vdc
6
Of
f
Of
f On Of
f
Of
f On
-2Vdc
7
Of
f
Of
f
Of
f On Of
f On
-3Vdc
3.
PROP
OSE
D
TOPOLOG
Y
Th
e pro
p
o
s
ed
to
po
log
y
is sim
p
le
in
d
e
sign an
d
co
m
p
ared to
th
e ex
isting
top
o
l
o
g
i
es, it co
n
s
ists of
th
ree
d
c
sou
r
ces and
si
x
switch
e
s.
It also
hav
e
ad
d
ition
a
l
featu
r
es lik
e
on
ly two switches con
d
u
c
ting
at an
in
terv
al
o
f
time. Two
switches u
s
ed
for
p
o
l
arity rev
e
rs
al an
d th
e
r
e
m
a
in
i
n
g fo
ur
sw
itches u
s
ed
f
o
r
wav
e
fo
r
m
gene
rat
i
o
n.
The gene
ralized expression for the num
b
er of sw
i
t
c
he
s
and t
h
e n
u
m
b
er
of
dc s
o
u
r
ces f
o
r t
h
e
pr
o
pose
d
t
o
p
o
l
ogy
i
s
gi
ven
by
:
N= (
2
*V
–
5
)
Whe
r
e
N=
n
u
m
ber of l
e
vel
s
and
V=
n
u
m
b
er
of s
w
i
t
c
hes
.
N =
(2*S +
1)
Whe
r
e S=n
u
m
b
er
o
f
dc vol
t
a
ge
s
o
urces
.
Fi
gu
re 4 sh
o
w
s t
h
e ci
rcui
t
arr
a
ngem
e
nt
of p
r
op
ose
d
t
o
p
o
l
o
gy
whi
c
h co
nsi
s
t
s
of si
x swi
t
c
hes an
d t
h
e
resistiv
e lo
ad
is u
s
ed. Switches S4
&S6
are
u
s
ed
for re
vers
al polarity and the re
m
a
in
in
g switch
e
s are used
to
g
e
n
e
rate th
e lev
e
ls in
bo
th
po
sitiv
e and
n
e
g
a
tiv
e sid
e
s t
o
p
r
o
d
u
ce th
e
desired
sev
e
n
lev
e
l wav
e
fo
rm
s. Th
e
switch
i
ng
sequen
ce is
d
i
sp
lay
e
d
in Tab
l
e 4.
Evaluation Warning : The document was created with Spire.PDF for Python.
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S
Vo
l. 5
,
No
. 1
,
Ju
ly 20
14
:
63
–
70
66
Fi
gu
re 4.
C
o
nfi
g
u
r
at
i
o
n of sev
e
n
l
e
vel
si
x
s
w
i
t
c
h
Pr
o
pose
d
To
pol
ogy
Tabl
e
4.
Swi
t
c
hi
n
g
Pat
t
e
r
n
fo
r se
ven
l
e
vel
si
x s
w
i
t
c
h t
o
p
o
l
ogy
S.No
S
w
itch
e
s state
S1 S2 S3 S4 S5 S6
Output
voltage
1
Of
f On Of
f
Of
f
Of
f On
Vdc
2
On
Of
f Of
f Of
f Of
f
On
2Vdc
3
Of
f
Of
f On Of
f
Of
f On
3Vdc
4
Of
f Of
f Of
f Of
f Of
f Of
f
0
5
On Of
f
Of
f On Of
f
Of
f
-Vdc
6
Of
f On Of
f On Of
f
Of
f
-2Vdc
7
Of
f Of
f Of
f
On
On
Of
f
-3Vdc
4.
PWM TECHNIQUES
The m
odul
at
i
o
n t
echni
que
us
ed i
n
t
h
i
s
pape
r i
s
l
e
vel
shi
f
t
e
d m
odul
at
i
on.
Phase s
h
i
f
t
e
d
m
odul
at
i
on i
s
not
use
d
beca
use i
t
gene
rat
e
s m
o
re ha
rm
oni
cs.
In
l
e
vel
s
h
i
f
t
e
d
m
odul
at
i
on t
h
ere
are
f
o
u
r
t
e
c
hni
ques
p
h
ase
d
i
spo
s
itio
n, phase o
p
p
o
sitio
n
d
i
spo
s
itio
n, altern
ativ
e
p
h
a
se
o
ppo
sitio
n
d
i
sp
o
s
ition
,
inv
e
rt
ed
ph
ase d
i
spositio
n
.
Out
o
f
t
h
ese
f
o
ur
t
w
o t
ech
ni
q
u
es a
r
e
di
scus
s
e
d
here
.
4.
1. Al
ter
n
a
t
i
v
e
Ph
ase opp
o
s
i
ti
on Di
sp
osi
t
i
o
n (A
PO
D)
Every
ca
rri
e
r
(t
ri
an
gul
a
r)
w
a
vef
o
rm
s i
s
i
nve
rt
ed
wi
t
h
t
h
e ne
xt
t
r
i
a
n
gul
a
r
w
a
ve
fo
r
m
and i
t
i
s
in
tersected wit
h
th
e sinu
so
id
al wav
e
fo
rm
.
The a
b
o
v
e e
x
pl
a
n
at
i
o
n
i
s
di
ag
r
a
m
m
at
i
cal
ly
show
n i
n
fi
g
u
re
5.
Fig
u
re
5
.
Altern
ativ
e Ph
as
e op
po
sition
d
i
spositio
n
PWM
4.
2.
In
ver
t
ed
Ph
ase
Di
spo
s
i
t
i
o
n
(IP
D
)
Al
l
t
h
e si
x t
r
i
a
ng
ul
ar
wa
ve f
o
rm
s are i
nvert
e
d
a
nd i
t
is in
tersected
with th
e sin
u
s
o
i
d
a
l wav
e
form
i
t
is
sho
w
n i
n
Fi
gu
r
e
6.
Whe
n
t
h
e
si
n
u
s
oi
dal
wave i
s
hi
g
h
er t
h
an al
l
t
h
e 6 ca
rri
er
wave
f
o
rm
s pul
ses are g
e
ne
rat
e
d i
n
up
pe
r
sequ
en
ce and
t
h
e sinu
so
id
al sig
n
a
l is lower th
an all th
e
6 c
a
rri
er
wa
vef
o
rm
s p
u
l
s
es are
ge
nerat
e
d i
n
t
h
e l
o
we
r
sequence
. Ze
ro level is
produced
when the
s
i
nus
oidal
sign
al is lesser t
h
an
lo
wer carrier wav
e
s and
it is
big
g
e
r
than highe
r
ca
rrier wave
form
s.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
PED
S
I
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208
8-8
6
9
4
A New Multilevel Inverter with Re
duced Nu
mber of
Switches (Gnana Prakash M)
67
Fig
u
re
6
.
In
v
e
rted
Ph
ase
Op
po
sitio
n
d
i
spo
s
i
tio
n
PWM
5.
SIMULATION RESULTS
Th
e sim
u
lat
i
o
n
d
i
ag
ram
o
f
th
e p
r
opo
sed
in
verter is sh
own
in
Fig
u
re 7
.
All th
e switch
e
s u
s
ed
in
th
is
ci
rcui
t
are M
O
SFET.
T
h
e s
w
i
t
c
hes S
4
a
n
d S
6
a
r
e
bi
di
rect
i
o
nal
an
d t
h
e
re
m
a
i
n
i
ng s
w
i
t
c
hes a
r
e
uni
di
re
ct
i
onal
and t
h
e resi
st
i
v
e l
o
a
d
i
s
t
a
ken as 1
0
o
h
m
s
.The dc s
o
urce
vol
t
a
ge i
s
t
a
ken as
10
V.
The ci
rc
ui
t
us
ed f
o
r
gene
rat
i
n
g t
h
e
pul
ses
i
s
s
h
o
w
n i
n
Fi
g
u
r
e
7.
Fi
gu
re
7.
Si
m
u
l
a
t
i
on di
a
g
ram
fo
r P
r
o
p
o
se
d
7
Level
M
L
I
The ci
rcui
t
i
s
desi
gne
d i
n
M
a
t
l
a
b/
sim
u
l
i
nk an
d t
h
e ge
nerat
i
o
n o
f
p
u
l
s
es has bee
n
m
a
de by
com
p
aring e
v
e
r
y carrie
r
wa
ve with the si
ne
wave
and th
e
resultant
pulses has
been gi
ven to t
h
e appropriate
swi
t
c
hes t
o
pr
od
uce t
h
e s
e
v
e
n l
e
vel
st
ai
rc
ase wav
e
f
o
rm
. The wa
ve
fo
r
m
s of t
h
e
vol
t
a
ge an
d t
h
e c
u
r
r
ent
i
s
sho
w
n i
n
Fi
g
u
r
e 9. Fi
gu
re 8
sho
w
s
ho
w t
h
e
pul
ses are
ge
nerat
e
d an
d t
h
e app
r
o
p
ri
at
e
pul
ses i
s
gi
ven
t
o
t
h
e
respective swit
ches.Here
t
h
e
swi
t
c
h S
2
ha
s
been
gi
ve
n
wi
t
h
t
h
e
pul
ses
of
+Vdc a
n
d -
2
V
d
c an
d t
h
e s
w
i
t
ch S
1
req
u
i
r
es
2
V
dc and
–
V
dc
a
n
d t
h
e
s
w
i
t
c
h
S
3
need
s 3V
dc
a
n
d
t
h
e
s
w
i
t
c
h S
5
need
s -3
V
d
c.
Swi
t
c
h
e
s
S
6
r
e
qui
res
p
o
s
itiv
e
p
o
l
arit
y an
d
th
e switch
s4
n
e
ed
s
n
e
gativ
e p
o
l
arity
an
d
th
e
b
a
sic log
i
c g
a
tes lik
e AND,
OR, NOT are
use
d
f
o
r c
o
m
p
ari
n
g t
h
e
car
ri
er si
g
n
al
s t
o
pr
o
duce
t
h
e
desi
r
e
d l
e
vel
s
f
o
r
t
h
e
swi
t
c
hes
.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
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:
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-86
94
I
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PED
S
Vo
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,
No
. 1
,
Ju
ly 20
14
:
63
–
70
68
Fi
gu
re
8.
P
u
l
s
e ge
nerat
i
o
n ci
r
c
ui
t
f
o
r
Pr
o
pos
ed Se
ve
n l
e
vel
M
L
I
Fi
gu
re
9.
O
u
pu
t
Vol
t
a
ge
an
d
C
u
r
r
ent
Wa
vef
o
rm
of
p
r
o
p
o
se
d M
L
I
The t
o
t
a
l
ha
rm
oni
c
di
st
ort
i
o
n
of
AP
OD
, I
P
D P
W
M
sche
m
e
i
s
vi
ew t
h
r
o
u
g
h
t
h
e F
F
T
wi
n
d
o
w
a
nd i
t
sho
w
n bel
o
w
.
The com
p
ari
s
o
n
t
a
bl
e has
bee
n
creat
ed
fo
r t
o
t
a
l
harm
oni
c di
st
ort
i
o
n a
nd
t
h
e v
o
l
t
a
ge st
r
e
ss t
o
sh
ow
t
h
at th
e pr
opo
sed top
o
l
og
y is
b
e
tter
wh
en c
o
m
p
ared t
o
the
existing t
o
pologies.
Fig
u
r
e
10
.
FFT An
alysis of
p
r
o
p
o
s
ed
t
o
po
logy u
s
ing
A
P
O
D
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
PED
S
I
S
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:
208
8-8
6
9
4
A New Multilevel Inverter with Re
duced Nu
mber of
Switches (Gnana Prakash M)
69
Fig
u
r
e
11
.
FFT An
alysis of
p
r
o
p
o
s
ed
t
o
po
logy u
s
ing
I
P
D
Tabl
e 5.
C
o
m
p
ari
s
o
n
of
TH
D C
ont
e
n
t
PWM
T
echnique
Sy
mm
et
ric
conventio
nal cascaded
7level MLI
(%
)
Asy
m
m
e
t
r
ic
conventio
nal cascaded
7level MLI
(%
)
7level
9
switch
(%)
MLI
7
l
ev
el,
7switch
(%)
MLI
7level,
6switch
(%)
MLI
7level,
5switch
(%)M
LI
Pr
oposed 6
switch 7level
(%) ML
I
APOD 22.
46
19.
42
-
-
18.
52
18.
4
18.
18
IPD
-
-
-
-
-
-
1
7
.
9
9
Tabl
e
6. C
o
m
p
ari
s
o
n
of
V
o
l
t
a
ge St
ress ac
ro
s
s
Swi
t
c
hes
Par
a
m
e
ter Conventio
nal
CM
L
I
9switches 7level
MLI
7switches7level
MLI
6switches
7level
MLI
5switches 7level
MLI
Pr
oposed
T
opology
6switches 7level
MLI
Voltage
Stress
5V 11V(
S
5)
6V(
S
3)
3.
33V(
S
3)
3.
33V(
S
3)
2V(
S
3&
S1)
(all switches
)
10V(
S
6)
6V(
S
2)
13.
3V(
S
2)
13.
3V(
S
2)
19V(
S
5)
2V(
S
7)
10V(
S
8&
S9)
18V(
S
1)
23.
3V(
S
1)
23.
3V(
S
1)
9V(
S
6)
Tabl
e
7. C
o
m
p
ari
s
o
n
of
t
h
e c
o
m
pone
nt
s
of
pr
o
pose
d
m
u
l
t
i
l
e
vel
i
n
v
e
rt
er
wi
t
h
t
h
e
exi
s
t
i
ng
t
o
p
o
l
o
gi
es
In-built
structure
Fly
i
ng
capacitor
Diode clam
ped
Cascaded
7level
7level,
9switch
7level,
7switc
h
7level,
6switch
7level,
5switch
Pr
oposed
7level,
6switch
Nu
m
b
e
r
of
capacitor
1
4
6
-
-
-
-
-
-
Nu
m
b
e
r
of dio
d
es
- >=8
-
-
-
-
-
-
Nu
m
b
e
r
of
switches
10
10
12
9
7
6
5
6
Nu
m
b
e
r
of
dc sour
ces
-
-
3
3
3
4
4
3
6.
CO
NCL
USI
O
N
A
n
e
w top
o
l
o
gy for sev
e
n
level
m
u
ltilev
e
l in
v
e
rter is
p
r
op
osed
i
n
th
is p
a
per an
d th
e
simu
latio
n
s
are
d
o
n
e
i
n
Matlab/si
m
u
lin
k
.
Th
e sim
u
lat
i
o
n
resu
lts are m
a
tc
h
e
d
with
th
e conv
en
tion
a
l sev
e
n
lev
e
l i
n
v
e
rter with
the reduction in THD. And the inverte
d
pha
se
opposition
disposition
m
e
thod produce re
duction
in the
h
a
rm
o
n
i
c
d
i
stortio
n co
m
p
ared to
th
e conv
en
tio
n
a
l topo
log
i
es.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
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,
No
. 1
,
Ju
ly 20
14
:
63
–
70
70
REFERE
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BIOGRAP
HI
ES
OF AUTH
ORS
Gnana P
r
akas
h.
M
was born in
Vello
re, Tamiln
adu. Currently
h
e
is
pursuing Master’s Degree in
P
o
wer Ele
c
troni
cs
at VIT
Univer
s
i
t
y
, Vel
l
ore
.
He
rec
e
ived
his
Ba
chelor
Degre
e
in
Ele
c
tr
ica
l
an
d
Electronics Eng
i
neer
ing in th
e
y
e
ar 2005 at
C.Abdul Hakeem college of
Engineer
ing and
Techno
log
y
aff
ilia
ted to Anna
Universit
y
, C
h
ennai
.
His research
inter
e
sts are c
a
scad
ed
m
u
ltileve
l Inv
e
rt
er, Power
El
ec
tr
onics Appli
cat
io
n in Driv
es and
Ele
c
tri
cal
m
achi
n
es.
Balamurugan.M
was born in Vellore, Tamiln
adu
.
Currently
he is
pursuing Master’s Degree in
P
o
wer Ele
c
troni
cs
at VIT
Univer
s
i
t
y
, Vel
l
ore
.
He
rec
e
ived
his
Ba
chelor
Degre
e
in
Ele
c
tr
ica
l
an
d
Electronics Eng
i
neer
ing in th
e
y
e
ar 2012 at
C.Abdul Hakeem college of
Engineer
ing and
Techno
log
y
aff
ilia
ted to Anna
Universit
y
, C
h
ennai
.
His research
inter
e
sts are c
a
scad
ed
m
u
ltileve
l Inv
e
rt
er, Power
El
ec
tr
onics app
lic
ation
in R
e
newab
l
e
e
n
erg
y
s
y
s
t
em
s.
Um
as
hankar.S
rece
ived B
.
E. D
e
gree
in El
ec
tri
cal
and El
ec
tro
n
ics
Engin
eerin
g from
Govt.
College of Tech
nolog
y
,
Coimbatore in the
y
ear
2
001 and M. Tech., Degree and PhD in
Power
Electronics from VIT University
, Vellor
e
in
the
y
ear 2004
and 20
13 respectively
.
Currently
he
is
working as Associate Professor in the School
of
Electrical
En
gineer
ing at VI
T University
,
Vellore.
He worked as Asst.
Professor-Senior,
Senior R&D En
gineer
and Senior Application
Engine
er in the
power elec
troni
c
s
, renewabl
e En
erg
y
and ele
c
tri
c
al drives
fie
l
d for m
o
re than 10
ye
ars
.
He has
been one of the
Editori
al Board
m
e
m
b
ers in Internation
a
l journa
l
of electron
i
cs,
communication
and electrical e
ngineer
ing and reviewer in r
e
p
u
ted journal publications lik
e
Elsevier,
IEEE
and IET. He ha
s published/pr
esented
78 pap
e
rs
in n
a
tion
a
l
and
inte
rnat
ional
journals/conferences. He
also co
-authored
/co-
edit
ed 9 books/ch
a
pters and 9
tech
nical articles on
power el
ec
troni
cs
appl
ica
tions
in ren
e
wabl
e e
n
erg
y
and
al
li
e
d
are
a
s
.
His
cu
rrent
are
a
s
of
res
earch
a
c
tiv
iti
es
includ
e powe
r
el
ectron
i
cs
ap
plic
ations
in
wi
nd and s
o
lar
en
erg
y
,
ele
c
tr
ica
l
drives
and
con
t
r
o
l, s
m
art
grid
an
d power qu
ali
t
y
.
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