Inter
national
J
our
nal
of
P
o
wer
Electr
onics
and
Dri
v
e
System
(IJPEDS)
V
ol.
11,
No.
3,
Septemeber
2020,
pp.
1388
1397
ISSN:
2088-8694,
DOI:
10.11591/ijpeds.v11.i3.pp1388-1397
r
1388
Design
and
implementation
of
an
optimized
multile
v
el
po
wer
in
v
erter
structur
e
based
on
C
MEX
and
PSPICE
Mohammed
Setti,
Mohamed
Cherkaoui
Engineering
for
Smart
and
Sustainable
Systems
Research
Center
,
Mohammed
V
Uni
v
ersity
in
Rabat,
Morocco
Article
Inf
o
Article
history:
Recei
v
ed
Feb
9,
2020
Re
vised
Mar
6,
2020
Accepted
Mar
22,
2020
K
eyw
ords:
C
MEX
S-function
Multile
v
el
in
v
erter
PSPICE
Switching
frequenc
y
Symmetric/asymmetric
ABSTRA
CT
In
this
paper
,
both
symmetric
and
asymmetric
operations
for
an
optimized
cascaded
multile
v
el
po
wer
in
v
erter
(MLI)
are
thoroughly
e
xamined.
While
symmetric
configurations
are
more
suitable
for
A
C
dri
v
es
due
to
their
equal
po
wer
sharing
among
the
v
arious
le
v
els,
the
asymmetric
topologies
fulfill
the
higher
number
of
po
wer
source
combinations
under
the
same
po
wer
semiconductor
switch
count.
Additionally
,
particular
attention
w
as
put
on
the
design
of
this
optimized
topology
in
terms
of
both
reliability
and
po
wer
ef
ficienc
y
by
managing
redundant
states
and
minimizing
the
number
of
po
wer
switch
commutations.
Furthermore,
a
fundamental
switching
frequenc
y
modulat
ion
(FSFM)
is
thoroughly
described
in
C
MEX
programming
language
and
then
the
resulting
g
ating
signals
are
fed
into
the
po
wer
circuit
designed
with
PSPICE.
By
applying
this
co-simulation
approach,
the
control
design
task
is
greatly
simplified
while
achie
ving
adv
anced
analyses
with
more
realistic
electronic
de
vices.
This
is
an
open
access
article
under
the
CC
BY
-SA
license
.
Corresponding
A
uthor:
Mohammed
Setti,
Mohammadia
School
of
Engineers,
Ibn-Sina
A
v
enue,
765,
Rabat,
Morocco.
Email:
mohammedsetti@research.emi.ac.ma
1.
INTR
ODUCTION
Multile
v
el
po
wer
in
v
erters
(MLIs)
are
considered
as
one
of
the
most
ef
fecti
v
e
w
ay
to
generate
high
quality
A
C
po
wer
.
Besides
a
good
harmonic
profile
and
lo
w
electromagnetic
interferences
that
a
staircase
w
a
v
eform
can
pro
vide,
some
partial
adv
antages
related
to
design
and
reliability
are
directly
obtained
[1].
The
po
wer
semiconductor
switching
de
vices
in
use
can
w
ork
in
syner
gy
to
deli
v
er
the
desirable
po
wer
le
v
el,
which
let
each
one
of
them
participate
only
in
a
fraction
of
the
total
po
wer
magnitude.
Moreo
v
er
,
some
multile
v
el
po
wer
in
v
erter
structures
can
pro
vide
dif
ferent
switching
combinations
referred
to
as
r
edundant
states
which
can
be
useful
to
program
f
ault-tolerant
operations
[2–5]
monitored
by
switch
f
ault
diagnosis
algorithms
[6].
Despite
of
all
their
e
x
c
iting
adv
antages,
MLI
topologies
come
with
a
double-edged
sw
ord.
The
y
require
a
lar
ge
number
of
po
wer
s
emiconductor
v
alv
es
which
penalizes
both
the
o
v
erall
po
wer
system
ef
ficienc
y
and
reliability
while
meeting
b
udget
constraints
[7].
The
situation
tends
to
be
more
gloomy
with
the
introduction
of
dedicated
ICs
for
dri
ving
po
wer
switches,
so
additional
losses
should
be
e
xpected
and
the
call
for
sophisticated
controllers
becomes
ine
vitable.
F
or
a
ll
these
reasons
and
more,
se
v
eral
MLI
topologies
ha
v
e
been
de
v
eloped
to
address
these
shortcomings
by
limiting
the
number
of
their
po
wer
switching
de
vices
[8–10].
In
practice,
the
cascaded
topologies
wit
h
multiple
DC
sources
are
considered
as
one
of
the
most
authoritati
v
e
multile
v
el
topologies
currently
a
v
ail
able,
the
y
ha
v
e
been
successfully
tested
in
some
rene
w
able
J
ournal
homepage:
http://ijpeds.iaescor
e
.com
Evaluation Warning : The document was created with Spire.PDF for Python.
Int
J
Po
w
Elec
&
Dri
Syst
ISSN:
2088-8694
r
1389
ener
gy
systems
for
more
than
a
decade.
The
y
can
be
found
either
in
symmetric
or
in
asymmetric
configuration
depending
on
the
magnitude
of
their
v
oltage
sources.
Asymmetric
nature
of
DC
sources
w
ould
pro
vide
e
xtra
le
v
els
to
the
output
signals
so
as
to
enhance
their
harmonic
profile.
Ho
we
v
er
,
in
the
most
asymmetric
structures,
po
wers
deli
v
ered
by
the
v
arious
le
v
els
are
quite
di
f
ferent.
This
is
a
serious
limitation
of
such
configurations
for
applications
in
A
C
dri
v
es
[11,
12].
Due
to
their
nature,
asymmetrical
configurations
ha
v
e
unequal
po
wer
sharing;
this
doesn’
t
allo
w
the
bridges
to
be
easily
replaced
(as
the
high
and
lo
w
side
bridges
most
lik
ely
to
be
made
by
dif
ferent
po
wer
de
vices)
and
hence
lose
the
adv
an-
tage
of
modularity
[11].
Also,
it
goes
without
saying
that
the
peak
in
v
erse
v
oltage
(PIV)
is
noticeably
greater
in
asymmetric
operation.
The
ne
xt
section
deals
with
an
optimized
po
wer
in
v
erter
topology
under
asymmetric
op
e
ration.
It
has
already
been
the
subject
of
a
pre
vious
w
ork
[13],
b
ut
ne
v
ertheless,
did
neither
stress
an
y
aspect
of
po
wer
ef
ficienc
y
or
reliability
of
such
po
wer
con
v
erter
nor
try
to
address
the
issue
of
the
PIV
withstanding.
F
or
these
reasons
and
more,
this
article
w
as
fully
re
written,
better
arranged
and
thoroughly
upgraded
all
the
simulation
results.
Also,
a
ne
w
symmetric
configuration
is
proposed
on
the
basi
s
of
what
w
as
fulfilled,
where
redundant
states
in
dif
ferent
operating
modes
required
by
f
ault-tolerant
applications
are
highlighted
and
commented.
Afterw
ards,
the
po
wer
ef
ficienc
y
of
the
proposed
MLI
topology
is
e
v
aluated
and
compared
to
some
state-of-the-art
topologies.
Furthermore,
a
guide
to
co-simulating
po
wer
control
systems
using
C
programming
language
via
Simulink
MEX
S-function
under
PSPICE
en
vironment
is
ne
wly
pro
vided.
This
will
bring
more
adv
antages
o
v
er
con
v
entional
approach
adopted
in
such
pre
vious
w
ork
and
a
v
oid
to
manage
t
he
dizzy
number
of
Simulink
function
blocks.
The
generated
digital
signals
can
be
transferred
to
the
tar
get
embedded
system
or
fed
into
the
po
wer
circuit
made
from
realistic
electrical
components
under
PSPICE.
Results
and
discussion
are
carried
out
while
rele
v
ant
conclusions
are
highlighted
at
the
end
of
this
paper
.
2.
PR
OPOSED
PO
WER
INVER
TER
T
OPOLOGY
In
contrast
to
some
structures
suggested
in
the
literature
that
call
for
e
xtra
capacitors,
diodes
or
transformers
to
clamp/bring
the
v
oltage
up
to
a
suitable
le
v
el,
the
proposed
MLI
topology
depicted
in
Figure
1(a)
(top)
mak
es
use
only
of
v
oltage
sources
and
switches
(the
Schottk
y
diode
D
S
only
tak
e
part
of
the
dri
ving
circuitry
of
Figure
1(a)
(base)
to
allo
w
asymmetric
turn
on
and
of
f).
Namely
,
for
the
symmetric
scheme
(where
k
=
1
),
there
are
four
unidirectional
(
S
1
;j
to
S
3
;j
)
and
tw
o
bidirectional
(
S
2
;j
)
po
wer
switches
supplied
by
tw
o
identical
DC
v
oltage
sources.
The
sam
e
frame
w
ork
can
be
e
xtended
to
pro
vide
asymmetric
operation
by
ha
ving
the
v
oltage
of
the
second
DC
source
equals
twice
that
of
the
first
one
(
k
=
2
).
Notice
that
S
1
;
1
and
S
1
;
2
share
a
common
drain
while
S
3
;
1
and
S
3
;
2
share
a
common
source
electrode.
On
the
other
hand,
asymmetric
arrangement
with
k
=
3
is
also
possible
b
ut
require
that
the
location
between
the
pair
of
switches
S
1
;j
and
S
2
;j
then
between
S
2
;j
and
S
3
;j
are
sw
apped.
This
arrangement
will
not
be
considered
here
because
it
e
xhibits
the
same
performance
as
that
with
k
=
2
.
The
current
path
of
dif
ferent
operat
ing
modes
of
the
proposed
topology
is
depicted
by
Figure
1(b)
while
a
li
st
of
switch
states
is
tab
ulated
in
T
able
1.
In
order
to
ensure
that
all
the
desirable
v
oltage
le
v
els
are
produced
and
e
v
ery
v
oltage
source
is
protected
ag
ainst
short-circuits.
The
general
rule
can
be
then
defined
as
follo
ws:
S
i;j
=
f
0
;
1
g
2
Y
j
=1
3
X
i
=1
S
i;j
=
1
:
(1)
Since
the
proposed
structure
are
b
uilt
from
unidirectional
and
bidirectional
po
wer
swi
tches,
and
because
each
topology
comes
with
a
number
of
redundant
switching
states,
dif
ferent
switching
scenarios
are
a
v
ailable.
When
one
or
more
po
wer
switches
within
a
gi
v
en
po
wer
in
v
erter
circuit
f
ail,
either
permanently
or
temporarily
,
the
po
wer
deli
v
ered
to
the
load
will
therefore
be
altered
and
causing
a
decrease
in
the
o
v
erall
system
reliability
.
T
o
pre
v
ent
that
from
happening,
a
f
ault-tolerant
application
should
be
programmed
by
making
use
of
a
v
ailable
redundant
switch
states.
F
or
ea
ch
configuration,
the
T
able
2
summarizes
these
redundant
states
and
pro
vides
the
switching
patterns
accordingly
.
Also,
some
hints
are
gi
v
en
to
address
the
po
wer
consumption
issue.
Design
and
implementation
of
an
optimized
multile
vel
...
(Mohammed
Setti)
Evaluation Warning : The document was created with Spire.PDF for Python.
1390
r
ISSN:
2088-8694
(
a
)
(
b
)
(a)
(
a
)
(
b
)
(b)
Figure
1.
(a)
Proposed
po
wer
in
v
erter
structure
(top)
and
optocoupler
and
totem-pole
g
ate
dri
v
er
(base).
(b)
Current
path
of
dif
ferent
operating
modes
under
symmetric
(
k
=
1
)
and
asymmetric
(
k
=
2
)
setups.
k
is
the
v
oltage
ratio
T
able
1.
Switching
combinations
of
the
proposed
MLI
topology
for
symmetric
and
asymmetric
operations
le
v
el
in
p.u.
symmetric
asymmetric
S
1
;
1
S
1
;
2
S
2
;
1
S
2
;
2
S
3
;
1
S
3
;
2
S
1
;
1
S
1
;
2
S
2
;
1
S
2
;
2
S
3
;
1
S
3
;
2
3
n/a
n/a
n/a
n/a
n/a
n/a
0
1
0
0
1
0
2
0
1
0
0
1
0
0
0
0
1
1
0
1
0
1
1
0
0
0
0
1
1
0
0
0
1
(
r
edundant
state
)
0
0
0
1
1
0
n/a
n/a
n/a
n/a
n/a
n/a
0
1
1
0
0
0
0
1
1
0
0
0
0
0
(
r
edundant
state
)
0
0
0
0
1
1
0
0
0
0
1
1
0
(
r
edundant
state
)
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
0
1
0
0
1
0
0
1
(
r
edundant
state
)
0
0
1
0
0
1
n/a
n/a
n/a
n/a
n/a
n/a
2
1
0
0
0
0
1
0
0
1
0
0
1
3
n/a
n/a
n/a
n/a
n/a
n/a
1
0
0
0
0
1
3.
PO
WER
EFFICIENCY
COMP
ARISON
WITH
O
THER
T
OPOLOGIES
Mainly
,
there
are
tw
o
types
of
po
wer
losses
dissipated
within
a
semiconductor
switching
de
vice,
namely
the
conduction
and
the
switching
losses.
The
former
loss
es
are
associated
with
the
drain-to-source
O
N
resistance,
while
the
latter
are
link
ed
up
with
the
input/output
parasitic
capacitances
C
iss
and
C
oss
.
Also
and
since
all
FETs
are
symmetrical
de
vices,
the
a
v
erage
po
wer
conduction
loss
of
the
MOSFET
is
calculated
as
follo
ws:
P
m
=
R
ds
(
ON
)
1
2
Z
2
0
i
2
(
t
)
d
t
=
R
ds
(
ON
)
I
2
RMS
;
(2)
Where
R
ds
(
ON
)
is
the
drain-to-source
O
N
-state
resistance
of
the
po
wer
MOSFET
.
The
a
v
erage
po
wer
conduction
loss
P
m
can
be
e
v
aluated
to
as
the
product
of
R
ds
(
ON
)
and
the
square
of
the
RMS
drain
current.
Considering
that
at
instant
t
,
there
are
n
MOSFETs
in
the
current
path,
the
a
v
erage
v
alue
of
the
conduction
po
wer
loss
P
c
of
the
DC-to-A
C
con
v
erter
can
be
formulated
as
belo
w:
P
c
=
P
m
2
Z
2
0
n
(
t
)
d
t
=
P
m
N
A
V
G
:
(3)
Int
J
Po
w
Elec
&
Dri
Syst,
V
ol.
11,
No.
3,
Septemeber
2020
:
1388
–
1397
Evaluation Warning : The document was created with Spire.PDF for Python.
Int
J
Po
w
Elec
&
Dri
Syst
ISSN:
2088-8694
r
1391
T
able
2.
Redundant
switch
states
under
symmetric
and
asymmetric
operations
of
the
proposed
MLI
Configuration
Redundanc
y
State
P
attern
Note
Asymmetric
2
0
S
3
;
1
+
S
3
;
2
Preferred
(lo
w
po
wer
losses)
(
k
=
2)
0
S
2
;
1
+
S
2
;
2
Not
recommended
(high
po
wer
losses)
Symmetric
4
V
1
S
2
;
2
+
S
3
;
1
Identical
performance
(
k
=
1)
0
S
3
;
1
+
S
3
;
2
Suitable
when
either
V
1
or
+
V
1
redundant
state
is
used
(lo
w
switching
po
wer
losses)
0
S
2
;
1
+
S
2
;
2
Not
recommended
(high
po
wer
losses)
+
V
1
S
2
;
1
+
S
3
;
2
Identical
performance
The
switching
po
wer
loss
P
s
is
equal
to
the
sum
of
all
turn-on
and
turn-of
f
ener
gy
losses
in
a
fundamental
c
ycle
of
the
output
v
oltage
[14].
This
can
be
written
as
follo
ws:
P
s
=
n
X
k
=1
n
on
;k
X
i
=1
E
on
;
ki
+
n
X
k
=1
n
o
;k
X
i
=1
E
o
;
ki
!
f
sw
;
(4)
where
f
sw
is
the
switching
frequenc
y
and
n
on
;k
and
n
o
;k
are
the
number
of
turn-on
and
turn-of
f
of
the
k
th
MOSFET
during
a
fundamental
c
ycle.
Also,
E
on
;
ki
is
the
ener
gy
loss
of
the
k
th
MOSFET
during
the
i
th
turn-on
and
E
o
;
ki
is
the
ener
gy
loss
of
the
k
th
MOSFET
during
the
i
th
turn-of
f.
Since
most
MLI
structures
in
v
olv
e
high
number
of
po
wer
switches,
the
reason
to
dri
v
e
them
by
fundamental
frequenc
y
modulation
(FSFM)
becomes
ine
vitable
so
as
to
alle
viate
the
po
wer
switching
losses,
which
mak
es
the
conduction
losses
(
R
ds
(
ON
)
)
dominate
o
v
er
those
incurred
by
the
switching
transitions
(
Q
g
and
C
oss
):
2
R
ds
(
ON
)
I
2
RMS
(
Q
g
V
gs
+
C
oss
V
2
ds
)
f
sw
;
(5)
where
Q
g
is
the
g
at
e
char
ge
of
the
MOSFET
,
V
gs
is
the
RMS
g
ate-to-source
v
oltage,
C
oss
is
the
MOSFET
output
parasiti
c
capacitance
(
C
gd
+
C
ds
)
and
V
ds
is
the
RMS
drain-to-source
v
oltage.
The
total
l
o
s
s
P
t
is
then
the
sum
of
the
conduction
and
switching
losses:
P
t
=
P
c
+
P
s
P
c
:
(6)
T
able
3.
T
otal
blocking
v
oltage
and
acti
v
e
po
wer
switches
in
dif
ferent
cascaded
MLI
topologies
under
FSFM
T
opology
(a)
(b)
(c)
(d)
(e)
(f)
(g)
(h)
Proposed
No.
of
DC
sources
3
2
2
2
5
2
2
4
2
No.
of
bidirectional
switches
0
0
1
6
1
2
0
2
2
No.
of
unidirectional
switches
6
6
6
0
10
6
6
5
4
symmetric
(5-le
v
el)
No.
of
acti
v
e
po
wer
switches
n/a
24
28
32
n/a
28
n/a
26
20
T
otal
blocking
v
oltage
in
V
1
n/a
8
11
10
n/a
14
n/a
11
10
asymmetric
(7-le
v
el)
No.
of
acti
v
e
po
wer
switches
36
36
n/a
48
72
44
36
40
32
T
otal
blocking
v
oltage
in
V
1
18
12
n/a
16
18
22
12
16
16
Most
po
wer
ef
ficient
topologies
cannot
be
e
v
aluated
just
in
terms
of
ho
w
man
y
electronic
parts
the
y
w
ould
require,
b
ut
in
addition,
the
y
should
be
assessed
with
re
g
ard
to
the
total
number
of
their
acti
v
e
po
wer
switches
o
v
er
one
full-time
period
and
their
v
oltage
blocking
capability
.
As
it
w
as
sho
wn
in
T
ables
3
and
4,
the
proposed
MLI
e
xcels
all
the
8
structures
depicted
by
Figure
2
both
in
terms
of
po
wer
ef
ficienc
y
and
total
number
of
acti
v
e
po
wer
switches.
The
total
blocking
v
oltage
comparison
is
also
considered
since
switching
de
vices’
ratings
are
al
w
ays
correlated
to
their
maximum
blocking
v
oltage.
Moreo
v
er
,
the
total
harmonic
distor
-
tion
(THD)
and
indi
vidual
po
wer
dissipation
in
e
v
ery
po
wer
swi
tch
are
tab
ulated
in
T
able
4.
Finally
,
it
should
be
pointed
out
that
all
the
bidirectional
switches
are
assumed
to
be
arranged
by
tw
o
back-to-back
N-channel
po
wer
MOSFETs.
Design
and
implementation
of
an
optimized
multile
vel
...
(Mohammed
Setti)
Evaluation Warning : The document was created with Spire.PDF for Python.
1392
r
ISSN:
2088-8694
T
able
4.
Comparison
of
THD,
switch
po
wer
dissipation
(in
W
atts)
and
po
wer
ef
ficienc
y
of
selected
highly
ef
ficient
cascaded
MLI
topologies
under
FSFM
symmetric
asymmetric
T
opology
—
7.2%
thd
i
,
17.9%
thd
v
—
—
4.0%
thd
i
,
12.5%
thd
v
—
S
1
;
1
S
1
;
2
S
2
;
1
S
2
;
2
S
3
;
1
S
3
;
2
P
(%)
S
1
;
1
S
1
;
2
S
2
;
1
S
2
;
2
S
3
;
1
S
3
;
2
P
(%)
(a)
n/a
n/a
n/a
n/a
n/a
n/a
.599
.590
.606
.588
.599
.593
3.57
99.66
(b)
.636
.651
.659
.663
.688
.684
3.98
99.63
.590
.601
.590
.598
.588
.604
3.57
99.66
(g)
n/a
n/a
n/a
n/a
n/a
n/a
.588
.601
.590
.604
.591
.601
3.58
99.66
Pr
oposed
.630
.627
.258
.260
.485
.486
2.74
99.75
.448
.444
.396
.396
.554
.556
2.79
99.73
(a)
(b)
c
Z
`
(c)
Z
`
(d)
(e)
(f)
Z
`
(g)
(h)
Figure
2.
Cascaded
MLI
topologies
with
reduced
po
wer
switch
count
presented
in
literature:
(a)
from
[16],
(b)
from
[17],
(c)
from
[18],
(d)
from
[19],
(e)
from
[20],
(f)
from
[21],
(g)
from
[7]
and
(h)
from
[22]
4.
C
MEX
AND
PSPICE
CO-SIMULA
TION
This
section
is
de
v
oted
to
co-simulate
the
proposed
MLI
using
C
MEX
S-function
and
PSPICE
program.
Instead
of
using
mathematical
function
blocks
and
graphically
connecting
them
together
to
b
uild
system
models,
the
user
can
rely
on
the
system-functions
called
C
MEX
S-functions
,
which
are
defined
as
computer
language
description
written
in
C/C++
programming
language,
to
benefit
from
their
capabilities
to
interact
with
the
Simulink
engine.
Henceforth,
this
approach
has
the
adv
antage
to
not
be
cumbersome
as
the
former
does
and
requires
less
hardw
are
resources
and
time
during
e
x
ecution
and
maintenance.
Ho
we
v
er
,
only
the
switching
control
can
be
achie
v
ed
that
w
ay
,
since
Simulink
uses
only
ideal
models
and
non
technology-
specific
de
vices.
On
the
contrary
to
other
simulation
programs
lik
e
Simscape
Electrical,
PLECS
and
PSIM,
PSPICE
is
an
industry
standard
SPICE-based
simulator
and
is
primarily
intended
to
model
technology-specific
electronic
components
so
that
to
pro
vide
in-depth
det
ails
about
some
realistic
circuit
beha
viors
during
simulation.
F
or
these
reasons
and
more,
the
proposed
MLI
circuit
is
described
by
netlist.
C
MEX
S-functions
are
based
on
the
C
language.
The
y
must
be
compiled
as
MEX
files
using
mex
util-
ity
,
so
the
resulting
binary
file
is
platform-dependent
and
dynam
ically
loadable
e
x
ecutable
utilized
by
Simulink
program
[15].
Figure
3(a)
depicts
the
typical
w
orkflo
w
for
C
MEX
compiling
and
inte
grating
into
Simulink
models.
During
the
simulation,
the
Simulink
engine
must
retrie
v
e
information
about
the
function
used
by
the
Int
J
Po
w
Elec
&
Dri
Syst,
V
ol.
11,
No.
3,
Septemeber
2020
:
1388
–
1397
Evaluation Warning : The document was created with Spire.PDF for Python.
Int
J
Po
w
Elec
&
Dri
Syst
ISSN:
2088-8694
r
1393
C
MEX
S-function.
As
the
simulation
proceeds,
the
C
MEX
S-function,
the
Ordinary
Dif
ferential
Equations
(ODE)
Solv
er
and
the
Simulink
engine
interact
together
to
achie
v
e
specific
tasks.
The
interaction
between
C
MEX
S-function
and
Simulink
engine
is
realized
by
in
v
oking
callback
methods
that
the
S-function
implements.
In
order
to
model
the
g
ate
switching
patterns
required
to
dri
v
e
the
proposed
po
wer
in
v
erter
,
the
engine
should
in
v
ok
e
sequentially
the
C
MEX
S-function
callback
methods
as
illustrated
in
the
flo
wchart
of
the
Figure
3(b).
The
methods
dra
wn
in
black
line
are
mandatory
,
whereas
those
sho
wn
in
gray
color
are
optional.
Also,
in
the
flo
wchart
gi
v
en
by
the
Figure
3b,
mainly
three
steps
are
in
v
olv
ed:
(
I
)
initialization,
(
I
I
)
calculation
of
switching
outputs
in
the
major
time
st
ep,
and
(
I
I
I
)
termination
of
the
simulation.
The
mdlInitializeSizes()
callback
method
aims
to
identify
the
width
and
data
type
of
dif
ferent
input
and
output
ports.
The
mdlInitializeSampleTimes()
is
then
in
v
ok
ed
to
specify
both
the
of
fset
time
and
sample
rate
at
which
the
S-function
should
operate.
Afterw
ards,
at
e
v
ery
simulation
time
step,
the
mdlOutputs()
method
is
called
to
compute
the
S-function’
s
switching
outputs
by
means
of
the
Simulink
engine
and
then
dispatches
the
results
as
array
elements.
The
block’
s
core
logic
has
to
be
implemented
inside
the
body
of
this
callback
method.
The
FSFM
algorithm
follo
ws
this
requirement,
which
in
f
act
corresponds
to
one
of
the
switching
pattern
set
tab
ulated
in
T
able
1.
As
its
name
implies,
the
mdlTerminate()
method
is
called
to
perform
an
y
tasks
required
at
the
end
of
the
simulation
process
lik
e
closing
deb
ugging
files
or
freeing
dynamic
memory
allocations.
The
generated
FSFM
g
ating
signals
for
dri
ving
the
proposed
MLI
are
based
on
the
NLC
scheme
[8]
and
gi
v
en
by
Figure
4
under
symmetric
and
asymmetri
c
operations.
The
rounding
functions
defined
inside
mdlOutputs()
must
handle
the
misleading
number
representation
of
half-inte
gers
by
defining
a
proper
tie-breaking
rule
such
as
round-half-to-e
v
en.
These
signals
can
either
be
fed
into
PSPICE
or
directly
sent
to
the
tar
get
hardw
are
via
the
Embedded
Coder
,
which
allo
ws
the
code
to
be
compiled
and
e
x
ecuted
on
an
y
processor
.
C-MEX
sour
ce
file
mex
utility
C
compiler
GC
C
,MSV
C
,...
Binary
MEX-file
S-function
b
lock
R
efer
ence
Gating
Signals
Œ
S
i
;
j
n
m
ODE
solv
er
Sim
ulink
engine
*.MEXW32/64
(WIN
OS)
T
o
SPICE
via
FSTIM
MOSFET
ga
te
dri
v
ers
On
tar
get
har
d
w
ar
e
(Embed
ded
Coder)
(a)
mdlInitializeSizes()
mdlSetInputPortFrameData()
mdlInitializeSampleTimes()
mdlSetInputPortDataType()
mdlSetOutputPortDataType()
mdlSetDefaultPortDataTypes()
mdlOutputs()
mdlTerminate()
(
i
)
(
ii
)
(
iii
)
(b)
Figure
3.
(a)
T
ypical
w
orkflo
w
for
C
MEX
compiling
and
inte
grating
into
Simulink
models.
The
results
can
be
either
link
ed
to
PSPICE
or
run
on
the
tar
get
hardw
are
via
the
Embedded
Coder
.
(b)
C
MEX
S-function
callback
methods
flo
wchart
used
for
modeling
the
switching
controller
S
1
;
1
S
1
;
2
S
2
;
1
S
2
;
2
S
3
;
1
0
4
8
12
16
20
24
28
32
time
in
milliseconds
S
3
;
2
0
4
8
12
16
20
24
28
32
time
in
milliseconds
sy
mmetric
(5-
le
vel
)
asy
mmetric
(7-
le
vel
)
Figure
4.
Gating
signals
for
the
proposed
MLI
for
both
symme
tric
and
asymmetric
configurations
under
FSFM
Design
and
implementation
of
an
optimized
multile
vel
...
(Mohammed
Setti)
Evaluation Warning : The document was created with Spire.PDF for Python.
1394
r
ISSN:
2088-8694
The
PSPICE
file
stimulus
(FSTIM)
de
vices
are
aimed
to
pro
vide
digital
signals
to
a
gi
v
en
circuit
node
through
e
xternal
data
file
[23],
so
as
to
pro
vide
a
link
to
the
FSFM
g
ating
signals.
Another
approach
called
PSPICE
SLPS
interf
ace
has
already
been
suggested
to
pro
vide
co-simulation
under
Simulink
[24].
This
tool
comes
with
good
features,
b
ut
still
remain
some
dra
wbacks
that
should
be
addressed:
(a)
The
actual
electronic
block
is
substi
tuted
with
an
ideal
model
since
the
simulation
of
the
po
wer
circuit
is
set
up
under
Simulink
en
vironment;
(b)
The
internal
properties
of
PSPICE
that
ha
v
e
smaller
time
steps
than
those
of
Simulink
cannot
be
check
ed.
Also,
some
Simulink
minor
steps
are
skipped,
and
thus
data
is
not
fully
e
xchanged
with
PSPICE
[25];
(c)
The
SLPS
data
e
xchange
is
synchronized
with
Simulink
steps.
T
o
pre
v
ent
o
v
erlooking
phenomena
from
happening,
Simulink
maximum
step
size
should
be
chosen
carefully
,
so
to
ensure
the
best
trade-of
f
between
accurac
y
and
simulation
time;
(d)
Only
one
SLPS
block
per
Simulink
model
is
allo
wed
[25].
The
number
of
interf
aces
an
SLPS
block
can
handle
is
limited.
As
reported
by
man
y
users,
Simulink
will
crash
once
the
limit
is
e
xceeded;
(e)
Some
l
imitations
are
inherited
from
the
f
act
that
Simulink
are
generic
simulation
programs
not
tar
geted
for
mix
ed-signal
electronic
designs.
In
contrast
to
ho
w
the
SLPS
interf
ace
tool
operates,
the
suggested
co-si
mulation
approach
is
no
w
fulfilled
thoroughly
under
PSPICE
en
vironment,
so
as
to
pre
v
ent
the
idealization
of
the
used
electronic
de
vices.
Consequently
,
the
o
v
erlooking
and
data
e
xchange
issue
are
no
longer
a
problem
as
soon
as
the
g
ating
signals
retrie
v
ed
from
Simulink
are
correctly
processed
and
adapted
to
the
requirements
of
PSPICE
stimulus
de
vices.
The
dri
ving
of
the
dif
ferent
po
wer
MOSFETs
of
Figure
1(a)
(top)
is
done
by
the
A
v
ago
HCPL-3140
optocoupler
based
dri
v
ers
sho
wn
by
Figure
1(a)
(base).
Ho
we
v
er
,
each
non-in
v
erting
optical
ly
isolated
totem-
pole
g
ate
dri
v
er
requires
one
floating
po
wer
supply
of
12
v
olts
with
respect
to
the
ground
node
V
EE
,
so
as
to
be
able
to
dri
v
e
high-side
N-channel
po
wer
MOSFETs.
Ad
di
tionally
,
a
100
nF
bypass
capacitor
C
D
must
be
added
to
stabilize
the
operation
of
the
high
g
ain
linear
amplifier
,
otherwise,
the
switching
functionality
may
be
compromised.
Finally
,
PSPICE
simulator
needs
at
least
one
ground
or
node
zer
o
to
reference
all
the
calculated
v
oltages,
so
in
order
to
isolate
the
control
side
of
the
circuit
from
the
po
wer
side
and
distinguish
between
the
tw
o
side
grounds,
a
resistance
R
1
with
high
v
alue
is
used
to
pre
v
ent
floating
node
error
from
happening.
Moreo
v
er
,
the
load
Z
`
represents
an
inducti
v
e
load
with
a
DPF
=
98
%
lagging
formed
by
an
R
`
=
50
in
series
with
an
L
`
=
32
mH
.
All
the
po
wer
MOSFETs
operate
at
fundamental
frequenc
y
(50
Hz)
and
are
under
h
a
rd
switching
condition.
Lo
w
switching
po
wer
losses
are
al
w
ays
correlated
with
f
ast
commutations
which
are
the
major
reason
for
electromagnetic
interference
and
v
oltage
spik
e
a
cross
the
drain
and
source
terminals
due
to
the
e
xistence
of
stray
inductances.
Additionally
,
the
switching
speed
v
aries
with
respect
to
the
v
alue
of
the
g
ate
resistor
R
G
which
w
ould
mak
e
the
selection
more
dif
ficult
in
order
to
a
v
oid
the
o
v
erlap
time
that
will
cause
lar
ge
current
sur
ge.
Both
Figures
5(d)
and
5(e)
present
some
sur
ges
in
the
drain
current
of
the
MOSFETs
on
each
column
when
the
e
xternal
g
ate
resistors
R
2
and
the
Schottk
y
diodes
D
S
are
omitted
from
the
dri
ving
circuit
of
Fig-
ure
1(a)(base).
As
it
can
be
seen,
the
maximum
rating
allo
wed
for
the
pulsed
drain
current
is
e
xceeded
in
case
of
a
600V
CoolM
OS
CFD7
N-channel
po
wer
MOSFET
,
so
in
order
to
get
rid
from
this
situation,
each
po
wer
switch
should
be
dri
v
en
through
dif
ferent
g
ate
resistors
to
allo
w
asymmetric
turn
on
and
turn
of
f.
Figure
5(f)
and
5(g)
highlight,
respecti
v
ely
,
the
di
f
ference
by
plotting
the
g
ate-to-source
v
oltage
V
GS
for
both
S
2
;
2
/
S
3
;
2
S
1
;
1
/
S
2
;
1
that
ha
v
e
been
equi
pped
with
g
ate
resistors
on
top
of
those
which
ha
v
e
no
additional
g
ate
resistors.
As
the
Figures
5(h)
and
5(i)
suggest,
the
drain
current
spik
es
through
the
six
po
wer
switches
are
no
w
mostly
v
an-
ished.
The
A
C
output
v
oltage
and
current
of
the
proposed
5-
and
7-le
v
el
po
wer
in
v
erters
are
illustrated
together
through
the
Figure
5(a)
under
an
inducti
v
e
load
with
a
DPF
0
:
98
lagging.
Additionally
,
the
v
oltage/current
harmonic
profiles
for
both
c
o
nfi
gu
r
ations
are
also
included,
respecti
v
ely
,
by
Figures
5(b)
and
by
Figures
5(c),
wherein
their
THD
are
calculated
separately
within
one
complete
time
period
(
20
ms
).
0
5
10
15
20
320
V
0
C
320
V
l
o
ad
v
ol
t
a
ge
V
`
TIME
IN
MILLISECONDS
(a)
8
A
0
C
8
A
l
o
ad
current
I
`
(cos
0
:
98
)
0
5
10
15
20
0
l
o
ad
current
I
`
(cos
0
:
98
)
TIME
IN
MILLISECONDS
320
V
0
C
320
V
l
o
ad
v
ol
t
a
ge
V
`
(a)
Figure
5
Int
J
Po
w
Elec
&
Dri
Syst,
V
ol.
11,
No.
3,
Septemeber
2020
:
1388
–
1397
Evaluation Warning : The document was created with Spire.PDF for Python.
Int
J
Po
w
Elec
&
Dri
Syst
ISSN:
2088-8694
r
1395
0
0
:
5
1
1
:
5
2
2
:
5
3
3
:
5
4
4
:
5
5
0
336
V
37
V
thd
17
:
9
%
y
-
scale
not
linear
0
0
:
5
1
1
:
5
2
2
:
5
3
3
:
5
4
4
:
5
5
0
6
:
6
A
0
:
3
A
thd
7
:
2
%
y
-
scale
not
linear
FREQ
IN
KIL
OHER
TZ
(b)
(b)
0
0
:
5
1
1
:
5
2
2
:
5
3
3
:
5
4
4
:
5
5
0
330
V
20
V
thd
12
:
5
%
y
-
scale
not
linear
0
0
:
5
1
1
:
5
2
2
:
5
3
3
:
5
4
4
:
5
5
0
6
:
5
A
0
:
2
A
thd
4
%
y
-
scale
not
linear
FREQ
IN
KIL
OHER
TZ
(c)
(c)
0
5
10
15
20
150
A
0
C
150
A
S
1
;
1
S
1
;
1
S
1
;
1
S
2
;
1
S
2
;
1
S
2
;
1
=
S
3
;
1
S
2
;
1
(d)
(d)
20
0
5
10
15
20
150
A
0
C
150
A
S
1
;
2
S
1
;
2
S
1
;
2
S
2
;
2
=
S
3
;
2
S
2
;
2
S
2
;
2
S
2
;
2
(e)
(e)
1
;
666
1
;
667
1
;
668
0
C
15
V
V
T
H
(f)
C
(f)
668
3
;
135
3
;
136
3
;
137
0
C
15
V
V
T
H
(g)
(g)
0
5
10
15
20
10
A
0
C
10
A
TIME
IN
MILLISECONDS
(h)
(h)
0
5
10
15
20
10
A
0
C
10
A
TIME
IN
MILLISECONDS
(i)
(i)
Figure
5.
Output
w
a
v
eforms/spectra
and
switching
characteristics
of
the
proposed
MLI
with
an
inducti
v
e
load
(
DPF
0
:
98
).
(a)
Load
v
oltage
V
`
and
current
I
`
w
a
v
eforms
in
symmetric/asymmetric
configura
tion,
respecti
v
ely
.
(b)
Load
v
oltage/current
spectrum
under
symmetric
setup.
(c)
Load
v
oltage/current
spectrum
under
asymmetric
setup
(The
y-axis
scale
of
fundamental
spectrum
and
harmonic
spectra
is
nonlinear).
Drain
current
through
the
po
wer
MOSFETs
where
no
g
ate
resistor
(
R
2
=
0
):
(d)
S
1
;
1
(
),
S
2
;
1
(
)
and
S
3
;
1
(
).
(e)
S
1
;
2
(
),
S
2
;
2
(
)
and
S
3
;
2
(
).
V
oltage
across
the
g
ate
and
source
terminals
of
the
po
wer
MOSFETs:
(f)
S
2
;
2
(
/
)
and
S
3
;
2
(
/
)
with/without
g
ate
resistors.
(g)
S
1
;
1
(
/
)
and
S
2
;
1
(
/
)
with/without
g
ate
resistors
(
V
T
H
is
the
g
ate
threshold
v
oltage
of
the
600V
CoolMOS
CFD7
po
wer
MOSFET).
Drain
current
when
g
ate
resistors
and
Schottk
y
diodes
are
added:
(h)
S
1
;
1
(
),
S
2
;
1
(
)
and
S
3
;
1
(
).
(i)
S
1
;
2
(
),
S
2
;
2
(
)
and
S
3
;
2
(
)
5.
CONCLUSION
In
this
article,
the
symmetric
and
asymmetric
configurations
of
the
proposed
MLI
were
compared
to
some
well-established
topologies
in
the
literature.
It
has
sho
wn
that
the
proposed
structure
accomplishes
the
highest
po
wer
ef
ficienc
y
scor
e
(
99
:
73
99
:
75%
)
by
restraining
the
number
of
acti
v
e
po
wer
switches
per
c
ycle.
Moreo
v
er
,
the
proposed
symme
tric
topology
e
xhibits
lo
w
total
blocking
v
oltage
and
se
v
eral
redundant
switch
states,
which
w
ould
bring
additional
enhancement
to
the
o
v
erall
system
reliability
.
Alternati
v
ely
,
asym-
metric
structure
pro
vides
a
good
harmonic
profile
(about
4%
THD
i
and
12.5%
THD
v
)
which
positi
v
ely
impact
the
A
C
side
lo
w-pass
filter
in
order
to
comply
with
the
international
standards
in
terms
of
po
wer
quality
.
Design
and
implementation
of
an
optimized
multile
vel
...
(Mohammed
Setti)
Evaluation Warning : The document was created with Spire.PDF for Python.
1396
r
ISSN:
2088-8694
Afterw
ards,
the
FSFM
w
as
described
i
n
C
MEX
and
run
thr
o
ugh
a
single
Simulink
S-function
block.
This
w
ould
bring
significant
enhancement
in
de
v
elopment
and
simulation
speed
and
mak
e
maintenance
ef
fort-
less
when
compared
to
the
con
v
entional
approach
based
on
graphical
modeling.
The
generated
g
ating
signals
can
be
either
sent
to
the
embedded
hardw
are
or
inte
grated
as
digital
stimuli
through
the
PSPICE
file
stimulus
de
vice.
This
technique
has
some
adv
antages
o
v
er
the
SLPS
interf
ace
t
o
ol
especially
when
simulating
open-
loop
SMPS
topologies
and
mak
e
use
of
m
o
r
e
realistic
electronic
de
vices
pro
vided
by
almost
e
v
ery
electronics
manuf
acturers.
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ijeh,
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ault
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erter
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w
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el
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erter
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el
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erter
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v
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”
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on
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2018.
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w
po
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ef
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v
en-le
v
el
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v
erter
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el
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el
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Dri
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11,
No.
3,
Septemeber
2020
:
1388
–
1397
Evaluation Warning : The document was created with Spire.PDF for Python.
Int
J
Po
w
Elec
&
Dri
Syst
ISSN:
2088-8694
r
1397
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Mac
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[25]
Cadence
Design
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Inc.,
PSPICE
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Interface
User
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2016.
Design
and
implementation
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multile
vel
...
(Mohammed
Setti)
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