Inter
national
J
our
nal
of
P
o
wer
Electr
onics
and
Dri
v
e
System
(IJPEDS)
V
ol.
11,
No.
4,
December
2020,
pp.
1883
1889
ISSN:
2088-8694,
DOI:
10.11591/ijpeds.v11.i4.pp1883-1889
r
1883
A
high-perf
ormance
multile
v
el
in
v
erter
with
r
educed
po
wer
electr
onic
de
vices
Amer
Chlaihawi,
Adnan
Sab
bar,
Hur
J
edi
Department
of
Electrical
Engineering,
Uni
v
ersity
of
K
uf
a,
Iraq
Article
Inf
o
Article
history:
Recei
v
ed
Feb
20,
2020
Re
vised
Apr
26,
2020
Accepted
May
19,
2020
K
eyw
ords:
High-performance
operation
Multile
v
el
in
v
erter
(MLI)
Nearest
le
v
el
modulation
(NLM)
ABSTRA
CT
This
paper
introduces
a
ne
w
topology
of
multile
v
el
in
v
erter
,
which
is
able
to
operate
at
high
performance.
This
proposed
circuit
achie
v
es
requirements
of
reduced
number
of
switches,
g
ate-dri
v
e
circuits,
and
high
design
fle
xibility
.
In
most
cases
fifteen-le
v
el
in
v
erters
need
at
least
twelv
e
switches.
The
proposed
topology
has
only
ten
switches.
The
in
v
erter
has
a
quasi-sine
output
v
oltage,
which
is
formed
by
le
v
el
generator
and
polarity
changer
to
produce
the
desired
v
oltage
and
current
w
a
v
eforms.
The
detailed
operation
of
the
proposed
in
v
erter
is
e
xpl
ained.
The
theoretic
al
analysis
and
design
procedure
are
gi
v
en.
Simulation
results
are
presented
to
confirm
the
analytical
ap-
proach
of
the
pr
oposed
circuit.
A
15-le
v
el
and
31-le
v
el
multile
v
el
in
v
erters
were
de-
signed
and
tested
at
50
Hz.
This
is
an
open
access
article
under
the
CC
BY
-SA
license
.
Corresponding
A
uthor:
Adnan
Sabbar
,
Department
of
Electrical
Engineering,
Uni
v
ersity
of
K
uf
a,
Najaf,
Iraq.
Email:
adnan.sabbar@uokuf
a.edu.iq
1.
INTR
ODUCTION
W
ith
the
rapid
de
v
elopment
of
po
wer
electronics,
the
demand
of
po
wer
con
v
erters
are
high
perfor
-
mance,
lo
w
cost
and
high
po
wer
quality
applications
[1–3].
Reducing
the
number
of
switches
in
po
wer
elec-
tronics
can
impro
v
e
the
po
wer
density
and
leads
to
lo
w
v
oltage
stress
on
switches
[4–7].
Multile
v
el
con
v
erters
can
att
ain
both
fundamental
switching
frequenc
y
and
high
switching
frequenc
y
PWM
[8–10].
Therefore,
mul-
tile
v
el
in
v
erters
with
separate
DC
sources
are
suited
for
operation
at
lo
w
frequenc
y
to
achie
v
e
lo
w
switching
losses
and
high
ef
ficienc
y
[11–13].
In
v
erters
in
such
application
handle
high
v
oltage
and
e
xtensi
v
e
po
wer
.
Thus,
high-le
v
el
in
v
erters,
which
are
compos
ed
of
switching
po
wer
de
vices
inte
grated
g
ate
bipolar
transistors
(IG-
BTs),
are
suitable
t
o
achie
v
e
high
v
oltage
applications
[14,
15].
Most
con
v
entional
multile
v
el
in
v
erters,
such
as
Flying
Capacitor
(FC),
Neutral
Point
Clamped
(NPC),
and
Cascaded
H-Bridge
(C
HB)
suf
fer
from
high-v
oltage
stress
on
switch,
high
Electro
Magnetic
Interference
(EMI)
and
poor
po
wer
quality
output
[16–18].
In
order
to
solv
e
these
issues,
a
ne
w
topology
of
multile
v
el
in
v
erter
is
presented.
In
last
fe
w
decades,
se
v
eral
authors
ha
v
e
been
increasingly
focused
on
multile
v
el
in
v
erter
topologies
with
reduction
in
numbers
of
po
wer
switches
[19–23].
T
opology
[24]
is
combined
of
IGBT
and
diode
causing
reduction
in
ef
ficienc
y
.
In
addition,
the
losses
and
cost
will
be
increased
and
its
industrial
applications
will
be
restricted.
In
[25]
sub-multile
v
el
con
v
erter
blocks
are
connected
in
series.
This
circuit
consists
of
capacitors
and
four
bi-directional
switches
are
utilized
in
each
unit.
Thus,
the
installation
area
i
s
increased
in
the
proposed
topology
.
Most
of
the
multile
v
el
in
v
erters
suf
fer
from
high
v
oltage
stresses
at
the
po
wer
switches
and
require
dif
ferent
v
oltage
rating
of
the
po
wer
switches.
In
addition,
switching
frequenc
y
leads
to
a
decrease
in
ef
ficienc
y
J
ournal
homepage:
http://ijpeds.iaescor
e
.com
Evaluation Warning : The document was created with Spire.PDF for Python.
1884
r
ISSN:
2088-8694
due
to
switching
losses.
Therefore,
the
proposed
topology
is
attracti
v
e
for
high-performance
applications.
This
w
ork
proposes
a
high
po
wer
quality
multile
v
el
in
v
erter
with
reduced
in
numbers
of
po
wer
semi-
conductor
de
vices.
The
proposed
topology
can
attain
a
lar
ge
number
of
le
v
els
with
asymmetric
DC
v
oltage
sources.
This
topology
is
based
on
the
con
v
entional
in
v
erter
that
utilizes
le
v
el
generation
and
polarity
change.
The
ne
w
circuit
can
be
utilized
for
15-le
v
el
and
31-le
v
el
in
v
erter
.
T
o
implement
a
15-le
v
el
in
v
erter
,
ten
IGBT
switches
and
three
dc
v
oltage
sources
are
selected.
The
multile
v
el
in
v
erter
generates
staircase
v
oltage
w
a
v
eform
with
decreased
electromagnetic
compatibility
(EMC)
issues
and
lo
w
distortion.
The
ne
w
topology
also
utilizes
lo
w
number
of
po
wer
switches
and
includes
a
lo
w-design
comple
xity
.
The
described
topology
also
sho
ws
in
details
the
analysis
of
the
steady-state
v
oltage
w
a
v
eforms.
In
order
to
determine
an
appropri
ate
characteristics
of
the
multi
le
v
el
in
v
erter
,
a
design
procedure
has
been
applied.
The
proposed
circuit
w
as
si
mulated
and
tested
at
a
frequenc
y
of
50
Hz.
A
c
on
t
rol
unit
of
signals
are
used
to
generate
fix
ed
v
alues
of
operating
frequenc
y
and
duty
ratio.
Collecti
v
ely
,
these
fe
atures
mak
e
the
ne
w
multil
e
v
el
in
v
erter
adv
antageous
in
applications
,
such
as
A
C
dri
v
es
and
F
A
CTS
de
vices.
2.
AN
AL
YSIS
OF
THE
PR
OPOSED
MUL
TILEVEL
INVER
TER
T
OPOLOGY
Figure
1
sho
ws
the
proposed
multile
v
el
in
v
erter
circuit.
The
proposed
topology
consist
of
le
v
el
gen-
erate
and
polarity
change.
The
le
v
el
generation
has
po
wer
switch
P
i
and
po
wer
switch
S
i
,
which
is
connected
in
series
with
the
DC
v
ol
tage
source
V
i
.
The
circuit
of
polarity
change
is
comprised
H-Bridge
po
wer
switches
H
S
i
and
connected
in
parallel
with
the
load.
In
this
study
,
IGBT
transis
tors,
which
ha
v
e
high
switching
perfor
-
mance,
are
used
in
the
proposed
topology
.
W
e
focus
on
identifying
the
characteristics
of
the
proposed
in
v
erter
to
pro
vide
a
fle
xible
output
v
oltage
w
a
v
eform
across
the
load
of
the
circuit
with
minimum
number
of
switches.
Figure
1.
Proposed
multile
v
el
in
v
erter
circuit
The
ne
w
topology
can
produce
fifteen-le
v
el
output
during
asymmetric
condition.
The
operating
modes
during
asymmetric
operation
of
the
circuit
to
obtain
alternating
output
v
oltage
across
the
load
is
sho
wn
in
Figure
2.
The
proposed
topology
requires
six
switches
and
three
DC
v
oltage
sources
to
generate
positi
v
e-le
v
els
steps
output
v
oltage
at
the
load
as
sho
wn
in
the
left
part
of
the
in
v
erter
.
A
polarity
changer
,
which
is
comprised
of
four
switches,
is
added
to
generate
the
ne
g
ati
v
e-le
v
els
steps
output
v
oltage
at
the
load.
The
switches
H
S
i
are
utilized
to
re
v
erse
the
polarity
of
the
output
v
oltage
of
the
in
v
erter
.
The
analysis
of
the
proposed
circuit
is
based
on
the
the
O
N
-state
and
the
O
FF
-state
of
the
switches
P
i
and
S
i
,
respecti
v
ely
.
The
switches
H
S
1
and
H
S
4
are
O
N
during
the
positi
v
e
c
ycle
of
the
operation,
while
the
switches
H
S
2
and
H
S
4
are
O
FF
during
the
ne
g
ati
v
e
c
ycle
of
the
operation.
Int
J
Po
w
Elec
&
Dri
Syst,
V
ol.
11,
No.
4,
December
2020
:
1883
–
1889
Evaluation Warning : The document was created with Spire.PDF for Python.
Int
J
Po
w
Elec
&
Dri
Syst
ISSN:
2088-8694
r
1885
Figure
2.
Operation
mode
of
switches.
Figure
3
sho
ws
the
illustrating
operation
of
idealized
steps
of
the
circuit
o
v
er
a
period.
As
can
be
seen,
each
step
for
output
v
oltage
is
double
of
the
v
oltage
source
V
i
.
The
switches
P
i
and
S
i
of
the
in
v
erter
can
be
deri
v
ed
according
to
the
control
unit
circuit
to
generate
pulse
width
modulator
w
a
v
eforms
as
sho
wn
in
Figure
4.
Figure
3.
Le
v
el
modulation
technique
Figure
4.
Control
unit
of
signals
for
15-le
v
el
switches
T
o
establish
the
design
equations,
the
circuit
beha
vior
is
analyzed
in
each
interv
al.
It
is
considered
V
i
as
a
reference
v
oltage
in
the
proposed
multile
v
el
in
v
erter
.
The
number
of
DC
v
oltage
sources
N
V
base
on
the
number
of
unit
cell
m
in
the
in
v
erter
N
=
2
m
;
(1)
where,
m
=
0
;
1
;
2
;
3
:::i
.
The
steps
of
output
v
oltage
D
steps
can
be
found
as
D
steps
=
2
i
+2
1
:
(2)
The
maximum
output
v
oltage
v
O
is
the
sum
of
DC
v
oltage
sources
N
v
O
=
D
steps
1
2
V
i
:
(3)
The
po
wer
switches
of
the
proposed
topology
can
be
switched
at
an
y
duty
c
ycle
D
.
It
can
be
determined
based
on
the
specifications
of
the
multile
v
el
in
v
erter
.
A
high-performance
multile
vel
in
verter
with
r
educed
power
electr
onic
de
vices
(Amer
Chlaihawi)
Evaluation Warning : The document was created with Spire.PDF for Python.
1886
r
ISSN:
2088-8694
3.
DESIGN
PR
OCEDURE
A
design
procedure
for
the
ne
w
multile
v
el
in
v
erter
is
presented
to
supply
a
resisti
v
e
load
at
operating
frequenc
y
f
s
=
50
Hz.
In
the
design
procedure,
the
follo
wing
design
parameters
V
i
,
v
O
,
and
D
are
determined.
The
reference
DC
v
oltage
source
V
i
for
15-le
v
el
and
31-le
v
el
were
chosen
to
be
45
V
and
20
V
,
respecti
v
ely
.
Furthermore,
the
duty
c
ycle
of
po
wer
switches
is
50%.
The
reference
DC
v
oltage
V
i
can
be
selected
basing
on
the
application
of
the
in
v
erter
.
In
the
proposed
circuit,
the
designer
can
easily
adjust
the
v
alue
of
duty
c
ycle
to
achie
v
e
the
re
qu
i
red
dri
v
en
v
oltage
w
a
v
eform
of
the
p
o
we
r
switches.
F
or
15-le
v
el
output
and
step
v
oltage
45
V
,
the
peak-to-peak
output
v
oltage
of
the
multile
v
el
in
v
erter
is
v
aried
from
+312
to
-312.
F
or
the
31-le
v
el
in
v
erter
,
the
reference
DC
v
oltage
V
i
=
20
V
is
applied
at
the
proposed
circuit,
the
peak
v
alue
of
v
oltage
stress
is
312
V
at
duty
c
ycle
D
=
50%.
The
peak
v
alue
of
the
v
oltage
stress
depends
on
the
total
DC
source
v
oltage
on
the
po
wer
switch.
The
v
alue
of
v
GE
v
oltage
based
on
the
characteristics
of
the
po
wer
switch
IGBT
in
the
in
v
erter
.
Therefore,
it
is
important
to
select
a
proper
dri
ving
v
oltage
rating
for
the
po
wer
switch.
In
this
w
ork,
the
v
oltage
v
GE
rating
of
the
po
wer
switch,
which
is
utilized
in
the
g
ate
dri
v
er
,
is
20
V
.
The
tr
ansistor
B
UP306D
w
as
utilized
as
a
IGBT
po
wer
switch
in
circuit.
The
load
of
the
proposed
in
v
erter
is
chosen
to
be
a
resisti
v
e
load
R
L
=
50
.
The
major
dif
ferences
between
the
proposed
topology
and
the
popular
multile
v
el
in
v
erters
ar
e
the
number
of
po
wer
switches
and
the
type
of
switching.
Thus,
most
multile
v
el
in
v
erter
circuits
operate
at
least
twelv
e
po
wer
switches.
T
o
operate
fifteen-le
v
el
in
v
erter
,
the
proposed
multile
v
el
in
v
erter
has
six
switches
in
the
le
v
el
generation
and
four
switches
in
the
H-bridge.
Furthermore,
the
switching
beha
vior
of
IGBT
transistors
in
the
proposed
multile
v
el
in
v
erter
can
achie
v
e
high
v
oltage
applications.
Therefore,
the
performance
of
the
in
v
erter
can
increase
the
ef
ficienc
y
of
the
in
v
erter
.
These
features
sho
w
the
the
adv
antage
of
the
ne
w
circuit.
The
specifications
and
parameters
of
the
circuit
are
gi
v
en
in
T
able
1.
T
able
1.
List
of
parameters
for
multile
v
el
in
v
erter
at
f
s
=
50
Hz
Components
V
alue
B
UP306D
V
C
E
=
1200
V
,
V
GE
=
20
V
,
I
C
=
23
A
C
iss
=
1300
pF
,
C
oss
=
100
pF
,
C
r
ss
=
50
pF
R
50
V
i
45
V
,
20
V
4.
SIMULA
TION
RESUL
TS
Based
on
the
design
methodology
and
the
circuit
operation,
the
proposed
multile
v
el
in
v
erter
has
been
v
erified
through
MatLab
simulation.
The
performance
of
the
proposed
topology
during
the
asymmetric
oper
-
ation
is
analyzed.
A
50
Hz
PWM
signal
is
used
to
supply
the
po
wer
switches,
and
the
v
alue
of
duty
c
ycle
is
D
=
0.5.
A
B
UP
306D
IGBT
po
wer
switch
with
anti
parallel
diode
(1200
V
,
23
A)
from
Siemens
w
as
used
as
the
po
wer
transist
or
in
the
multile
v
el
in
v
erter
circuit.
In
order
to
mak
e
the
circuit
operates
in
high
performance,
this
po
wer
switch
is
optimized
for
lo
w
switching
losses
and
high-speed
operating.
The
proposed
topology
is
simulated
for
15-le
v
el
in
v
erter
and
31-le
v
el
in
v
erter
,
respecti
v
ely
.
4.1.
15-le
v
el
multile
v
el
in
v
erter
T
o
generate
appropriate
switching
Pulse
W
idth
Modulation
schemes
for
the
po
wer
switches,
the
circuit
in
Figure
4
is
used.
The
fundamental
frequenc
y
is
utilized
to
generate
the
s
witching
pulses
in
the
circuit.
According
to
the
switching
states,
the
pulses
are
generated
at
each
step
to
dri
v
e
the
po
wer
switches
as
sho
wn
in
Figure
5.
If
the
pulses
form
accurately
,
the
ef
ficienc
y
and
harmonic
distortion
can
be
controlled
ef
fecti
v
ely
in
the
proposed
multile
v
el
in
v
erter
.
The
switches
of
H-bridge
are
operated
in
a
complementary
mode
to
produce
the
positi
v
e
and
the
ne
g
ati
v
e
le
v
els
steps
output
v
oltage
at
the
load.
The
in
v
erter
pro
vides
the
A
C
signal
with
a
peak
magnitude
312
V
to
the
load,
when
the
dc
v
oltage
source
is
45
V
.
In
order
to
observ
e
the
step
v
oltage
w
a
v
eform
at
the
output
resistor
,
the
zoomed
w
a
v
eform
of
the
output
v
oltage
for
the
multile
v
el
in
v
erter
is
sho
wn
in
Figure
6.
It
can
be
seen
that
the
step
size
of
the
w
a
v
eform
is
45
V
.
The
step
le
v
el
of
the
in
v
erter
w
as
captured
in
Figure
7.
It
is
clear
that
the
output
v
oltage
is
close
to
sine
w
a
v
eform.
The
presented
approach
pro
v
es
that
the
ne
w
in
v
erter
pro
vides
lo
w-v
oltage
stress
and
small-v
alued
components.
Int
J
Po
w
Elec
&
Dri
Syst,
V
ol.
11,
No.
4,
December
2020
:
1883
–
1889
Evaluation Warning : The document was created with Spire.PDF for Python.
Int
J
Po
w
Elec
&
Dri
Syst
ISSN:
2088-8694
r
1887
Figure
5.
Simulated
15-le
v
el
switching
pulse
w
a
v
eforms
of
multile
v
el
in
v
erter
Figure
6.
Simulated
of
15-le
v
el
zoomed
output
v
oltage
w
a
v
eform
Figure
7.
Simulated
of
15-le
v
el
multile
v
el
in
v
erter
w
a
v
eform
4.2.
31-le
v
el
multile
v
el
in
v
erter
The
proposed
topology
can
be
utilized
for
31-le
v
el
to
generate
A
C
w
a
v
eform
close
to
sine
signal.
The
po
wer
switches
of
31-le
v
el
circuit
are
deri
v
ed
by
the
control
circuit
to
form
switching
pulses
as
sho
wn
in
Figure
8.
The
output
v
oltage
w
a
v
eform
in
Figure
9
sho
ws
the
operation
of
31-le
v
el
of
the
proposed
topology
.
It
is
clearly
sho
ws
that
the
operation
of
the
circuit
is
obtained
by
the
le
v
el
generation
and
change
polarity
circuit
to
supply
the
A
C
signal
to
t
he
load.
The
maximum
v
alue
of
the
v
oltage
stress
w
as
measured
as
312
V
for
the
input
v
oltage
V
=
20
V
.
The
peak-to-peak
output
v
oltage
of
the
multi
le
v
el
in
v
erter
across
the
load
is
v
aried
from
+185
to
-185.
It
can
be
noticed
that
the
output
v
oltage
is
close
to
sine
w
a
v
eform.
A
high-performance
multile
vel
in
verter
with
r
educed
power
electr
onic
de
vices
(Amer
Chlaihawi)
Evaluation Warning : The document was created with Spire.PDF for Python.
1888
r
ISSN:
2088-8694
Figure
8.
Simulated
31-le
v
el
switching
pulse
w
a
v
eforms
of
multile
v
el
in
v
erter
Figure
9.
Simulated
31-le
v
el
multile
v
el
in
v
erter
w
a
v
eform.
5.
CONCLUSION
A
ne
w
switched-mode
multile
v
el
in
v
erter
,
which
is
deri
v
ed
from
con
v
entional
multile
v
el
in
v
erter
,
has
been
introduced.
This
topology
operates
at
constant
duty
c
ycle
and
frequenc
y
.
The
ne
w
topology
can
be
designed
for
15-le
v
el
and
31-le
v
el
in
v
erter
.
An
H-bridge
is
added
in
the
proposed
topology
to
generate
ne
g
ati
v
e
v
oltage
le
v
els.
It
has
a
lo
w
number
of
po
wer
switches,
lo
w
switch
v
oltage
stress,
lo
w
DC
v
oltage
sources,
and
fle
xible
design.
The
ne
w
circuit
is
designed
to
s
up
pl
y
A
C
signal
to
the
load
e
v
en
when
lo
w-input
v
oltage
of
the
in
v
erter
is
a
v
ailable.
Based
on
abo
v
e
analysis,
the
prototype
with
50
Hz
w
as
designed
and
simulated.
The
simulation
testing
results
demonstrate
a
good
agreement
between
the
simulations
and
the
calculations.
The
proposed
circuit
can
be
used
in
applications
that
demand
high
performance,
such
as
F
A
CTS
controllers
and
adjustable
motor
dri
v
es.
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Chlaihawi)
Evaluation Warning : The document was created with Spire.PDF for Python.