Inter national J our nal of P o wer Electr onics and Dri v e Systems (IJPEDS) V ol. 12, No. 3, September 2021, pp. 1293 ∼ 1303 ISSN: 2088-8694, DOI: 10.11591/ijpeds.v12.i3.pp1293-1303 ❒ 1293 P erf ormance e v aluation of GaN and Si based dri v er cir cuits f or a SiC MOSFET po wer switch Mart ´ ın J . Carr ´ a 1 , Her n ´ an T acca 2 , J os ´ e Lipo v etzk y 3 1, 2 Uni v ersidad de Buenos Aires, F acultad de Ingenier ´ ıa, Departamento de Electr ´ onica, Laboratorio de Control de Accionamientos, T racci ´ on y Potencia (LABCA TYP), Buenos Aires, Ar gentina 3 Centro At ´ omico Bariloche and Instituto Balseiro, R ´ ıo Ne gro, Ar gentina 3 Consejo Nacional de In v estig aciones Cient ´ ıcas y T ´ ecnicas, Buenos Aires, Ar gentina Article Inf o Article history: Recei v ed Jan 9, 2020 Re vised Apr 26, 2021 Accepted Jul 14, 2021 K eyw ords: GaN Gate Dri v er Performance SiC ABSTRA CT Silicon carbide (SiC), ne w po wer switches (PSW) require ne w dri v er circuits which can tak e adv antage of their ne w capabilities. In this paper a no v el Gallium Nitride (GaN) based g ate dri v er is proposed as a solution to control SiC po wer switches. The proposed dri v er is implemented and is performance compared with its silicon (Si) counterparts on a hard switching en vironment. A thorough e v aluation of the ener gy in v olv ed in the switching process is presented sho wing that the GaN based circuit e xhibits similar output losses b ut reduces the control po wer needed to operate at a specied frequenc y . This is an open access article under the CC BY -SA license . Corresponding A uthor: Mart ´ ın J. Carr ´ a Department of Electronics, F acultad de Ingenier ´ ıa Laboratorio de Control de Accionamientos, T racci ´ on y Potencia (LABCA TYP) A v . P aseo Colon 850, C1063A CV , Buenos Aires, Ar gentina Email: mcarra@.uba.ar 1. INTR ODUCTION Po wer electronics technology has al w ays e v olv ed to w ard higher ef cienc y , higher po wer density and more inte grated systems [1], [2]. Currently most con v erters are designed to be embedded into the application housing and therefore its v olume is restricted by the size of the product case. This size reduction is achie v ed using smaller passi v e elements and higher switching frequencies [3], which poses ne w challenges system ef - cienc y due to switching and dri v e losses [4]. Increasing the po wer density of the system without af fecting the o v erall ef cienc y requires a perfor - mance impro v ement in the po wer switches. Unfortunately , silicon (Si) based po wer de vices characteristics are reaching their theoretical limits, and e xhibit important limitations re g arding blocking v oltage capability , operation temperature and switching frequenc y restricting the use of them [1], [5]. In the past years, a ne w generation of po wer de vices based on wide bandg ap (WBG) s emiconductor materials [6] became a v ailable as commercial-of-the-shelf (CO TS) products. WBG semiconductors, lik e silicon carbide (SiC) and g allium nitride (GaN), sho w impro v ed material characteristics making them an e xcellent option as Si po wer de vices replacements. WBG materials are characterized by their high electrical eld strength which allo ws v ery thin drift layers with high doping rates [7], [8]. Consequently , de vices bas ed on these materials are beneted by reduced on-state resistance leading to reduced conduction losses [9]. Furthermore, carrier mobility in WGB materials is superior than in Si, allo wing f aster turn-on / of f switching times and hence, lo wering switching losses. J ournal homepage: http://ijpeds.iaescor e .com Evaluation Warning : The document was created with Spire.PDF for Python.
1294 ❒ ISSN: 2088-8694 Po wer de vices based on WBG materials are attracti v e because of their lo w input capacitance, lo w conduction and lo w switching losses, high operation temperature and high thermal conducti vity [10]. The use of these ne w de vices allo ws increasing the ef cienc y and a considerable impro v ement in size and rob ustness of po wer con v erters. In addition to this, SiC is a preferred semiconductor compared to GaN for high-v oltage and high-po wer de vice applications when both electrical an thermal limitations are considered [11]. Ev en though po wer MOSFETs based on SiC ha v e the benet of being a Normally Of f de vice, their oxide layer creates a lar ge input capacitance [12] which is a challenging problem while designing the dri v er circuit. This capacitance has to be char ged and dischar ged f ast enough to ensure the correct operation of the de vice. The dri v er circuit is a critical asset to e xploit the superior characteristics on this type of po wer switch (PSW). Using a dri v er with insuf cient current capability to control the v oltage of the g ate capacitance will increase switching losses prohibiti v ely , causing the destruction of the de vice by o v erheating. The maximum operating frequenc y of a PSW is bounded by the current handling capacity and the internal losses in the acti v e components of the g ate dri v er circuit. T o enable high frequenc y operation it is critical to reduce them to a minimum [13] while ensuring appropriate dri v e strength. Lo w v oltage high electron mobility transistors (HEMTs) based on GaN are good candidates to imple- ment the output stage of a dri v er circuit. This transistors outperform their Si counterparts in e v ery electrical aspect reducing to a minimum the capaciti v e load to the controller circuit without compromising the v oltage handling or the thermal management of the solution itself. Potential approaches on ho w to dri v e SiC MOS- FETs ha v e been widely e v aluated by [14]-[18], b ut nally , all of them, implement the dri v ers using traditional Si based de vices. On the other hand, Nag aoka et al . [12] introduces for the rst time the use of a dri v er output stage based on GaN HEMTs utilizing discrete custom de vices. In addition to Nag aoka’ s w ork, Okuda et al . [19] sho w the proof of concept of the GaN HEMT as part of a g ate dri v er that tar gets a SiC MOSFET in a hard switching en vironment. Ev en though Okuda’ s w ork proposes the use of CO TS de vices, the PSW is used at lo w blocking v oltage and drain current. Therefore, no conclusi v e e v aluation has been published re g arding the benets of the use of GaN based de vices as acti v e de vices in the g ate dri v er circuit. This w ork presents the implementation of a PSW g ate dri v er using lo w v oltage GaN HEMTs to con- trol a 1200V SiC MOSFETs plus an in-depth performance e v aluation and comparison ag ainst equi v alent g ate dri v ers using Si based MOSFETs and Bipolar transistors. The rest of t he paper is or g anized as follo ws: section 2 introduces the concept of the dri v er topology and the circ u i t implementation details. Section 3 present the test bench setup used in the Dual Pulse T ester (DPT). Section 4 presents the measurements performed to the each v ersion of the dri v er . And nally sections 5 conducts discussion on the data g athered and, nally , section 5 sho ws the conclusions of the w ork. 2. PR OPOSED GA TE DRIVER This section presents the w orking principles of the proposed PSW g ate dri v er using lo w v oltage GaN HEMTs to control a 1200V SiC MOSFETs. The structure of an SiC MOSFET is such that the g ate forms a non linear capacitor [20]. Char ging the g ate capac itor turns the PSW on and allo ws current to o w between drain and source terminals, while dischar ging it turns the de vice of f and a lar ge v oltage may then be block ed across the drain and source terminals. The minimum v oltage when the g ate capacitor is char ged and the de vice can just about conduct is the threshold v oltage ( V T H ). F or operating an SiC MOSFET as a switch, a v oltage suf cient lar ger than V T H should be applied between the g ate and source terminals. 2.1. Gate dri v er topology Figure 1 sho ws a simplied schematic of the proposed g ate dri v er , an elementary in v erter le g structure is made of GaN transistors Q H and Q L connected in series between tw o po wer supplies V O N and V O F F . The central point of the le g, labeled as “G” in the Figure 1, is connected to the g ate of the PSW . When Q H or Q L are on resistors R GH and R GL respecti v ely limit the char ging current o wing to the g ate thus controlling the V GS sle w rate and therefore the PSW turn-on / of f time. The inductor L G models the parasitic inductance of the connection to the PSW g ate terminal, minimized as much as possible in the design of the PCB. Gallium Nitride HEMTs EPC-2012 from EPC [21] ha v e been selected as the current booster switches ( Q H and Q L ) due to their high continuous drain current I D , their high blocking v oltage rate V D S S , and their lo w On-Resistance R D S O N . Moreo v er these transistors presents a fraction of the input capacitance C I S S to the controller in comparison with Si options. Finally their small footprint allo ws a compact circuit design. T able 1 summarizes the k e y parameters of the GaN transistor . Resistors R B H and R B L limit the current o w Int J Po w Elec & Dri Syst, V ol. 12, No. 3, September 2021 : 1293 – 1303 Evaluation Warning : The document was created with Spire.PDF for Python.
Int J Po w Elec & Dri Syst ISSN: 2088-8694 ❒ 1295 to t he g ates of the transistors Q H and Q L respecti v ely , reducing the ringing in their g ates and lo wering the electromagnetic emissions, ensuring a f ast transition of the de vices while operating them in a secure condition. The v oltages of the isolated po wer supplies used to actually char ge and dischar ge the g ate of the PS W where selected to impro v e its performance. T o turn on the PSW V O N = 20 V is used, lo wering to the minim um the on resistance ( R D S − O N ), thus reducing the conduction losses. On the other hand V O F F = − 5 V w as selected to turn of f the PSW increasing the noise immunity of the g ate of the po wer de vice. Figure 1. Dri v er circuit block diagram T able 1. EPC2012 eGAN transistors k e y parameters list [21] P arameter V alue Breakdo wn v oltage V D S − B 200 V Rated current (Tc=100C) I D 3 A Gate-source v oltage Max V GS − M X − 5 V / 6 V threshold v oltage V T H 1 . 4 V input capacitance C I S S 128 pF output capacitance C O S S 73 pF g ate char ge Q G 1 . 5 nC on-state resistance R D S − O N 70 m Ω Operation of the GaN booster stage is achie v ed using a dedicated controller unit. The unit reads the input signal I N and the dead-time conguration t D and generates tw o complementary non o v erlapping control feeds. These feeds, with the dead-time already injected, are transmitted through the isolation barrier using tw o high speed Aluminium Gallium Arsenide (AlGaAs) optocouplers. The transmitted signals are sourced into a CO TS half bridge controller which nally turns on and of f the GaN transistors using a V GS of V D R I V E / 0 V respecti v ely . F or this particular w ork V D R I V E is 5 V . Currently GaN HEMTs lacks of a commercially a v ailable complementary de vice. Therefore, to con- trol Q H , the half-bridge controller must shift V D R I V E v oltage and reference it to the source terminal of Q H which commutes between V O F F and V O N . The t D is an 8-bit digital input that congures the dead-time (in steps of 20 nS ) that is injected in between the state transitions to a v oid the undesired shot-through ef fect in the GaN half-bridge. During the dead-time both Q H and Q L are of f, and the conduction state of the PSW is retained until it’ s e xtinguished. This ef fect is sho wn in Figure 2, the shaded zones of the diagram represent the dead-time and its ef fect in the conduction status of the PSW . Figure 2. Acti v ation signals of the dri v er circuit after the isolation barrier P erformance e valuation of GaN and Si based driver cir cuits ... (Mart ´ ın J . Carr ´ a) Evaluation Warning : The document was created with Spire.PDF for Python.
1296 ❒ ISSN: 2088-8694 2.2. Operation stages During a full switching c ycle of the PSW the dri v er circuit goes through four specic stages. A detailed description of the dri v er operation is sho wn in Figure 3. − Stage-1-(S1): signal I N is lo w and the V GS L of Q L rises to V D R I V E , turning the de vice ON. Q H remains in OFF state ( V GS H = 0 V ) and the v oltage across V GS − P S W of the PSW is V O F F . During this stage the capacitance C I S S = C GD + C GS is dischar ged through R GL lea ving the PSW in OFF state with no current o w allo wed. − Stage-2-(S2): signal I N changes to high and the dead-time starts running. Q L is turned of f without changing the conduction state of Q H . The V GS − P S W v oltage is maintained by its o wn input capacitance C I S S . − Stage-3-(S3): after the dead-time is e xtinguished and then transistor Q H is turned ON ( V GS H = V D R I V E ). Q L remains OFF and the v oltage across V GS − P S W rises up to V O N . During this stage the capacitance C I S S is char ged through R GH turning on the PSW and allo wing the current to o w . − Stage-4-(S4): signal I N is lo w and dead-time starts running. Q H is deacti v ated while Q L remains OFF too and the conduction state of the PSW remains unaltere d while the dead-time is consumed until Stage-1 be gins and the sequence starts all o v er ag ain. Figure 3. Operation states of the dri v er and the SiC Po wer MOSFET 3. EXPERIMENT AL RESUL TS T o e v aluate the performance of the proposed GaN current booster a prototype w as b uilt and tested. Furthermore, for comparati v e purposes, tw o v ariants of the same topology were b uilt one using Si bipolar junction transistor (BJT) FZT1053A [22] and its complementary de vice FZT951 [23] both from Diodes Inc. and the other one using Si MOSFETs NDT3055 [24], T able 2 describes the main characteristics of each v ariant. In order to measure the switching transients and the po wer losses of the dri v er and the PSW , a fully congurable Double Pulse T ester (DPT) board [25] with an inducti v e load w as used. This conguration is sho wn in Figure 4, the dashed box indicates the de vice under test (DUT). The acti v e de vice of the DPT is k ept unchanged during all t he tests. T o ensure f ast interchangeability and stability in the testbench each tested circuit w as designed and b uilt using the same connection footprint. T able 2. Dri v er k e y characteristics GAN MOS BJT [l]Booster de vice EPC2012 NDT3055L [l]FZT1053A and FZT951 F ootprint Custom SO T223 SO T223 T opology Half bridge Half bridge Emmiter follo wer PCB Area 8 . 14 mm 2 98 mm 2 98 mm 2 R GH R GL 10Ω 10Ω 10Ω R B H R B L 5 . 6Ω 5 . 6Ω 56Ω Int J Po w Elec & Dri Syst, V ol. 12, No. 3, September 2021 : 1293 – 1303 Evaluation Warning : The document was created with Spire.PDF for Python.
Int J Po w Elec & Dri Syst ISSN: 2088-8694 ❒ 1297 Figure 4. DPT measurement bench schematic with its parasitics components The load inductor L Load w as manuf actured with an inductance of 505 µH with an air core to a v oid saturation. An ultra f ast SiC schottk y diode [26] w as chosen as a free wheeling diode D F W . The b us capac- itance C B U S is composed of a multilayer ceramic and metalized polyprop ylene lm capacitors stack which totalize a capacitance of 5 µF with a maximum rated v oltage of 1200 V . The PSW used in the DPT is the SiC MOSFET CMF10120D from CREE [27]. Its k e y parameters are sho wn in in T able 3. T able 3. CREE CMF10120D transistors k e y parameters list [27] P arameter ( T = 25 ◦ C ) V alue Breakdo wn v oltage V D S − B 1200 V Rated current (Tc=100C) I D 24 A Gate-source v oltage Max V GS − M X − 5 V / + 25 V Threshold v oltage V T H 3 . 1 V Input capacitance C I S S [l] 928 pF @ V D S = 800 V 1200 pF @ V D S = 0 V Output capacitance C O S S 63 pF @800 V Gate char ge Q G 47 . 1 nC On-state resistance R D S − O N 190 m Ω The test w as carried out aplying tw o pulses of dif ferent durations on the g ate of the PSW . T o set the drain test current of the PSW to I D = 22 A a curr ent b uild-up pulse with a duration of T buil d u p = 20 µS w as used with a b us v oltage of V B U S = 580 V . Fina lly , the turn on time w as T O N = 2 . 5 µS , and the operation frequenc y w as dened as f sw = 125 K H z with a duty c ycle D ∼ 30% . During the measurements the test circuit remains unchanged, only the g ate dri v er is replaced to comapre each v ariant. All v oltage measurements were performed using a T ektr onix THS3014 with four isolated oating channels oscilloscope. As a current transducer a Pearson Electronics INC. current monitor Model: 2878 [28] w as used. During the realization of the measurements all the best practices described in [29] were enforced. 3.1. Dri v er contr ol signals Figure 5 (a) sho ws the V GS v oltage of each transistor at the output stage in the GaN based dri v er during the current b uild up pulse. During the dead-time periods in S2 and S4 both switches, Q H and Q L , are of f a v oiding the shoot-through ef fect in the GaN half bridge le g. Also it is possible to see that dri v e v oltage le v el for Q H is lo wer lo wer than for Q L due to the ef fect of the bootstrap diode of the half-bridge controller . Figure 5 (b) e xhibits the v oltage signal generated by the g ate dri v er with the dead-time already injected sho wing that the dead-time has no direct inuence in the pulse conformation. P erformance e valuation of GaN and Si based driver cir cuits ... (Mart ´ ın J . Carr ´ a) Evaluation Warning : The document was created with Spire.PDF for Python.
1298 ❒ ISSN: 2088-8694 (a) (b) Figure 5. These gures are; (a) Control signals of the GaN transistors with the dead-time injected during the current b uild up pulse; (b) PSW g ate to source v oltage generated by the GaN g ate dri v er during the current b uild up pulse 3.2. T ur n-on characterization Figure 6 sho ws the drain-source current I D S , drain-source v oltage V D S and instantaneous po wer P D during the turn-on transient of the PSW for each dri v er technology . Because of the inducti v e nature of the load used in the DPT , at the start of the test pulse, the free wheel ing d i ode D F W conducts the full test current. The PSW current I D sho wn in Figure 6 (a) increases displacing the D F W current while the PSW drain v oltage V D S , sho wn in Figure 6 (b), is clamped to the b us v oltage V B U S because of the conducting free wheel diode. When the PSW conducts the test current in full, D F W is reco v ered and block ed. Afterw ards the v oltage V D S f alls do wn to the on-state le v el. The inst antaneous po wer dissipated in the PSW w as obtained combining V D S and I D S and the result is sho wn in Figure 6 (c). The shape on each curv e is mostly triangular and compatible with an inducti v e switching. A summary the measurements during the turn-on stage is detailed in T able 4. (a) (b) (c) Figure 6. Electrical quantities measured on the SiC MOSFET during the T urn ON period; (a) T urn ON drain current; (b) T urn ON v oltage; (c)T urn ON instantaneous po wer T able 4. SiC MOSFET switching ON: transient measurement summary GaN MOS BJT T urn-on time ( ns ) 41 45 41 V D S F all-time ( ns ) 21 20 21 V D S Sle w-rate ( V / nS ) -23 -24 -23 I D S Rise-time ( ns ) 20 25 20 I D S Sle w-rate ( A / nS ) 0.8 0.7 0.8 3.3. T ur n-off characterization Figure 7 sho ws the drain-source current I D S , drain-source v oltage V D S and instantaneous po wer P D v alues during the turn-of f transient of the PSW for each dri v er technology . As the on test time for GaN and BJT Int J Po w Elec & Dri Syst, V ol. 12, No. 3, September 2021 : 1293 – 1303 Evaluation Warning : The document was created with Spire.PDF for Python.
Int J Po w Elec & Dri Syst ISSN: 2088-8694 ❒ 1299 dri v ers dif fers from the used with the MOS dri v er the switch of f information w as separated for clarity: Figures 7 (a), (c), and (e) sho w the transients for GaN and BJT dri v ers while Figure 7 (b), (d), and (f). During the of f transition the PSW de vice conducts the test current as the V D S v oltage, sho wn in Figure 7 (a) and (b), rises up to the supply rail. When the v oltage transient ends, D F W becomes forw ard-biased and be gins to conduct displacing the PSW current I D S , and f alling do wn to zero as sho wn in Fi g ur es 7 (c) and (d). Figures 7 (e) and (f) sho w the instantaneous po wer dissipated in the PSW and in the same w ay than during the turn-ON transient it presents a triangular shape compatible with a pure inducti v e switching. A summary of the measurements during the turn-of f stage can be found in T able 5. (a) (b) (c) (d) (e) (f) Figure 7. Electrical quantities measured on the SiC MOSFET during the T urn OFF period; (a) T urn ON drain-source v oltage for GAN and BJT ; (b) T urn ON drain-source v oltage for MOS; (c) T urn OFF drain current for GAN and BJT ; (d) T urn OFF drain current for MOS; (e) T urn OFF instantaneous po wer for GAN and BJT ; (f) T urn OFF instantaneous po wer for MOS T able 5. SiC MOSFET switching OFF: transient measurement summary . GaN MOS BJT T urn-of f time ( ns ) 19 22 20 V D S Rise-time ( ns ) 12 13 13 V D S Sle w-rate ( V / nS ) 40 36 37 I D S F all-time ( ns ) 7 9 7 I D S Sle w-rate ( A / nS ) -2.4 -1.9 -2.5 3.4. PSW switching ener gy and dri v er losses The switching action of the PSW and the dri v er itself result in una v oidable losses. The operation of turning on or of f the PSW in v olv es the char ging and dischar ging process of the g ate capacitance and, therefore, P erformance e valuation of GaN and Si based driver cir cuits ... (Mart ´ ın J . Carr ´ a) Evaluation Warning : The document was created with Spire.PDF for Python.
1300 ❒ ISSN: 2088-8694 a certain amount of char ge has to be transferred. The po wer lost due to the dri ving the PSW input capacitance process is dissipated in the output stage components of the g ate dri v er circuit formed by R GH , R GL , Q H and Q L and is computed as Output l osses . T o accomplish this operation the control stage has to command the output de vices Q L and Q H during the switching process, hence dissipating ener gy . The po wer dissipated during the control operation is accounted for in the contr ol losses . The dri v er po wer losses are summarized in T able 6. In addition to this the switching ener gy of the PSW during a full period is 470 µJ within 1 ± % despite the g ate dri v er technology . 4. DISCUSSION This section discusses the results obtained on the bench tests of the PSW using the proposed GaN based g ate dri v er and compares it ag ainst their Si based BJT and MOSFET counterparts. T able 6. Gate dri v e po wer dissipation GAN MOS BJT Output losses ( W ) 2.3 2.4 1.9 Control losses ( W ) 2 33 290 4.1. PSW Curr ent and v oltage beha vior Figures 6 and 7 sho w the v oltages and currents in the PSW when is turned on and of f using the GaN, BJT and MOSFET dri v ers. GaN and BJT dri v ers produce similar v oltages, currents and instantaneous po wer signals. During the turn-on process the rise times of I D S are similar to the V D S taking 20ns to reach the test current and 21ns to achie v e full v oltage swing, with a total time of 41ns. During the turn-of f process the PSW drain current f all time achie v es 7ns, while it tak es 12ns and 13ns to the GaN and BJT dri v ers respecti v ely to block the PSW and withstand the full test v oltage totalizing a turn-of f time of 19ns for GaN dri v er and 20ns for the BJT v ariant. Ne v ertheless, the PSW sho ws a slo wer beha vior under the control of the MOS dri v er taking 25ns, a 25% more time, to the de vice to achie v e the test current. Due to the inducti v e load, the V D S transient start is delayed increasing the total turn-on switching time in 10% totalizing 45ns. During the turn-of f the PSW tak es 13ns to block the v oltage and 9ns to reduce the I D S to zero computing a turn-of f time of 22ns. Figure 8 sho ws that the MOS g ate dri v er produces a slo wer V GS sle w-rate in the PSW unlik e GaN and BJT dri v ers that e xhibit a si milar performance. As the output transistors on each dri v er were selected to ha v e similar current and blocking v oltage capacity , the dri v e strength of each dri v er implementation is actually limited by the e xternal resistor , R GH or R GL , depending on the transition, plus the contrib ution of the PSW internal resistor R G . As sho wn in Figure 9 (a) when the dri v er switches from S 2 to S 3 , to turn on the PSW , Q H char ges the output capacitance composed of C QL O S S and C P S W I S S . Con v ersely in Figure 9 (b) when the dri v er switches from S 4 to S 1 , turning of f the PSW , Q L dischar ges the g ate capacitance, made up by C QH O S S and C P S W I S S . In T able 7 summarises the output capacitance of the transistors used, it is possible to see that during the S 2 7→ S 3 transition, the dri v en g ate capacitance using the GaN dri v er is 25% smaller than the MOS v ersion, and 50% smaller than the BJT option. In the same w ay , during the S 4 7→ S 1 transition, the dri v en g ate capacitance the GaN solution is 30% smaller than the MOS, and 23% smaller than the BJT . Furthermore, both MOS and GaN dri v er half-bridge controllers use a supply v oltage of V D R I V E = 5 V for the output stage in addition to a bootstrap capacitor to operate the high side of the le g with the consequence of reducing the o v erdri v e. While this v oltage pro v es to be suf ci ent to turn-on the EPC2012 it’ s not enough for the NDT3055 MOSFET which typically needs 10V of V GS to operate at its full electrical characteristics therefore slo wering the V GS rise-time in the MOS dri v er . Despite the do wngraded performance of the MOS dri v er , all three circuits produce alm ost the same switching ener gy loss in the PSW under the same operation condition. Thes e results are consistent with the switching ener gy informed in the PSW’ s de vice datasheet [3]. The slightly increase in switching loss of the MOSFET v ersion is re lated to its slo wer performance, b ut is ne glectable in comparison with the absolute ener gy v alue. 4.2. Dri v er loss assessment The Output Po wer of each dri v er sho w similar losses on each technology v ariant. BJT e xhibits a reduction in 25% on the output loss due to the scatter of the on-resistance R C E O N on each de vice of the Int J Po w Elec & Dri Syst, V ol. 12, No. 3, September 2021 : 1293 – 1303 Evaluation Warning : The document was created with Spire.PDF for Python.
Int J Po w Elec & Dri Syst ISSN: 2088-8694 ❒ 1301 output stage. On the other hand GaN sho ws a great impro v ement in the control losses with 2mW , 14 times smaller than MOS and 145 times smaller than needed for the BJT output stage. (a) (b) (c) Figure 8. PSW g ate to source v oltage; (a)T urn ON v oltage for GAN, BJT and MOS; (b) T urn OFF v oltage for GAN and BJT ; (c) T urn OFF v oltage for MOS (a) (b) Figure 9. Current o w during the acti v ation of the dri v er circuit after the isolation barrier; (a) (S2 S3) current o w during T urn ON; (b) (S4 S1) current o w during T urn OFF stage T able 7. Dri v er transistor output capacitance De vice EPC2012 [21] NDT3055L [24] C O S S @ V D S = 0 V ( pF ) 250 600 FZT1053A [22] FZT951 [23] C J E @ V C E = 0 V ( pF ) 520 1150 5. CONCLUSIONS A GaN based g ate dri v er w as proposed, simulated and e xperimentally v alidated in an inducti v e hard switching en vironment using a DPT bench with a state of the art SiC MOSFET as acti v e de vice. Its perfor - mance w as compared ag ainst similar solutions using Si based BJT and MOSFET transistors and during all the e v aluations the PSW sho ws equi v alent performance with almost equal switching losses. This is e xplained since the switching process is dominated by the e xternal g ate resistors R GH and R GL ne glecting the ef fects of the on-resistance of the dri v er output transistors. All three dri v ers sho w similar output losses due to the f act that P erformance e valuation of GaN and Si based driver cir cuits ... (Mart ´ ın J . Carr ´ a) Evaluation Warning : The document was created with Spire.PDF for Python.
1302 ❒ ISSN: 2088-8694 the transistor for each dri v er were selected with similar electrical output charact eristics. On the other hand the GaN dri v er control loss is ne gligible in comparison with the BJT and MOS v ariants relaxing the requirements of the control logic. Fi nally the GaN based output s tage is 12 times smaller . This area reduction in addition to enhanced characteris tics of the GaN ma terial mak es this option suitable to inte grate directly in a dedicated po wer module reducing the circuit parasitics A CKNO WLEDGMENT This w ork is a PhD Thesis supported the F acultad de Ingenier ´ ıa of the Uni v ersidad de Buenos Aires and by the “UB A CYT 20020170100386B A” research subsidy titled “Nue v as estructuras y t ´ ecnicas de simu- laci ´ on y control para con v ertidores est ´ aticos y generadores de pulsos” from the same uni v ersity . REFERENCES [1] X. S he, A. Q. Huang, O. Luc ıa, a nd B. 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