Internati
o
nal
Journal of P
o
wer Elect
roni
cs an
d
Drive
S
y
ste
m
(I
JPE
D
S)
V
o
l.
4, N
o
. 3
,
Sep
t
em
b
e
r
2014
, pp
. 29
9
~
30
7
I
S
SN
: 208
8-8
6
9
4
2
99
Jo
urn
a
l
h
o
me
pa
ge
: h
ttp
://iaesjo
u
r
na
l.com/
o
n
lin
e/ind
e
x.ph
p
/
IJPEDS
Multilevel DC Link Inverter
with Reduced Switches and
Batteries
Y.
R.
M
a
n
j
un
ath
a
*, B
.
A
.
A
n
an
d*
*
* Department of
Electrical Eng
i
n
eerin
g
,
U.V
.
C.E, K.R. Circle, B
e
ngaluru-1
** Electrical
Engineer
ing, Department of Agricu
ltural Engineerin
g,
UAS-B,
GKVK Campus,
Bangalore-65
Article Info
A
B
STRAC
T
Article histo
r
y:
Received Oct 3, 2013
R
e
vi
sed M
a
r
1,
2
0
1
4
Accepted
Mar 18, 2014
Multilev
e
l inver
t
ers are the best solution for m
e
dium
and high vol
tage power
ele
c
troni
c drive
s
. Becaus
e
of
its
unique charac
teris
t
ic of s
y
nthes
i
zin
g
sinusoidal
voltag
e
w
i
th less har
m
onic c
ontents using several D
C
sources. In
a three ph
ase m
u
ltil
evel
invert
er
, ea
ch phase of a
cascad
ed H-bridge invert
er
requires ‘
n
’ DC
sources to obtain
2n + 1
output voltag
e
lev
e
ls. On
e particular
d
i
sa
d
v
a
n
t
a
ge
i
s
that, it
incr
eases
n
u
m
b
e
r
o
f
pow
er semiconducto
r switches.
To o
v
ercom
e
thi
s
disadvantage a
m
u
ltilevel D
C
l
i
n
k
i
n
v
e
r
t
e
r
(
M
LDCLI)
with redu
ced
nu
mber of switc
h
e
s and batteries
is proposed.
Keyword:
Cas
caded
H-brid
ge inv
e
rte
r
DC
li
nk
MLDCLI
Mu
ltilev
e
l in
v
e
rter
Power ele
c
tron
ic
drives
Copyright ©
201
4 Institut
e
o
f
Ad
vanced
Engin
eer
ing and S
c
i
e
nce.
All rights re
se
rve
d
.
Co
rresp
ond
i
ng
Autho
r
:
B.A
.
An
and
Assistant Profe
ssor,
Depa
rt
m
e
nt
of
Ag
ri
cul
t
u
ral
E
ngi
neeri
n
g
,
U
A
S-
B, G.K.V
.
K
,
Ban
g
alo
r
e-
560
065
Em
a
il: lo
v
a
n
a
nd
158
6@g
m
ai
l.co
m
1.
INTRODUCTION
Multilevel converters ha
ve
received m
o
re
and m
o
re
atte
ntion
beca
use
of t
h
eir ca
pabi
lity of high
vol
t
a
ge
ope
rat
i
on,
hi
gh
ef
fi
c
i
ency
, a
n
d
l
o
w el
ect
r
o
m
a
gnet
i
c
i
n
t
e
rfer
e
n
ce (EM
I
).
T
h
e
desi
re
d
o
u
t
p
u
t
of
a
m
u
ltilevel converter is synthesized by several sources
of dc voltages. W
ith a
n
increasing num
b
er of dc
vol
t
a
ge
so
u
r
ce
s, t
h
e c
o
nve
rt
er
v
o
l
t
a
ge
out
put
wa
vef
o
rm
app
r
oac
h
es a
nea
r
l
y
si
nus
oi
dal
w
a
vef
o
rm
whi
l
e
usi
n
g
a fundam
e
ntal fre
que
ncy swit
ching schem
e
. These res
u
lts
in low s
w
itching losses
,
and because of seve
ral dc
sources
, the switches experi
ence a lower
voltage stres
s
. As a result, m
u
ltilevel converter technology is
p
r
o
m
isin
g
fo
r
h
i
gh
po
wer electric d
e
v
i
ces su
ch
as u
tility
ap
p
lication
s
[1]. Th
ere are three
m
a
j
o
r m
u
lt
ilev
e
l
topologies: cascaded, di
ode cl
a
m
ped, a
nd ca
pacitor clam
pe
d. F
o
r t
h
e n
u
m
b
er
of l
e
vel
s
(
M
) great
e
r
t
h
a
n
t
h
re
e
o
r
so
m
e
app
licatio
n
s
su
ch
as reactiv
e and
h
a
rm
o
n
i
c co
m
p
en
satio
n in
p
o
wer system
s, th
ese m
u
l
tilev
e
l
conve
r
ters do not require
a
s
e
parate dc power source
to maintain
each voltage
le
vel. Instea
d,
eac
h voltage
l
e
vel
can be su
pp
o
r
t
e
d by
a capaci
t
o
r
wi
t
h
p
r
o
p
er c
ont
r
o
l
.
Ho
we
ver
,
fo
r M
> 3 and app
l
i
cat
i
ons i
n
v
o
l
v
ed i
n
active power t
r
ans
f
er, suc
h
a
s
m
o
tor
driv
es, th
ese m
u
lt
ile
v
e
l co
nv
erters
all req
u
i
re either iso
l
ated
d
c
p
o
wer
sources or a com
p
licated voltage bala
nci
n
g circuit and control schem
e
to
support and
main
tain each volta
ge
lev
e
l. In
th
is
asp
ect, th
e th
ree ex
istin
g mu
ltilev
e
l co
nv
erters are n
e
ither op
erab
le
no
r co
m
p
lete fo
r
real
(activ
e) power co
nv
ersi
o
n
b
e
cau
se th
ey all
d
e
p
e
nd
on
ou
tsid
e circu
its for vo
ltag
e
b
a
lancin
g
[2
]. Mu
ltilev
e
l
i
nve
rt
ers
pr
od
uce a st
ep
ped
out
put
phas
e
v
o
l
t
a
ge wi
t
h
a
r
e
fi
ne
d ha
rm
oni
c pro
f
i
l
e
w
h
e
n
com
p
are
d
t
o
a t
w
o-
l
e
vel
i
nvert
er
-f
ed dri
v
e sy
st
em
. Howe
ve
r, these confi
g
ura
tions are also c
o
m
p
l
e
x for
hi
g
h
er n
u
m
b
er of
l
e
vel
s
.
Th
e three-lev
e
l in
v
e
rter is
realized
by
co
nn
ect
i
ng t
w
o 2
-
l
e
vel
i
nve
rt
ers i
n
casca
de. T
h
i
s
t
h
ree
-
l
e
vel
i
n
vert
er
st
ruct
u
r
e
doe
s
not
s
h
ow t
h
e v
o
l
t
a
ge fl
uct
u
at
i
ons
o
f
t
h
e
ne
ut
ral
p
o
i
n
t
,
as i
s
ol
at
ed
po
wer
s
u
p
p
l
i
e
s are em
pl
oy
ed
to power the i
n
dividual
inv
e
r
t
er
s.
[3
].
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-86
94
I
J
PED
S
Vo
l.
4
,
No
.
3
,
Sep
t
em
b
e
r
2
014
:
29
9 – 307
30
0
Fo
r m
a
n
y
ap
p
l
icatio
n
s
, to
g
e
t
m
a
n
y
sep
a
rate DC so
urces is d
i
fficu
lt, an
d
t
o
o
m
a
n
y
DC so
urces will
require m
a
ny long cables a
n
d could lead t
o
voltage
unbalance am
ong the DC source
s [4]. To
reduce the
num
ber of DC
sources and s
e
m
i
conductor switches re
quired, when the
cascaded
m
u
ltilevel conve
rter is
ap
p
lied
to
a mo
tor d
r
i
v
e, a sch
e
m
e
is p
r
op
osed
in
th
is p
a
per, th
at allo
ws
th
e u
s
e of
two
une
q
u
al
vol
t
a
g
e
DC
sources a
n
d
ei
ght
switch
e
s t
o
g
e
n
e
rate
7
level eq
u
a
l step
mu
ltile
v
e
l in
v
e
rter ou
tpu
t
.
Whereas th
e conv
en
tio
n
a
l
cascad
ed
m
u
lt
ilev
e
l in
v
e
rter requ
ires
three
equal
v
o
l
t
a
g
e
DC
so
urces
and
twelve
switch
e
s to
g
e
n
e
rate
7
lev
e
ls. Th
is sch
e
m
e
p
r
o
v
i
d
e
s th
e cap
ab
ility
to
p
r
odu
ce h
i
g
h
e
r vo
ltag
e
s
at h
i
g
h
e
r sp
eed
s
(wh
e
re th
ey are
neede
d
) wi
t
h
a l
o
w s
w
i
t
c
hi
ng
fre
q
u
ency
,
whi
c
h has i
n
here
nt
l
o
w
sw
i
t
c
hi
ng l
o
sses
and
hi
g
h
c
o
n
v
e
rsi
o
n
efficiency. For
electric/hybr
i
d
electric ve
hicle m
o
tor drive
applicatio
n
s
,
on
e
H
-
b
r
i
d
g
e
s an
d fo
ur
sw
itches fo
r
cascad
ing
t
h
e
b
a
tteries fo
r each
p
h
a
se is a
go
od
t
r
ad
eo
ff
b
e
tween
p
e
rfo
r
m
a
n
ce, co
st and
reliab
ility.
2.
MULTILEVE
L
CASCADE
D
H-BRID
GE
S IN
VE
RTER
STR
UCT
U
R
E
To
op
erate a cascad
ed
m
u
ltil
ev
el inv
e
rter
usin
g tw
o
u
n
e
qu
al DC
source, [5
]
p
r
op
o
s
ed
to use th
e
first
DC s
o
ur
ces (i.e
., t
h
e
b
a
ttery
connect
ed to fi
rst
H-bridge,
H
1
) as
V
dc
an
d th
e m
a
g
n
itud
e
of
v
o
ltag
e
of
seco
nd bat
t
e
ry
as
2
V
dc
.To
u
nderstand
th
e concep
t, co
nsid
er
a cas
cad
ed
m
u
ltilev
e
l in
v
e
rter
with
two
H-brid
g
e
s
as sh
ow
n i
n
Fi
gu
re
1. T
h
e D
C
sou
r
ce f
o
r t
h
e fi
r
s
t
H-
b
r
i
d
ge (
H
1
) is a
b
a
ttery o
r
fu
el cell V
1
with
an
ou
tpu
t
vol
t
a
ge of V
dc
, and the
DC s
o
urce for t
h
e s
econd
H-bri
d
ge (H
2
) is
V
2
with
an
ou
tpu
t
vo
ltag
e
of V
dc
/2. Th
e
o
u
t
p
u
t
vo
ltag
e
o
f
th
e cascad
e
d
m
u
ltilev
e
l in
v
e
rter is:
t
V
t
V
t
V
2
1
(
1
)
Fig
u
re
1
.
Sing
l
e
ph
ase st
ru
ct
ure
o
f
a Mu
ltilev
e
l
cascade
d
H-
bri
dge
s
i
n
vert
e
r
Fig
u
re
2
.
Mu
ltilev
e
l con
v
erter ou
tpu
t
with two
une
q
u
al
bat
t
e
ri
es
B
y
gi
vi
n
g
t
h
e
t
r
i
gge
ri
n
g
pul
s
e
s t
o
t
h
e s
w
i
t
c
hes
of
H
1
ap
pr
op
ri
at
el
y
,
t
h
e out
put
vol
t
a
ge
V
1
can
be
m
a
de eq
ual
t
o
V
dC
, 0,
or -V
dC
. wh
ile th
e
o
u
t
p
u
t
vo
ltag
e
of
H
2
i.e.,
V
2
ca
n
be
m
a
de eq
u
a
l
t
o
2V
dc
, 0
,
or
–
2V
dc
by
gi
vi
n
g
t
h
e t
r
i
g
geri
ng
pul
ses t
o
t
h
e s
w
i
t
c
hes
of
H
2
app
r
op
ri
at
el
y
.
There
f
ore,
t
h
e out
put
vol
t
a
ge of
t
h
e
conve
r
ter can
have the
values, (2V
dc
+V
dc
),
2
V
dc
, V
dc
, 0,
-V
dc
, -
2
V
dc
a
nd
-3
V
dc
(-
V
dc
-2
V
dc
) whic
h are 7
pos
si
bl
e
out
put
l
e
vel
s
.
Fi
g
u
re
2 s
h
o
w
s
t
h
e
7 l
e
vel
eq
ual
st
e
p
o
u
t
p
ut
v
o
l
t
a
ge
wa
vef
o
rm
[5]
.
Th
e si
g
n
i
ficant ad
v
a
n
t
ag
es
o
f
m
u
ltilev
e
l co
nfigu
r
a
tion
are,
vo
ltag
e
sh
ari
n
g bo
th statically an
d
dy
nam
i
cal
ly
and i
t
pr
od
uce
s
bet
t
e
r vol
t
a
ge wa
vef
o
rm
s wi
t
h
l
e
ss harm
oni
c cont
en
t
s
. One pa
rt
i
c
ul
ar
d
i
sadv
an
tag
e
o
f
cascad
ed
H-b
r
i
d
g
e
s m
u
l
tilev
e
l in
v
e
rt
er is th
at, it i
n
creases
great
er nu
m
b
er
o
f
po
wer
sem
i
cond
uct
o
r
swi
t
c
hes.
The w
o
rk
pr
oposed
in
[
6
] r
e
du
ces th
e nu
mb
er
of
sw
itch
e
s, th
eir
g
a
te dr
iv
ers,
co
m
p
ared
with th
e ex
istin
g mu
ltilev
e
l in
v
e
rter co
un
terp
arts with
h
a
rm
o
n
i
c profile i
m
p
r
ove
m
e
n
t
.
3.
CASCADE
D
HALF
-B
RIDGE
–
BASE
D
MULTI
LEV
EL DC LI
N
K
INV
E
RTER
STRU
C
T
UR
E
WITH UNE
Q
UAL VOLT
A
G
E
SO
U
RCE
S
Th
e
work
pro
p
o
s
ed
in
[6
]
u
tilizes th
ree
b
a
tteries and
ten
switch
e
s to g
e
nerate sev
e
n
voltag
e
lev
e
ls
p
e
r
p
h
a
se. Th
i
s
p
a
p
e
r proposes a sch
e
m
e
in
w
h
ich
on
ly
tw
o
b
a
tteries an
d
eigh
t sw
i
t
ch
es are u
tilized
to
gene
rat
e
sam
e
num
ber
of
v
o
l
t
a
ge l
e
vel
s
pe
r
pha
se an
d
i
t
i
s
sho
w
n
i
n
Fi
gu
re
3.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
PED
S
I
S
SN
:
208
8-8
6
9
4
Multilevel
DC Link Inverter with
Reduce
d Sw
itches and Batteries
(Y.
R. Manjunat
ha)
30
1
Fig
u
re 3
.
7-l
e
vel
C
a
scad
ed
m
u
ltil
ev
el
DC lin
k inv
e
rt
er with
u
n
e
qu
al
so
urce
The
casca
de
d Mu
lti
Level
D
C
L
i
n
k
(
M
LD
C
L
)
inv
e
rter wi
t
h
u
n
e
qual
vol
t
a
ge bat
t
e
ri
es
co
nsi
s
t
s
o
f
hal
f
b
r
i
dge
cel
l
s
and
o
n
e
f
u
l
l
bri
d
ge cel
l
.
Ea
ch
hal
f
-
b
ri
dge
cel
l
has t
w
o s
w
i
t
c
hes
S
1
and
S
2
.
T
h
ey
operate
in
a t
oggl
e fas
h
i
o
n. T
h
e
cell
sou
r
ce
is
b
y
p
a
sse
d
w
h
e
n
S
1
i
s
on
and
S
2
i
s
o
f
f.
T
h
e
cell source
adds
to the D
C
lin
k
vo
ltag
e
wh
en
S
1
i
s
o
f
f
a
nd
S
2
i
s
on. T
h
e
hal
f
bri
d
ge cel
l
produces
DC bus
vol
t
a
ge
w
a
v
e
f
o
r
m
i
n
t
h
e
sha
p
e
o
f
staircase and the
full bri
d
ge
inve
rter cell
altern
ates t
h
e
voltag
e
po
la
rity
to
prod
u
ce a
n
AC
vol
t
a
ge
of
st
ai
r
case
wa
ve
fo
rm
.
Si
n
g
l
e
-p
has
e
b
r
id
g
e
inv
e
r
t
er
c
o
n
t
a
i
n
s
fo
ur
swi
t
c
he
s fr
om
S
a
, S
b
, S
c
and S
d
.
Tabl
e 1. Swi
t
c
hi
n
g
Pat
t
e
r
n
F
o
r
C
a
scade
d
H
-
B
r
i
d
ge
M
l
dci
W
i
t
h
Une
q
u
a
l
Vo
ltag
e
So
urces—Sev
e
n Level
Levels
S
1
S
2
S
3
S
4
S
a
S
b
S
c
S
d
V
R
L
1
on
of
f
of
f
on
on
of
f
of
f
on
V
dc
2
of
f
on
on
of
f
on
of
f
of
f
on
2V
dc
3
of
f
on
of
f
on
on
of
f
of
f
on
3V
dc
4
o
ff o
ff o
ff o
ff
o
ff o
ff o
ff o
ff
0
V
5
on
of
f
of
f
on
of
f
on
on
of
f
-
V
dc
6
of
f
on
on
of
f
of
f
on
on
of
f
-
2
V
dc
7
of
f
on
of
f
on
of
f
on
on
of
f
-
3
V
dc
Tabl
e
1 s
h
o
w
s swi
t
c
hi
ng
p
a
t
t
e
rn f
o
r cas
caded
H
-
bri
d
g
e
M
L
DC
i
nve
rt
er
wi
t
h
une
qual
v
o
l
t
a
g
e
sources
. Specifically, the
MLDCL for
m
ed by the
2
ha
l
f
-
b
ri
dge
c
e
l
l
s
provi
d
es a
stairc
ase-wa
ve
form
i
n
t
h
e
dc-
b
us
vol
t
a
g
e
of
3
step
s
to
th
e
fu
ll b
r
i
d
g
e
inv
e
rter,
wh
ich
i
n
tu
rn
al
t
e
rnat
es
t
h
e
vol
t
a
ge p
o
l
a
ri
t
y
to
pr
od
u
c
e
an
ac
v
o
lta
g
e
V
an
of a
staircas
e sha
p
e
with
7
le
v
e
l
s
.
4.
CO
MP
ARI
SI
ON O
F
ML
DCL I
N
VER
TER WITH
UNEQ
U
AL
SOU
R
C
ES A
ND E
X
ISTI
NG
CO
UNTE
R
P
ARTS
Th
e m
u
lti
lev
e
l d
c
-link
in
v
e
rt
er effectiv
ely redu
ces
t
h
e
nu
m
b
er of swi
t
c
hes an
d t
h
ei
r
gat
e
dri
v
ers
.
Cascad
ed
m
u
ltilev
e
l in
v
e
rter
requ
ires
2
* (m
-1
) n
u
m
b
er of
swi
t
c
hes an
d t
h
e cascade
d
M
L
DC
L re
qui
re onl
y
(m
+3) num
ber
of
swi
t
c
hes
.
Whe
r
eas t
h
e p
r
o
p
o
sed M
L
D
C
L i
nve
rt
er
wi
t
h
u
n
e
qual
vol
t
a
ge so
u
r
ces r
e
qui
re
s
just (m
+8) switches,
Where
m
takes the
values
0,
2, 4, 6,
8,.
., f
o
r
7, 15, 31, 63,
.., s
w
itching levels
resp
ectiv
ely.
In
add
ition
,
th
e n
e
w m
u
lti
lev
e
l d
c
-link
inv
e
rt
er sav
e
s th
e cost o
f
t
h
e inv
e
rt
er circu
it b
y
hav
i
ng
an a
dditional
m
odule of single-phase
full bri
dge i
n
vert
er.
W
ith hi
ghe
r
voltage
levels, only two
swit
ches a
r
e
en
oug
h fo
r
fabricatin
g
each
bridg
e
in
m
u
ltil
ev
el d
c
-lin
k
(MLDCL)
with four switch
e
s in
sing
le
p
h
a
se fu
ll
bri
dge
i
n
vert
er
.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
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088
-86
94
I
J
PED
S
Vo
l.
4
,
No
.
3
,
Sep
t
em
b
e
r
2
014
:
29
9 – 307
30
2
Tabl
e
2. C
o
m
pone
nt
C
o
u
n
t
C
o
m
p
ari
s
on
—S
even
Le
vel
s
Types of
Invert
er
No.
of
Levels
No. of Batt
eries
No. of Sw
itches
Conventio
nal Multi Level
Inverter
wi
th equal source voltages
7 3
12
15
7
28
31
15
60
63
31
122
M
L
DC
L
I
nver
t
er
with equal sour
ce
voltages
7 3
10
15
7
18
31
15
34
63
31
65
M
L
DC
L
I
nver
t
er
with unequal volta
ge sour
ces
7 2
8
15
3
10
31
4
12
63
5
14
Fi
gu
re
4.
C
o
m
p
ari
s
on
o
f
req
u
i
red
n
u
m
b
er o
f
Swi
t
c
he
s
Fig
u
r
e
4
shows th
e r
e
du
ctio
n in
nu
m
b
er
of
sw
itc
h
e
s in th
e MLDCL inv
e
rter with un
equ
a
l vo
ltag
e
so
urces. Th
e
n
u
m
b
e
r
o
f
levels as co
m
p
ared
to th
e
Conv
en
tion
a
l M
u
lti Lev
e
l
Inv
e
rt
er
with
eq
u
a
l
so
urce
vol
t
a
ge
s an
d M
L
DC
L In
ve
r
t
er wi
t
h
eq
ual
sou
r
ce v
o
l
t
a
ge
s th
e MLDCL in
v
e
rter with
un
equ
a
l vo
ltag
e
so
urces
schem
e
considerably re
duces
th
e
nu
m
b
er o
f
switch
e
s.
Fig
u
r
e
5
shows
th
e r
e
d
u
c
tion
in
nu
m
b
er
of
b
a
tter
i
es in th
e MLDCL inv
e
rter
with
un
equ
a
l vo
ltag
e
sources
. The num
b
er of batte
ries as
co
m
p
ared
to
t
h
e Conv
en
tion
a
l Mu
lt
i Lev
e
l In
v
e
rter with
equ
a
l so
urce
vol
t
a
ge
s an
d M
L
DC
L In
ve
r
t
er wi
t
h
eq
ual
sou
r
ce v
o
l
t
a
ge
s th
e MLDCL in
v
e
rter with
un
equ
a
l vo
ltag
e
so
urces
schem
e
considerably re
duces
the
num
b
er of batteries.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
PED
S
I
S
SN
:
208
8-8
6
9
4
Multilevel
DC Link Inverter with
Reduce
d Sw
itches and Batteries
(Y.
R. Manjunat
ha)
30
3
Fig
u
r
e
5
.
Co
mp
ar
iso
n
of
r
e
quir
e
d
nu
m
b
er
of Batter
i
es
5.
MO
DUL
ATI
O
N A
N
D
SWI
T
CHI
N
G CO
NTROL
Gene
ral
l
y
, t
r
a
d
i
t
i
onal
P
W
M
cont
rol
m
e
t
hods
an
d s
p
ac
e vect
o
r
P
W
M
m
e
t
hods a
r
e ap
pl
i
e
d t
o
m
u
ltilevel inverter m
odulation contro
l. The
disadva
n
tage of
the traditiona
l PW
M m
e
thods is the powe
r loss
i
n
t
h
e swi
t
c
he
s due t
o
t
h
e
h
i
gh s
w
i
t
c
hi
n
g
fre
que
ncy
[
7
]
-
[
9]
. F
o
r t
h
ese
reaso
n
s
,
l
o
w
s
w
i
t
c
hi
n
g
f
r
eq
u
e
ncy
cont
rol
m
e
t
hod
s, suc
h
as a fu
ndam
e
nt
al
freq
u
ency
m
e
t
hod [1
0]
, an
d t
h
e act
i
v
e harm
oni
c el
im
i
n
at
i
on m
e
t
h
o
d
[1
1]
has be
en
pr
o
pose
d
f
o
r
m
o
t
o
r dri
v
e a
p
pl
i
cat
i
ons. T
h
i
s
i
s
t
h
e sim
p
l
e
st
swi
t
c
hi
n
g
cont
rol
m
e
t
hod
fo
r t
h
e
pr
o
pose
d
m
u
l
t
i
l
e
vel
m
o
t
o
r dri
v
e. It
al
so
i
s
an effect
i
v
e m
odul
at
i
o
n
cont
r
o
l
m
e
t
hod
fo
r t
h
e p
r
op
ose
d
Mu
ltilev
e
l D
C
l
i
n
k
i
n
v
e
r
t
e
r
with
un
equ
a
l
v
o
ltag
e
so
urces m
o
to
r driv
e.
The
Fo
uri
e
r se
ri
es ex
pa
nsi
o
n
of
t
h
e
7-l
e
vel
e
qual
st
ep
o
u
t
p
u
t
vol
t
a
ge
wa
ve
fo
rm
i
s
:
t
n
n
n
n
n
V
t
V
n
dc
sin
cos
cos
cos
4
3
2
1
...
5
,
3
,
1
(2)
Whe
r
e ‘
n
’ i
s
t
h
e or
de
r of
ha
rm
oni
c i
n
t
h
e
out
put
v
o
l
t
a
ge
of m
u
l
t
i
l
e
vel
i
nve
rt
er. Gi
ve
n a desi
re
d
fund
am
en
tal v
o
ltag
e
V
1
, on
e
wan
t
s to
d
e
termin
e th
e switch
i
ng
ang
l
es
θ
1
,
θ
2
,
θ
3
so that
t
V
t
V
sin
1
,
and s
p
eci
fi
c hi
ghe
r ha
rm
oni
cs of
t
n
V
are eliminated [6]-[8].
For t
h
re
e
-
phas
e m
o
tor
drive
applications,
t
h
e
t
r
i
p
l
e
n har
m
oni
cs
i
n
eac
h pha
se need
not
be
co
nsi
d
e
r
ed as t
h
ey aut
o
m
a
tically
can
cel in
th
e lin
e-to
-lin
e
vol
t
a
ge
s. T
h
e l
o
we
r or
de
r ha
rm
oni
cs can b
e
el
im
i
n
at
ed b
y
choo
si
n
g
p
r
ope
r val
u
es f
o
r
θ
1
,
θ
2
and
θ
3
in
th
e
fo
llowing
equ
a
tio
n
s
:
0
7
cos
7
cos
7
cos
0
5
cos
5
cos
5
cos
cos
cos
cos
3
2
1
3
2
1
3
2
1
m
(
3
)
Th
is is a system o
f
th
ree tran
scen
d
e
n
t
al equ
a
tio
ns in
th
e
th
r
ee unk
now
ns
θ
1
,
θ
2
, and
θ
3
. There a
r
e
m
a
ny
way
s
o
n
e
can s
o
l
v
e
fo
r
t
h
e an
gl
es [
1
0
]
, [1
2]
-[
1
4
]
He
re t
h
e
resul
t
a
nt
m
e
t
hod
[
11]
,
[
15]
was
used
t
o
fi
nd
t
h
e s
w
i
t
c
hi
n
g
a
ngl
es
. T
h
e m
odul
at
i
o
n i
n
de
x
m
i
s
defi
ned
as
:
dc
V
V
m
2
1
(4)
An
d t
h
e t
o
t
a
l
h
a
rm
oni
c di
st
o
r
t
i
on
(T
HD
)
u
p
t
o
t
h
e
5
0
th
harm
oni
c
(
o
d
d
,
n
o
n
-
t
ri
pl
en)
i
s
c
o
m
put
e
d
as:
1
2
49
2
7
2
5
......
V
V
V
V
THD
(
5
)
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-86
94
I
J
PED
S
Vo
l.
4
,
No
.
3
,
Sep
t
em
b
e
r
2
014
:
29
9 – 307
30
4
6.
S
I
M
U
L
A
T
I
O
N
AND E
X
P
E
R
I
M
E
N
T
A
L
R
E
S
U
L
T
S
To val
i
d
at
e t
h
e pr
op
ose
d
M
L
DC
L i
n
vert
e
r
wi
t
h
u
n
e
qua
l
vol
t
a
ge s
o
u
r
ces, a
m
o
t
o
r
dri
v
e co
nt
r
o
l
schem
e
has be
en de
vel
o
pe
d.
The s
w
i
t
c
hes u
s
ed f
o
r t
h
i
s
i
n
v
e
rt
er are t
h
e I
G
B
T
s G
T
6
0
M
3
0
3
(
T
os
hi
ba
M
a
ke)
.
The
gat
i
n
g p
u
l
s
es are
ge
nerat
e
d
by
m
i
crocont
r
o
l
l
e
r b
o
a
r
d
.
A
3-
p
h
ase i
n
duct
i
o
n m
o
t
o
r
i
s
sel
ect
ed wi
t
h
t
h
e
speci
fi
cat
i
o
ns s
h
o
w
n i
n
t
h
e
Ta
bl
e 3
bel
o
w
.
A
l
so m
o
t
o
r m
o
d
e
l
i
s
de
vel
o
ped
usi
n
g
M
A
TL
AB
Si
m
u
l
i
nk.
Table 3. Speci
fication
of
m
o
tor
S. No.
Type of the
m
o
tor
3-
φ
Induc
tion
m
o
tor
1
Rated Output Power
3700 watts (
5
HP)
2
Rated line to line v
o
ltage
415 volts
3
Rated Cur
r
e
nt
8.
4 am
ps
4
Nu
m
b
er
of Poles
4
5 Fr
equency
50
Hz
6
Rated Speed
1485 r
p
m
7
T
y
pe of winding
Y-
connected
The pa
ram
e
t
e
r
s
of t
h
i
s
m
o
t
o
r are cal
cul
a
t
e
d by
co
nd
uct
i
ng
No
-l
oa
d t
e
st
, B
l
ocked R
o
t
o
r t
e
st
an
d
Retard
ation
test. Th
is m
o
to
r
m
o
d
e
l is si
m
u
lated
u
s
in
g
M
A
TLAB and
the
si
m
u
lated
re
s
u
lts are c
o
m
p
are
d
with
that of
practica
l
results. It is found
that thes
e two res
u
lts a
r
e ve
ry close to each
othe
r. T
h
en t
h
e m
o
tor m
odel
is si
m
u
lated
wi
th
th
e
propo
sed
cascad
e
d
m
u
ltilev
e
l in
v
e
rter.
Tim
e
F
i
gu
re 6.
S
t
ato
r
cu
r
r
e
n
t, m
o
to
r fe
d
f
r
o
m
S
P
WM
I
nve
rter
Fi
gu
re
7.
St
at
o
r
c
u
r
r
ent
,
m
o
t
o
r fe
d
fr
om
M
L
In
vert
e
r
F
i
gu
re
8.
O
u
t
p
ut
v
o
l
t
a
ge
wa
v
e
fo
rm
of M
L
I
(
3
pha
se)
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
PED
S
I
S
SN
:
208
8-8
6
9
4
Multilevel
DC Link Inverter with
Reduce
d Sw
itches and Batteries
(Y.
R. Manjunat
ha)
30
5
Fi
gu
re
6 s
h
ow
s t
h
e st
at
o
r
c
u
rre
nt
s
of t
h
ree
p
h
ase i
n
d
u
ct
i
o
n
m
o
t
o
r
on
no
-l
oa
d
fed
f
r
o
m
2 l
e
vel
i
nve
rt
er.
I
n
t
h
i
s
fi
g
u
re
eve
n
t
h
o
u
g
h
t
h
e
wa
v
e
fo
rm
l
ooks cl
ose t
o
si
n
u
s
o
i
d
al
, i
t
has
di
st
or
t
i
on.
Fi
g
u
re
7
i
s
t
h
e
st
at
or cur
r
e
n
t
s
of t
h
e sam
e
mot
o
r fed
wi
t
h
7
l
e
vel
i
nvert
er.
It
i
s
obser
ve
d t
h
at
t
h
e di
st
ort
i
on i
s
alm
o
st
reduce
d
.
Hen
ce t
h
e m
o
t
o
r
run
s
sm
o
o
t
h
l
y an
d
safely. Fig
.
8
is th
e t
h
ree
p
h
a
se ou
t
p
u
t
v
o
ltag
e
o
f
m
u
l
tilev
e
l (7
Lev
e
l)
in
v
e
rter
with
t
w
o un
eq
u
a
l
voltag
e
s.
7.
EX
PER
I
M
E
NTA
L
VA
LIDA
TION
To
ex
p
e
rim
e
n
t
ally v
a
lid
ate th
e p
r
op
o
s
ed
m
u
ltilev
e
l in
v
e
rter, a
p
r
o
t
o
t
yp
e
MLDCL inv
e
rt
er with
t
w
o
une
q
u
al
bat
t
e
ri
es per
p
h
ase a
nd
8
IGB
T
s
a
s
swi
t
c
hi
n
g
de
vi
ces. T
h
e f
u
n
d
am
ent
a
l
freq
u
e
ncy
o
f
t
h
e i
n
vert
er
out
put
i
s
5
0
H
z.
F
i
g
u
re
9
sh
o
w
s t
h
e
bl
oc
k
di
a
g
ram
of t
h
e e
x
peri
m
e
nt
al
set
up.
F
i
gu
re
9. B
l
oc
k
di
ag
ram
of t
h
e ex
peri
m
e
nt
al set
u
p
Th
e m
i
cr
o
c
on
t
r
o
ller
un
it is a PI
C
18
F8
722 micr
o
c
on
tro
ller
.
I
t
is an
8
0
p
i
n TQ
FP p
a
ck
ag
e n
e
ed
s
+1
2V
D
C
supply f
o
r
its
w
o
r
k
i
n
g an
d op
er
ates at a
f
r
e
qu
en
cy o
f
40
M
H
z.
Th
is m
i
cr
o
c
on
t
r
o
ller h
a
s
1
28K
B
o
f
p
r
og
r
a
m
m
e
mo
r
y
,
39
36
b
y
tes of
d
a
ta m
e
mo
r
y
an
d 102
4
b
y
tes of
d
a
ta
EPRO
M m
e
mo
r
y
.
I
t
also h
a
s 9
I
/
O
p
o
rts and
5
timers. Th
is micro
c
o
n
t
ro
ller is u
s
ed
to
im
p
l
e
m
e
n
t th
e con
t
ro
l alg
o
rith
m
(i.e. t
o
g
e
n
e
rate th
e
g
a
ting
pul
ses
)
f
o
r sw
i
t
c
hi
ng de
vi
ce
s i
n
t
h
e M
L
DC
L i
nvert
er
w
i
t
h
une
qual
v
o
l
t
a
ge so
urce
s
.
The gat
i
n
g pul
se
s
gene
rat
e
d
by
m
i
croco
n
t
r
ol
l
e
r can
n
o
t
be
co
nnect
e
d
di
rect
l
y
t
o
t
h
e
po
we
r sem
i
cond
uct
o
r
swi
t
c
hi
ng
d
e
vi
ces
.
Hen
ce th
e
d
r
i
v
er circu
it is in
tro
duce
d
bet
w
een m
i
croco
n
t
r
ol
l
e
r an
d M
L
DC
L i
nve
rt
er
wi
t
h
u
n
eq
ual
vol
t
a
ge
so
urces. Th
e
detailed
circu
it
d
i
agram
o
f
th
is driv
er un
it is sh
own
in Figure 10
.
Fig
u
r
e
1
0
.
G
a
te dr
iv
e circu
it fo
r IG
BT
Th
e driv
er circu
it co
n
s
ists of
an o
p
t
o
c
o
u
p
l
er (PC
81
7) t
o
whi
c
h t
h
e g
a
t
i
ng p
u
l
s
e ge
nerat
e
d by
micro
c
on
tro
ller is g
i
v
e
n. Th
i
s
op
to
co
up
ler
is u
s
ed
fo
r isolatio
n
pu
rpo
s
e. O
u
t
p
u
t
of
op
t
o
coup
ler
is
p
a
ssed
th
ro
ugh
a bu
ffer to
im
p
r
o
v
e
th
e ou
tpu
t
d
r
i
v
e cap
acity o
f
th
e driv
er circuit so
th
at th
e switch
i
ng
d
e
v
i
ce can
t
u
r
n
o
n
q
u
i
c
kl
y
wi
t
hout
del
a
y
.
The dri
v
er
ci
rcui
t
i
s
for
o
n
l
y
one s
w
i
t
c
h
i
ng de
vi
ce. M
L
DC
L i
n
vert
er
wi
t
h
u
n
e
qu
al
v
o
ltage sources
was
sh
own
i
n
Fi
g
u
re 3. Th
is
i
n
v
e
rter circu
it h
a
s
b
een
b
u
ilt using
90
0V, 60A
IGBTs
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-86
94
I
J
PED
S
Vo
l.
4
,
No
.
3
,
Sep
t
em
b
e
r
2
014
:
29
9 – 307
30
6
(i
.e. C
T
6
0
A
M
-
18
F o
f
M
i
t
s
ubi
shi
m
a
ke) as swi
t
c
hi
n
g
de
vi
c
e
s. These
de
vi
ces have a m
a
xi
m
u
m
t
u
rn
O
N
t
i
m
e
o
f
0.75
μ
s a
n
d
t
u
r
n
of
f t
i
m
e of 0.
7
μ
s.
8.
CO
NCL
USI
O
N
Th
is p
a
p
e
r d
e
v
e
lop
e
d
a M
u
ltilev
e
l DC Lin
k
In
v
e
rter
with
un
equ
a
l vo
l
t
ag
e sou
r
ces
m
o
to
r d
r
iv
e
cont
rol schem
e
that require
d only two-battery source
for each phase
. A 7-le
vel equal step output voltage
switch
i
ng
con
t
ro
l m
e
th
o
d
h
a
s b
e
en
app
lied to
t
h
e m
o
to
r
d
r
i
v
e. M
u
ltilev
e
l DC Li
n
k
Inv
e
rter
with
u
n
eq
u
a
l
vol
t
a
ge
so
urc
e
s
i
s
sim
u
l
a
t
e
d usi
n
g M
A
TL
AB
Si
m
u
l
i
nk.
The
har
d
wa
r
e
pr
ot
ot
y
p
e i
s
im
pl
em
ent
e
d usi
n
g
Micro
c
on
tro
ller. A sev
e
n
lev
e
l-cascad
e
d
m
u
l
tilev
e
l DC
-lin
k
inv
e
rter with
un
equ
a
l
v
o
ltag
e
sou
r
ces is
success
f
ully fabricated a
n
d
tested. T
h
e
ne
w ML
DCL i
n
verter with unequal
voltage sources
nee
d
s
least
num
ber o
f
co
m
ponent
s t
h
an
t
h
e ot
her co
u
n
t
e
r
p
art
exi
s
t
i
n
g m
u
l
t
i
l
e
vel
i
n
vert
er
s fo
r t
h
e
sam
e
l
e
vel
of out
p
u
t
wav
e
fo
rm
. By
in
creasi
n
g the nu
m
b
er of l
e
v
e
ls of t
h
e
Mu
ltilev
e
l DC Lin
k
Inv
e
rter with
un
equ
a
l
vo
ltag
e
sou
r
ces
swi
t
c
h
e
s, gat
e
d
r
i
v
e
r
and
bat
t
e
ry
a
r
e
re
duce
d
wi
t
h
bet
t
e
r out
put
w
a
vef
o
rm
.
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a
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r a
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u
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vel converters usi
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u
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I
J
PED
S
I
S
SN
:
208
8-8
6
9
4
Multilevel
DC Link Inverter with
Reduce
d Sw
itches and Batteries
(Y.
R. Manjunat
ha)
30
7
BIOGRAP
HI
ES OF
AUTH
ORS
Y.
R.
M
a
njunatha
di
d hi
s BE
from My
sor
e
Uni
v
e
r
si
ty
in E
l
ec
tric
al
And E
l
ect
roni
c
s
Engineering fro
m J.N.N Colleg
e of Eng
i
n
eer
in
g,
Shimoga. He has comp
le
te
d his Ma
ste
r
of
Techno
log
y
in
Power Electr
onics
Engineer
i
ng at B
.
M.S
Colleg
e of En
gineer
ing und
er
Vis
v
es
va
ra
ya
T
ech
nolo
g
i
c
a
l
Unive
r
s
i
t
y
Be
lga
u
m
.
Dr. M
a
n
j
u
n
tha h
a
s
ob
ta
in
ed his
Do
ctor
a
l
Degre
e
from
V.
M
.
U, S
a
l
e
m
in El
ec
tri
c
al En
gin
eer
ing
.
His
are
a
of inte
res
t
s
i
n
power e
l
e
c
tr
oni
cs
modeling, power eng
i
n
eer
ing
in
the fi
eld of ene
r
g
y
con
v
ers
i
on
,
Distribution S
y
s
t
em Automation
and Des
i
gnin
g
of P
o
wer El
e
c
tr
onics
Con
v
er
te
r
s
. He is
curr
en
tl
y Ch
airm
an a
nd Head of
the
Depar
t
men
t
in
Departmen
t
of
E
l
e
c
tr
ic
al
Eng
i
ne
er
i
ng at
U.V
.
C
.
E
,
Bang
alo
r
e
Univ
ers
i
t
y
.
B.
A.
Anand
did his BE fr
om V
i
s
v
es
v
a
r
a
ya
Tec
h
n
o
lo
g
i
c
a
l Univers
i
ty
during
2004-08 in
El
ec
tri
c
al
and
El
e
c
tro
n
i
c
s
Engi
ne
eri
ng f
r
o
m
S
r
i Kris
h
n
a I
n
s
t
i
t
ut
e
o
f
T
ech
nolo
g
y
,
Chikk
a
banav
a
r
a
, Bang
alore. He has completed
hi
s Master of En
gineer
ing in Po
wer and En
erg
y
S
y
stems at Univ
ersity
Visvesv
a
r
a
y
a
Co
lleg
e
of
Engineering [U.V..C
.E]
during
2010-201
1. Mr
.
B
.
A.
Ana
n
d i
s
o
b
t
ai
ni
n
g
hi
s Do
c
t
or
al
De
gr
ee
fr
om Visveswar
a
y
a
Techno
logical Univ
ersity
in
Depar
t
men
t
of
Electrical
Eng
i
neering
.
H
e
is
c
u
rre
n
tly
working
a
s
Assistant Profe
ssor of
El
ec
tri
c
al
Eng
i
n
eer
ing
in D
e
p
a
rt
m
e
nt of
Agri
cu
l
t
ura
l
Eng
i
ne
er
in
g at
Univ
ers
i
t
y
of Agri
cu
ltur
a
l
Sciences-Bangalore, G.K.V
.
K Ca
mpus, Ban
g
alore-5600
65. His inter
e
sts ar
e
in th
e ar
ea of
power s
y
s
t
em o
p
er
ation and
co
ntro
l, Substati
o
n
automatio
n and Power distr
i
butio
ns s
y
stem
studies.
Evaluation Warning : The document was created with Spire.PDF for Python.