Int ern at i onal  Journ al of  P ower E le ctr on i cs a n d  Drive  S ystem s   ( IJ PEDS )   Vo l.   12 ,  No.   1 ,  M a r 202 1 , p p.  345 ~ 355   IS S N:  20 88 - 8694 ,  DOI: 10 .11 591/ ij peds . v12.i 1 . pp 3 45 - 355          345       Journ al h om e page :  http: // ij pe ds .i aescore.c om   State   f eedback   co ntrol   of   advanc ed   stati c   var   com pensato r     using   a   f ive - l evel   NPC   i nv er t er   t op ology       Mansour   Be n yami na 1 ,   Ali   Tahri 2 ,   Ab del ka der   Bo ukor tt 3   1,3 Depa rtment   of   Elec tr ical   Engi n ee ring ,   Abde lhamid   Ibn   Badi s   Univer sity   of   Mos ta gan em ,   Mos tagane m ,  Alg eri a   2 Depa rtment   of   El e ct rot ec hni cs,   Univer sity   of   Sc ie nc es   and   Tech nology   of   Or an   US TO - MB ,  Bir   El   Dj ir ,   Alger i a       Art ic le   In f o     ABSTR A CT   Art ic le   hist or y:   Re cei ved   N ov   1 ,   20 20   Re vised   J an   9 ,   20 21   Accepte d   Fe b   8 ,   20 21       Thi s   p ape r   d ea l s   with   th e   mod el ing   and   cont r ol   of   an   adv anced   st at i c   var   com pensa tor   (A SV C)   using   a   fiv e - le v el   neut r al   p oint - clamp ed   (N PC )   volt ag e   source   inve r te r   (VS I).   Th e   non li ne ar   st ate   spa ce   mod el   of   th e   f ive - le ve l   ASVC   is   obta i ned   from   the   d - q   axi s   fr ame.   The   eff ec t ive n ess   of   thi s   com pensa tor   hi ghly   depe nds   on   the   cho ice   of   the   con trol   str at egy .   Th e   proposed   sta te   f ee dba ck   cont ro l   (SF C)   techniq ue   is   app li ed   to   adj ust   t he   ASVC   Var   flow   with   th e   AC   tr a nsmiss ion   net wo rk   and   a chieve   DC   volt ag e   ca pa ci tor   b al an ce .   The   dynamic   per form ance   of   the   ASVC   base d   SFC   cont roller   is   ev al ua te d   under   s eve ra l   oper at ing   condi ti ons .   Th e   simul a ti on   result s   de monstr at e   that   th e   pro posed   SFC   control   stra te gy   is   h ighl y   robust   com par ed   to   th e   conve nt iona l   Proportiona l - Inte gr a l   (PI)   con trol.   Ke yw or d s :   ASVC   M ulit il evel   in ve rter     Robust   c on t ro l   Stat e   feedbac k   con t ro l   This   is   an   open   acc ess   arti cl e   un der   the   CC   BY - SA   l ic ense .     Corres pond in g   Aut h or :   M a ns our   Be ny amina   Dep a rt me nt   of   Ele ct rical   Eng i neer i ng   FST   Fa culty ,   Abdelha mid   Ibn   Ba dis   U niv e r sit y   Sit e   1,   R oute   Be la hcel   27 000,   M ost aga nem,   Alge ria   Emai l:   mans ou r_be ny a mina @ yaho o.fr       1.   INTROD U CTION   The   sta ti c   com pensat ors   (S T ATCO M)s   are   importa nt   rea ct ive   com pens at ion   de vices   that   ha ve   bee n   us e d   in   powe r   sy ste ms   to   mai ntain   bus   volt age   at   a   c onsta nt   le vel,   im pro ve   the   tran sie nt   sta bili ty,   dam p   the   sy ste ms   an d   s uppress   volt age   flic ker   [1 ] - [ 4].   The   intr oduc ti on   of   m od e rn   s emic onduct or   dev ic es   in   the   desig n   of   pow er   el ect ronic   c onve rters   has   resu lt ed   in   a   s olid - sta te   Va r   so urce   with   a   simpler   str uctu re,   namely   t he   ASVC   [5 ] - [ 7].   An   A SV C   is   a   fu ll y   con t ro ll ed   s witc h   base d   c onve rter,   w hich   is   an   up gr a de   ve rsion   of   T he   Stat ic   Var   Co mp e ns at ors   (SVCs),   a   thyrist or - ba sed   co nv e rter.   Like   an   S VC,   t he   AS VC   pro vid es   a   co ntr ol la ble   par al le l   com pe ns at io n.   The   reacti ve   powe r   ge ner at io n   or   abs orptio n   by   an   ASVC   is   the   same   as   that   of   an   S VC.   The   A S VC   has   adv a ntage s   ov e r   a   c onve ntio na l   SV C   [8 ] - [ 11].   The   A SV C   us e   a   P ulse   Widt h   M od ulati on   ( P W M )   c on tr olle d   DC - AC   V SI   with   a   ca pacit or   as   a   DC   powe r   sto rag e   dev ic e.   Re cent ly,   the   mu lt il evel   PWM   c on ver te r   t opol ogy   ha s   dra wn   tr emen dous   i nterest   in   the   power   in du stry   since   it   ca n   easi ly   pro vide   the   hi gh   po w er   require d   f or   hi gh   po wer   a pp li cat io ns   for   su c h   us es   as   sta ti c   VAR   c ompen s at ion ,   act ive   powe r   filt e rs,   a nd   t he   c ontr ol   of   la r ge   m oto rs   by   high   powe r   adjusta ble   fr e quenc y   dr ive s.   The   m os t   popu la r   str uctu re   pr opos e d   as   a   t ra ns f ormerless   volt age   sou rce   i nv e rter   is   the   diode   cl ampe d   co nverte r   base d   on   the   neu t ral   point   cl ampe d   ( NP C)   conve rter   pr opos e d   by   Na bae   [12 ] ,   [ 13] .   It   has   the   ad va ntages   th at   the   blo c king   volt age   of   ea c h   s witc hi ng   de vice   is   one   hal f   of   DC - link   volt age,   and   the   harm on ic s   c onte nts   ou t put   volt ag es   are   lo we r   than   th os e   of   a   two - le vel   in ver te r   f or   t he   same   switc hing   f requen c y.   T he   N P C   in ver te r   has   the   dr a w back   of   the   unbalan ce   DC   ca pacit or s   vo lt age   when   us e d   Evaluation Warning : The document was created with Spire.PDF for Python.
                          IS S N :   2088 - 8 694   In t J   P ow  Ele c  &  D ri   S ys t,   V ol .  12 , N o.   1 ,  Ma rch  20 21   :   345   –   3 55   346   as   a   sta ti c   var   com pe ns at or.   Dif fer e nt   met hods   we re   pr opose d   to   s olv e   this   issue .   S ome   resea rc her s   ha ve   pro po se d   to   i ns ert   two   in duct ors   in   one   le g   to   balan ce   the   capaci tors   volt age   [14 ] ,   [ 15].   Othe rs   ha ve   introd uced   a   m od i fied   s witc hi ng   patte r n   a nd   impro ved   the   opti mize d   P W M   te chn i qu e   [16 ] ,   [ 17].   This   pap e r   pre sents   a   modeli ng   an d   a nal ys is   of   this   ne w   t yp e   of   five - le ve l   inv e rter   us e d   for   sta ti c   VAR   co mp e nsa ti on .   The   co nt ro l   desig n   is   ba sed   on   the   co nventio nal   pro portio nal - inte gral   (P I )   c ontr oller   a nd   the   sta te   fee dback   co ntr oller   (S FC)   c ontroll ers   to   adj us t   t he   A SV C   Var   f low   with   t he   AC   s ys te m .   T he   SF C   con t ro ll er   al s o   has   the   abili ty   to   bala nce   the   t otal   DC   ca pacit or s   volt age   wi thout   an y   e xtra   de vice   or   design   of   a   co mp le x   ci r cuit   or   opti mi zi ng   co ntr ol   method.   Fi nally,   s om e   sim ulati on   res ults   unde r   va rio us   transie nt   conditi ons   of   t he   pro po se d   A SV C   m odel   a nd   its   c on tr ol   a r e   giv e n   to   pro ve   their   e ff ect iv eness.       2.   OVERVIEW   AND   MO DE LING   OF   TH E   ASVC - BA S ED   FI VE - LE VEL   IN VE R TE R   The   ASVC   ci rcu it   c on sist s   of   t wen t y   fou r - pu lse   VSI   with   f our   DC   capaci to rs   a nd   a   PWM   modu la to r.   T he   A SV C   is   c onnecte d   to   the   transmissi on   li ne   is   via   a   co upli ng   tra nsfo r mer   w her e   Rs   and   Ls   are   the   co upli ng   tra nsfo rme r   a ct ive   losses   an d   le aka ge   res pe ct ively,   as   s hown   in   Fig ur e   1   [18 ] - [ 22] .           Figure   1.   P ow e r   ci rc uit   of   the   ASVC - based   fi ve - le vel   N PC - VS I   in ver te r       wh e re ,     I s,abc   ,   I L,abc   :   S uppl y   a nd   loa d   c urren ts .   I c,abc   :   ASVC   cu rrents .   V s,abc   :   Supp l y   vo lt age s.   V o,abc   :   Inver te r   ou t put   volt age.   V dc,i   :   Ca pacit or   vo lt ages   at   diff e ren t   le vels .   V dc   :   Total   DC   side   vo lt age   of   the   I nverter .   I dc,i   :   DC   side   c urren t.   C s   :   DC   side   ca pacit or.     2.1.    PW M   c ontr ol   str at e gy   of   th e   fi ve - le ve l   NP C - VS I   in vert er   In   t his   work,   t he   P W M   c on t ro l   strat e gy   for   a   five - le vel   i nv e rter   us es   a   sing le   ref e re nc e   an d   f our   carriers   si gn al s   as   de picte d   in   Fig ure   2 (a )   w her e   a   sin usoidal   ref e ren ce   s ign al   is   c on ti nuousl y   c ompar ed   to   four   (N - 1   in   ge ner al )   tria ngle   wav e f or m s   w he re   N   is   the   nu mb e r   of   le vel   of   the   i nv e rter.   One   of   a dv a nta ges   of   this   te ch nique   is   that   the   sig nif ic ant   ha rm on ic s   are   c oncent ra te d   at   the   car rier   f re qu e nc y   [23 ] - [ 26].   The   fr e quenc y   modu la ti on   i ndex   a nd   the   a m pl it ud e   m odulati on   in dex   are   gi ven   by   ( 1)     { = = 2     ( − 1 )   (1)     wh e re   f c   :   Fr eq ue nc y   of   car ries.   A c   :   Peak - to - pea k   a mp li tud e   of   ca r ries.       Evaluation Warning : The document was created with Spire.PDF for Python.
In t J  P ow Elec   & Dri S ys t   IS S N:  20 88 - 8 694       Sta te  fee dback  con tr ol  of adv anced  static  v ar   compe nsator  usi ng a fi ve - le vel  NPC  …   ( M anso ur Be ny am i na )   347   f s   :   Fr eq ue ncy   of   re fer e nce.   A s   :   Peak   am plit ud e   of   ref e ren c e.   The   mat hemat ic al   mo del   of   the   co nverter   is   dev el oped   us in g   s witc h   connecti on   f un ct io n   F ki   ,   ( k = a,b,c )   :   na mes   of   a rms   a nd   ( i = 0,1,2, 3,4 )   :   num be r   of   t he   f un ct io n.   T he   switc hi ng   f un ct io n,   is   ei th er   1   or   0   corres pondin g   to   on   a nd   off   s ta te s   of   s witc h   S ki   ,   ( k = a,b,c )   :   name s   of   ar ms   a nd   ( i = 1,2 , 3,4,5, 6,7,8)   :   num ber   of   the   s witc hes   of   one   arm .   Ta ble   1   li sts   the   s witc h   c onnecti on   f unct ion   of   one   le g   a nd   ou t pu t   volt age.       Table   1.   A   pos sible   switc h   co mb inati on   of   one   ph a se   le g   for   the   N PC - base d   five - le vel   in ve rter   F ki   S a1   S a2   S a3   S a4   S a5   S a6   S a7   S a8   V oa   F a1   1   1   1   1   0   0   0   0   V dc /2   F a2   0   1   1   1   1   0   0   0   V dc /4   F a0   0   0   1   1   1   1   0   0   0   F a3   0   0   0   1   1   1   1   0   - V dc /4   F a4   0   0   0   0   1   1   1   1   - V dc /2       Using   the   up pe r   ar m   of   t he   phase - le g   ‘ a’   as   an   e xam ple   show n   by   Fig ure   2 ( b).   No te   t ha t   the   switc h   sta te s   S a1 ,   S a2 ,   S a3   an d   S a4   a re   com pleme ntar y   to   S a5 ,   S a6 ,   S a7   an d   S a8   res pe ct ively   [27 ] ,   [ 28] .           (a)       (b)     Figure   2.   (a )   Fi ve - le vel   P WM   con t ro l   ( m f = 12   and   m a = 0.8) ,   ( b)   Stat es   of   s w it ch       2.2.    M athem ati cal   m od el   of   th e   ASVC   sys tem   The   simpli fie d   three - phase   e quivale nt   ci rc uit   of   the   ASVC   connecte d   to   a   transmissi on   li ne   is   sho wn   in   Fig ur e   3.   T he   ASVC   sup plies   reacti ve   power   to   the   AC   transmissi on   s ys te m   if   the   m agn it ude   of   t he   ou t pu t   inv e rter   volt ag e   is   gr eat e r   t ha n   t he   AC   te rmi nal   vo lt age   a nd   a bsor b   reacti ve   powe r   from   the   AC   tra nsmi ssion   sy ste m   if   t he   mag nitud e   of   the   AC   te rmi na l   volt age   is   great er   t han   the   outp ut   in ve rter   vo lt age .   T he   Va r   exch a nge   is   ze ro   w he n   the   two   vo lt age s   are   e qu al   [ 29 ] ,   [ 30].   Evaluation Warning : The document was created with Spire.PDF for Python.
                          IS S N :   2088 - 8 694   In t J   P ow  Ele c  &  D ri   S ys t,   V ol .  12 , N o.   1 ,  Ma rch  20 21   :   345   –   3 55   348     (a)       (b)     Figure   3.   A SVC   cl os ed - loop   con t ro l   s ys te m ,   (a)   With   SFC   con t ro ll er,   ( b)   With   PI   c ontro ll er       a   :   T hr ee - ph as e   source   volt ag e,   b   :   Co upli ng   trans f or me r.   c   :   PWM   volt age   s ource   i nv e r te r,   d   :   DC   side   capaci to rs.   It   is   ass ume d   that   the   AC   si de   is   a   balanc ed   si nuso i dal   t hr ee - phase   vo l ta ge   s uppl y.   U sing   matri x   form,   the   math emat ic al   model   of   the   A SV C   s ys te m   is   giv e n   by   ( 2) :        [    ] = [         − 0 0 0 − 0 0 0 − ]         [    ] + 1 [  −   −   −  ]   (2)     The   ou t put   in ver te r   volt ages   relat ive   to   the   point   n   a nd   the   DC   side   currents   of   the   inv e rter   us i ng   the   connecti on   fun ct ion s   a re   giv e n   in   ( 3) - (7) :       [    ] = 1 3 [ 2 − 1 − 1 − 1 2 − 1 − 1 − 1 2 ] ( .  1 + .  2 − .  3 − .  4 )   (3)     [  1  2  3  4 ] = [ 1 1 1 2 2 2 3 4 3 4 3 4 ] [    ]   (4)      =  1 +  2 −  3 −  4   (5)     with :     Evaluation Warning : The document was created with Spire.PDF for Python.
In t J  P ow Elec   & Dri S ys t   IS S N:  20 88 - 8 694       Sta te  fee dback  con tr ol  of adv anced  static  v ar   compe nsator  usi ng a fi ve - le vel  NPC  …   ( M anso ur Be ny am i na )   349   {         = [ 1 1 1 ] = [ 2 2 2 ] = [ 3 3 3 ] = [ 4 4 4 ]   (6)     {      1 =  2 ⁄  2 =  4 ⁄  3 = −  4 ⁄  4 = −  2 ⁄   (7)     The   model   of   the   DC   side   cap aci tors   vo lt a ge s   is   gi ven   by   (8) :        [  1  2  3  4 ] = 1 [  1  2  3  4 ]   (8)     Ther e f or e,   by   us in g   the   d - q   f rame   tra ns f orm,   t he   no nline ar   sta te - s pace   model   of   the   A SV C   base d   on   the   fi ve - le vel   inv e rter   c ombi ne d   the   DC   ci rc uit   eq uatio n   ca n   be   e xpresse d   by   ( 9) :          [  ] = [         − − 0 − − − 0 − 4 0 ]         [  ] + [ sin cos 0 ]   (9)     wh e re   m   is   t he   rati o   relat in g   t he   AC   to   the   DC   volt age.     The   m odulati on   in dex   relat es   the   ma ximum   ph a se   volt age   V o,Peak   to   the   to ta l   DC   side   vo lt age   V dc   is   giv e n   by   ( 10) :      = √ 2 3   = ,    (10)     The   obta ined   s ta te   equ at io n   is   non - li nea r,   with   res pect   to   t he   c ontrol   va riable     w hich   is   relat ed   to   the   ph a se   dif fe ren ce   betwee n   the   s ource   volt age   a nd   i nv e rte r   ou t pu t   volt ag e.   In   the   ra nge   of   small   value s   of     (| |<   5° ),   t he   s mall - sign al   e quivale nt   sta te   equ at io ns   a nd   the   reacti ve   power   delivere d   by   t he   A SV C - base d   five - le vel   in vert er   syst em   in   the   d - q   f rame   is   expresse d   as   ( 11)   an d   (12 )   [ 18 ]:      [ ∆ ∆ ∆  ] = [         − − 0 − − − 0 − 4 0 ]         [ ∆ ∆ ∆  ] + [ − 1 0 0 ] ∆   (11)     ∆ = [ − 0 0 ] [ ∆ ∆ ∆  ]   (12)     from   ( 11)   a nd   ( 12),   the   tra nsfe r   f unct ion   of   t he   ASVC - base d   five - le vel   i nv e rter   s ys te m   is   gi ven   by:     ( ) = ∆ ( ) ∆ ( ) = (  − ) − 1 = ( ) ( )   (13)     with       ( ) = 2 ( 2 + + 2 4   2   )   (14)     ( ) = 3 + 2 2 + ( 2 + 2 2 + 2 4     ) + 2 4   2     (15)   3.   CONTR OL   S CHE ME   OF   THE   ASV C   S YS TE M   Evaluation Warning : The document was created with Spire.PDF for Python.
                          IS S N :   2088 - 8 694   In t J   P ow  Ele c  &  D ri   S ys t,   V ol .  12 , N o.   1 ,  Ma rch  20 21   :   345   –   3 55   350   3.1.    PI   c ontr ol le r   design   Figure   4   s how s   the   blo c k   dia gr a m   of   t he   A SV C - base d   fiv e - le vel   in ve rter   s ys te m   c ontr olled   by   PI   con t ro ll er.   T he   trans fer   f unct ion   of   t he   c on tr oller   is   e xpress ed   as   ( 16) :     ( ) = +   (16)     The   PI   pa rame te rs   are   cal cula te d   usi ng   r oot   locu s   desig n   for   a   da mp i ng   fac tor   0.7.           Figure   4.   Bl oc k   diag ram   of   the   ASVC   s ys te m   with   PI   c on t ro l       3.2.    The   State   feed ba c k   c ontrolle r   The   ove rall   cl ose d   lo op   c ontr ol   of   t he   ASV C - base d   fi ve - l evel   i nv e rter   with   S FC   c ontro l   te ch nique   is   sh ow n   in   Fi gur e   3 (a)   an d   t he   casca de   c ontr ol   sy ste m   of   t he   sta te - fee db ac k   co nf i gurati on   is   giv e n   in   Fig ur e   5   [31 ] ,   [ 32].   T he   con tr olled   vari able   Q c   is   co mp a red   with   the   set - po i nt   va lue   Q ref   an d   the   con t ro l   er ror   is   fe d   back   to   an   inte gr at or .   T he   f or mer   fee d   f orw ard   gain   k 1   is   now   the   gain   of   t he   integ rato r .   T his   co nfi gur at ion   sh ows   that   the   gain   K   in   t he   i nter nal   cl os e d - loop   is   a   fee dback   par a mete r.   The   basic   pr i nc iple   of   the   des ign e d   s ys te m   is   to   i ns ert   an   i nt egr at or   in   the   feed   f orward   pa th   bet ween   the   er ror   c omp arator   an d   t he   process   [ 31].           Figure   5.   Bl oc k   diag ram   of   t he   ASVC   s ys te m   with   SFC   co ntr ol       Fr om   t he   blo c k   diag ram   of   F i gure   5   we   get:     { ̇ =  +  =    (17)     = −  + 1   (18)     ̇ =  − =  −    (19)     We   ass um e   th at   the   sta te   eq uation   gi ven   by   (17)   is   c omp le te ly   sta te   co ntr ollable .   T he   au gm e nted   dy namic   sy ste m   ca n   be   descr i bed   by   an   e qu at io n   t hat   is   co mb i natio n   of   ( 17)   a nd   ( 19).     [ ̇ ( ) ̇ ( ) ] = [ 0 − 0 ] [ ( ) ( ) ] + [ 0 ] ( ) + [ 0 1 ]  ( )   (20)   Evaluation Warning : The document was created with Spire.PDF for Python.
In t J  P ow Elec   & Dri S ys t   IS S N:  20 88 - 8 694       Sta te  fee dback  con tr ol  of adv anced  static  v ar   compe nsator  usi ng a fi ve - le vel  NPC  …   ( M anso ur Be ny am i na )   351   = [ 0 ] [ ( ) ( ) ]   (21)     = [ − 1 ] [ ( ) ( ) ]   (22)     wh e re :       ̂ = [ 0 − 0 ] ;   ̂ = [ 0 ] ;   ̂ = [ 0 ]   (23)     We   s hall   desig n   an   a sympt otica ll y   sta ble   syst em   s uch   that   x( ∞ ),   xe (∞ ),   a nd   u( ∞ )   a ppr oa ch   c onsta nt   values ,   re sp ect ively .   The n,   at   ste ady   sta te 0 ) ( = e x ,   we   get   Q c (∞ ) = Q r ef   .   The   ai m   of   the   pro pose d   S FC   co ntr oller   is   to   re gu la te   t he   t ot al   DC   si de   vo l ta ge   V dc   w hich   is   the   s um   of   the   four   ca pa ci tors   volt age s   on   the   DC   side   of   t he   in ver t er,   the   AC - cu rrent   c omp on e nt s   I dq   a nd   the   re act ive   powe r   re spo nse   Q c .   The   sta te   sp ac e   re pr ese ntati on   of   the   ASV C   base d   up on   five - le vel   in ve rter   c ontr olled   by   S FC - con t ro ll er   can   be   descr i bed   by   an   e qu at io n   that   is   c ombinat ion   of   ( 11)   an d   ( 12).        [ ∆ ∆ ∆  ∆ ] = [           −   −   0   0   –   −   −   0   0   − 4   0   0     0   0   0 ]           [ ∆ ∆ ∆  ∆ ] + [ − 0 0 0 ] ∆   (24)     ∆ = [ − 0 0   0 ] [ ∆ ∆ ∆    ∆ ]   (25)     To   achie ve   a   good   dy namic   r esp on se   of   the   cl os ed   loop   s yst em,   t he   pole s   are   dete rmin e d   by   t he   Ac kerman n   al gorithm   w here:     1 = − 500 , 2 = − 450 , 3 = − 300 + 305 . 65 , 4 = − 300 − 305 . 65         The   necessa ry   sta te   feedbac k   gain   matri x K ˆ are   determi ned   usi ng   the   pole   pla cement   te c hn i que,   w her e     ̂ = [ ⋮ 1 ] = [ − 0 . 0320   − 0 . 0174   − 0 . 0023   − 0 . 0382 ]         4.   SI M ULATI O N   RESU LT S   AND   DISC USSION   A   dig it al   simul at ion   is   done   ba sed   on   the   det ai le d   ASVC   s yst em   sho wn   by   Fig ur e   3.   T he   PI   a nd   the   SFC   co ntr oller s’   par a mete rs   a re   li ste d   in   A ppen dix.     The   PI   an d   S FC   co ntr ollers   we re   e valuat ed   unde r   m or e   reali sti c   sim ulati on   co ndit ion   w he n   t he   ASVC   wa s   c ontr olled   by   P W M   c ontrol   ci rc uit.   Figure   6   dis pla ys   t he   simulat ion   run   f or   a   st ep   c ha ng e   in   t he   Q ref   ref e rence   f rom   10   K va r   (in du ct ive )   to   - 10   Kv a r   (c apacit ive)   in   orde r   to   s wing   the   s ys te m   fro m   le adi ng   to   la gg i ng   m ode   at   ti me   0.1   se c   an d   sta ndby   m ode   at   0.2   sec .   Fr om   Fig ure   6,   a   perf or ma nc e   com par is on   betwee n   the   t wo   c ontrolle r s   is   su mma rize d   in   Ta ble   2.   The   SFC   c ontr oller   has   a   rise   ti me   an d   set tl ing   ti me   of   12 .4   msec   an d   30   msec   res pecti vely,   w her e   t he   PI   con t ro ll er   has   a   rise   ti me   an d   set tl ing   ti me   of   14. 2   msec   a nd   45 .65   m sec   r especti vely .   It   can   be   see n   th at   the   rise   ti me   and   t he   set tl ing   ti me   of   the   S FC   c on t ro ll er   a re   12. 7   %   an d   35. 5   %   resp ect ivel y   le ss   than   t hose   of   the   PI   c on t ro ll er .   M ore ov e r,   t he   SFC   co ntr oller   does   not   ha ve   an y   ov e rs hoot   w hen   the   PI   c on t ro ll er   in   tra ns ie nt   sta te   exh i bits   5%   of   ov e rs hoot .       Table   2.   T he   pe rformance   co mp a rison   betw een   c onve ntio na l   PI   a nd   S FC   con t ro ll ers   Para m eters   PI   co n troller   SFC   co n troller   Ris e   Ti m e   ( msec)   1 4 .20   1 2 .40   Settlin g   Time   ( mse c)   4 5 .65   3 0 .00   Ov ersh o o t   ( % )   5   0   Evaluation Warning : The document was created with Spire.PDF for Python.
                          IS S N :   2088 - 8 694   In t J   P ow  Ele c  &  D ri   S ys t,   V ol .  12 , N o.   1 ,  Ma rch  20 21   :   345   –   3 55   352   Figure   7   s hows   a   phase   c urre nt   wav e f or m s   dyna mic   be ha vio r .   It   is   obser ve d   that   t he   c urr ent   injec te d   into   the   tra ns m issi on   line   c on t ro ll ed   by   t he   S FC   co ntr oller   is   faster   that   t he   one   c ontrolle d   by   P I.   Fig ur e   8   (a )   and   ( b)   s how   the   s ource   pha se   volt age   a nd   the   i nv e rter   c urren t   wa veforms   re sp ect ivel y   with   PI   a nd   SFC   con t ro ll ers .  At   first,   the   ASVC   is   ge ner at ing   10   kVar   i nductive   reacti ve   powe r   a nd   at   0.1   sec   is   fastl y   abs orbin g   al so   10   kVa r   but   as   a   capaci ti ve   reacti ve   power.   From   0.2   sec   the   AS VC   is   in   sta ndby   mode,   it   pro vid es   no   re act ive   powe r   ( Qc = 0   kVar ).   F igure   9   an d   Figure   10   re pr es ent   tran sie nt   DC   side   volt age   across   the   fou r   capaci tors   afte r   a   sudd e n   c hange   in   re fer e nce   un der   PI   an d   SFC   con tr ollers   r especti vely ,   it   can   be   no ti ced   t hat   volt age   flu ct uat ion   of   V dc1,2,3,4   wit h   SFC   co ntr oller   wer e   r edu ce d   by   50   %   c ompare d   to   t hose   ob ta ine d   with   PI   c ontrolle r .   Figure   11(a )(b )   a nd   Fig ur e   12(a )(b)   s how   t he   t ran sie nt   res pons e   of   the   to ta l   DC   side   vol ta ge   V dc ,   a nd   I d ,   I q   AC - c urre nt   co mpo nen ts   resp e ct ively   with   PI   an d   SF C   con t ro ll ers .   It   can   be   seen   t hat   total   side   volt age   con t ro ll ed   by   t he   S FC   is   bette r   that   t he   one   c on t ro ll ed   by   PI.   The   s ource   volt age   an d   i nverter   outp ut   vo lt age   wa veforms   of   the   f ive - le vel   NP C   inv e rter   f or   reacti ve   powe r   com pe ns at io n   with   PI   a nd   SFC   co ntro ll ers   a re   dep ic te d   by   Figure   13   (a )   a nd   ( b)   res pecti vely.             Figure   6.   Re act ive   po wer   res ponse     Figure   7.   a - ph a se   AC   c urre nt   r esp on se           (a)   (b)     Figure   8.   S our ce   volt age   a nd   AC   c urren t   Wa veforms.   (a )   with   PI   c on tr ol,   ( b)   with   SFC   c ontr ol           (a)   (b)     Figure   9.   Ca pa ci tor   vo lt age   at   dif fer e nt   le vel s   with   PI   co ntr ol ,   (a)   V dc1   an d   V dc4   ,   ( b)   V dc2   a nd   V dc3   Evaluation Warning : The document was created with Spire.PDF for Python.
In t J  P ow Elec   & Dri S ys t   IS S N:  20 88 - 8 694       Sta te  fee dback  con tr ol  of adv anced  static  v ar   compe nsator  usi ng a fi ve - le vel  NPC  …   ( M anso ur Be ny am i na )   353       (a)   (b)     Figure   10.   Ca pa ci tor   vo lt age   at   diff e re nt   le ve ls   with   SFC   c on t ro l ,   (a )   V dc1   and   V dc4   ,   ( b)   V dc2   and   V dc3         (a)     (b)     Figure   11.   T ot al   DC   side   volt age   V dc   of   t he   I nv e rter ,   (a )   with   PI   c ontrol,   (b)   wit h   S FC   co nt ro l         (a)     (b)     Figure   12.   AC   current   in   d - q   f rame,   (a )   with   PI   c ontrol ,   ( b)   with   S FC   c on tr ol           (a)   (b)     Figure   13.   Inve rter   ou t pu t   volt age   a nd   s ource   volt age,   (a)   wi th   PI   c on tr ol,   ( b)   with   SFC   c ontr ol         Evaluation Warning : The document was created with Spire.PDF for Python.
                          IS S N :   2088 - 8 694   In t J   P ow  Ele c  &  D ri   S ys t,   V ol .  12 , N o.   1 ,  Ma rch  20 21   :   345   –   3 55   354   5.   CONCL US I O N   In   this   pa per ,   a   simulat io n   s tudy   of   the   dyna mic   perfor mance   an d   robu st ness   of   st at e   feedbac k   con t ro l   ha ve   be en   pro posed ,   evaluate d   a nd   com par e d   to   a   co nventio nal   PI   c ontr oller   a pp li ed   to   an   A SVC   com pensat or   usi ng   five - le vel   NP C - VS C   i nverter .   T he   fi ve - le vel   N PC   inv e rter   has   be en   us ed   f or   it s   high   qu al it y   wa ves ha ping   ou t pu ts .   Simulat io n   res ults   s how   the   ef fecti ven e ss   of   t he   pro po sed   c ontr ol   st rateg y.   The   S FC   co ntr ol   al gorithm   s ho ws   that   reacti ve   powe r   c omp ensati on   is   ac hi eved   by   c on t r olli ng   t he   e xc ha ng e   of   act ive   powe r   betwee n   DC   s ide   of   i nv e rter   ci rcu it   a nd   AC   sy ste m .   It   c an   be   c oncl ud ed   that   the   SF C   co ntro ll er   le ads   to   impro ve   tran sie nt   res pons e   a nd   he nce   pro vi de   fast   re act ive   power   c ompe ns at io n   with   ba la ncing   t he   to ta l   DC   capaci tors   volt age.   Als o   the   S FC   co ntr oller   is   bette r   t han   the   PI   co ntr oller   and   can   be   easi ly   tu ned.       APPE ND I X     SIMULATI O N   P ARA METE RS   R s = 1Ω,   L s = 5× 10 - 3 H,   C s = 500× 10 - 6 F,   V s = 220V ,   m = 0.646,   ω = 100π   [r a d/sec] ,   K p =4.156× 10 - 6 ,   K i = 2.4× 10 - 3 ,   m f = 24,   m a =   0.8 ,   A c = 0.5 ,   A s =   0.8,   f c = 1200 Hz ,   f s   = 50Hz .         REFERE NCE S   [1]   J.   Fang,   X.   L i,   H.   Li   and   Y.   T ang,   "S ta b il i ty   i mprove m ent   for   three - phase   g ri d - conne c te d   con ver te rs   throug h   im ped anc e   resha ping   in   quadr at u re - axi s" ,   I EEE   Tr ansacti ons   on   P ower   El e ct ronics ,   vol.   33 ,   no .   10,   pp.   8365 - 8375 ,   Oct.   2018 .     [2]   S.   Yang,   J.   Fan g,   Y.   Ta ng ,   H.   Qiu,   C.   Dong   a nd   P.   W ang,   "M odula r   mul t il ev e l   conv ert er   synt het i c   in ert i a - bas ed   fre quenc y   support   for   me d ium - v olt ag e   microgrid s " ,   IEE E   Tr ansacti ons   on   Pow er   El e ct ronics ,   vol .   66 ,   no .   11,   pp .   8992 - 9002,   Nov.   2019 .     [3]   P.A.   Bl asc o,   R.   Montoya - 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