Internati
o
nal
Journal of P
o
wer Elect
roni
cs an
d
Drive
S
y
ste
m
(I
JPE
D
S)
Vol
.
6
,
No
. 2,
J
une
2
0
1
5
,
pp
. 24
2~
25
2
I
S
SN
: 208
8-8
6
9
4
2
42
Jo
urn
a
l
h
o
me
pa
ge
: h
ttp
://iaesjo
u
r
na
l.com/
o
n
lin
e/ind
e
x.ph
p
/
IJPEDS
An Efficient High Gain DC-DC
Converter for Automotive
Applications
Aisw
ary
a
T
.
M,
M.
Pr
abh
a
kar
School of
Electr
i
cal Engin
eer
ing,
VIT Univer
sity
, Chennai
Campus,
Chennai, India. 600127
Article Info
A
B
STRAC
T
Article histo
r
y:
Received Dec 17, 2014
Rev
i
sed
Mar
13
, 20
15
Accepte
d Apr 2, 2015
This paper presents a high gain
DC-DC
converter which uses a clamp cir
c
uit
to achiev
e soft
switching. The
proposed
conver
t
er
is design
ed to supply
a
high intensity
d
i
scharge (HID)
lamp us
ed in a
u
tom
obile he
ad
lam
p
s. The
converter oper
a
tes from a 12V input s
upply
and
provides an output voltag
e
of 120V at 35W output power. A clam
p cir
c
uit consisting
of a clamp
capa
c
itor
,
c
l
am
p switch and r
e
sonant indu
cto
r
will he
lp to
achi
e
ve
zero
voltag
e
switchin
g
(ZVS) of the b
o
th m
a
in and
cla
m
p switches. Th
e prac
ti
ca
l
performance of
the conver
t
er
was valid
ated through experimental results
.
Results obtain
e
d
from the prototy
p
e h
a
rd
ware pr
ove that
the con
v
erter m
e
e
t
s
the requir
e
ments
of HID lamp ap
plicati
on and
can be a ver
y
good
altern
ativ
e
to ex
isting
conv
erters.
Keyword:
Au
t
o
m
o
tiv
e Ap
p
lication
s
C
l
am
p ci
rcui
t
DC-DC converter
HI
D lam
p
s
Hig
h
gain
Copyright ©
201
5 Institut
e
o
f
Ad
vanced
Engin
eer
ing and S
c
i
e
nce.
All rights re
se
rve
d
.
Co
rresp
ond
i
ng
Autho
r
:
M
.
Pra
b
haka
r,
Ass
o
ciate Professor, Sc
hool
of Electrical E
n
ginee
r
ing,
VIT Un
iv
ersity, Ch
enn
a
i Camp
u
s
,
Van
d
al
u
r
-
K
el
a
m
bakkam
R
o
ad, C
h
e
nnai
,
I
n
di
a 6
0
0
1
2
7
.
Em
a
il: p
r
abh
a
kar.m
@
v
it.ac.in
1.
INTRODUCTION
Th
e h
i
gh
g
a
i
n
bo
o
s
t conver
t
er
h
a
s b
e
co
m
e
essen
tial
in
all
p
r
esent d
a
y ap
p
licatio
n
s
su
ch
as
aut
o
m
obi
l
e
appl
i
cat
i
o
ns, p
hot
ov
ol
t
a
i
c
sy
st
em
s,
m
e
di
cal
equi
pm
ent
s
and U
PS s
y
st
em
s. In al
l
such
ap
p
lication
s
, a
DC-DC co
nv
erter with vo
ltage g
a
i
n
eq
u
a
l t
o
or greater t
h
a
n
10 is e
sse
ntial. The
classical boos
t
co
nv
erter fails
to
p
r
ov
id
e a
vo
ltag
e
g
a
i
n
of
1
0
b
ecau
s
e
of t
h
e li
m
ited
d
u
t
y ratio
. In
creased
du
ty ratio
lead
s to
hi
g
h
re
ve
rse
reco
very
pr
o
b
l
em
s, hi
gh
s
w
i
t
c
hi
n
g
st
res
s
res
u
lting i
n
red
u
ce
d
effi
ciency and increased
electro
m
a
g
n
e
tic in
terferen
ce
(EMI) [1
].
Other altern
ativ
e to
po
log
i
es fo
r
o
b
t
ain
i
n
g
h
i
gh v
o
ltag
e
rati
o
in
clud
e
fl
y
b
ack c
o
n
v
e
r
t
e
rs, c
o
u
p
l
e
d
i
nduct
o
r (C
I)
based t
o
p
o
l
o
gi
es, swi
t
c
he
d
capaci
t
o
r an
d
ot
her
bo
ost
deri
ve
d
t
o
p
o
l
o
gi
es. Fl
y
b
ack
c
o
nve
rt
ers
are
capa
b
l
e
of p
r
o
v
i
d
i
n
g hi
g
h
gai
n
but
pre
s
ence
of wi
n
d
i
n
g
l
e
akage
i
n
d
u
ct
ance
l
eads t
o
hi
g
h
er c
o
m
ponent
c
u
r
r
e
n
t
st
ress
as
de
p
i
ct
ed i
n
[2]
.
In
c
o
upl
e
d
i
n
d
u
ct
o
r
based
t
o
pol
ogi
es
, hi
g
h
gai
n
i
s
o
b
t
a
i
n
e
d
by
va
ry
i
n
g
t
h
e num
ber of
t
u
r
n
s
i
n
t
h
e
co
up
led indu
cto
r
. Th
is
r
e
du
ces th
e sw
itch
i
n
g
str
e
ss an
d
eli
m
in
ates th
e r
e
v
e
r
s
e r
e
cover
y
pro
b
l
em
also
as
dem
onst
r
at
ed i
n
[
3
]
.
Ho
we
ver
,
t
h
e us
e of
a co
up
led
indu
ctor
lead
s to
vo
ltag
e
ring
ing
across th
e switch
du
e to
the leaka
g
e i
n
ductance
and t
h
e stray
ca
pacitance.
The
r
efore, it bec
o
m
e
s n
ecessary to use
a s
n
ubber circ
uit or
a switch with
relative high ON state resis
t
ance (R
DS,ON
). C
onse
que
nt
l
y
, t
h
i
s
resul
t
s
i
n
de
gra
d
e
d
co
nve
rt
er
efficiency.
In
[4]
a
nd
[5]
,
a con
v
e
r
t
e
r t
o
pol
ogy
whi
c
h
use
d
t
h
e active cla
m
p circuit to effectively
recycle the
st
ore
d
ene
r
gy
prese
n
t
i
n
t
h
e c
o
u
p
l
e
d i
n
d
u
ct
o
r
was p
r
o
p
o
se
d
.
Furt
her
,
t
h
e st
ore
d
ene
r
gy
i
n
t
h
e st
ray
i
nduc
t
a
nce
can be a
b
s
o
r
b
e
d
by
usi
n
g a c
o
upl
e
d
i
n
duct
o
r
wi
t
h
a pa
ssi
ve
rege
nerat
i
ve sn
ub
be
r as cl
ai
m
e
d i
n
[6]
.
A co
upl
e
d
in
du
ctor based to
po
log
y
wh
i
c
h
u
s
ed m
u
lti-
wind
ing
an
d
a vo
ltag
e
d
oub
ler circu
it was
p
r
esen
ted in
[7]. The
to
po
log
y
p
r
o
p
o
s
ed
in
[8
] u
s
ed
a co
up
led
in
du
ctor with
ap
pro
p
riate tu
rns ratio
n
to
ob
tain
h
i
gh
con
v
ersi
on
r
a
tio
. Th
is topo
log
y
in
tegr
ated
a
f
l
yb
ack
ar
ran
g
e
m
e
n
t
and
a step
-up
conver
t
er
. Th
e t
o
polo
g
i
es in
cor
p
o
r
atin
g
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-86
94
I
J
PED
S
Vo
l. 6,
No
.
2,
Ju
ne 20
15
:
242
–
2
52
2
43
t
h
e
co
u
p
l
e
d
i
n
duct
o
r
o
r
fl
y
b
ack
t
r
a
n
s
f
o
r
m
e
r do
n
o
t
pr
o
v
i
d
e
t
h
e req
u
i
r
ed
hi
gh
gai
n
at
hi
g
h
out
put
p
o
we
r
ratin
g
s
. Th
is is m
a
in
ly d
u
e
to th
e limited
cap
acity o
f
m
a
g
n
e
tic core wh
i
c
h
h
a
s to
b
e
su
b
s
tan
tially in
creased
base
d
on the i
n
crem
ental output power.
For
l
o
w
po
we
r ap
pl
i
cat
i
ons
,
hi
g
h
st
e
p
-
u
p
co
nve
rt
er
bas
e
d
on the s
w
i
t
ched-capacitor circ
uit is
pre
f
er
red
.
Si
nc
e i
nduct
o
rs are
not
use
d
, t
h
e s
w
i
t
c
hed ca
paci
t
o
r co
nv
ert
e
r h
e
l
p
s t
o
achi
e
ve
hi
gh
po
wer
de
nsi
t
y
as pr
opo
sed in [
9
]-[1
1
]
.
Ho
wev
e
r, r
e
gu
lating
th
e ou
tpu
t
vo
ltag
e
resu
lts i
n
redu
ced
efficien
cy. By in
teg
r
ating
th
e switch
cap
acito
r
with
bo
o
s
t co
nv
e
r
ter, higher c
o
nversion ratios
at
better effic
i
encies are possible.
Ho
we
ver
,
suc
h
t
o
p
o
l
o
gi
es re
q
u
i
r
e m
o
re n
u
m
b
er
of c
o
m
pon
ent
s
as p
r
ese
n
t
e
d i
n
[1
2]
. T
o
p
o
l
o
gi
es p
r
o
p
o
s
e
d i
n
[1
3]
an
d [
1
4]
use
onl
y
a si
ngl
e s
w
i
t
c
h.
T
h
ese t
o
p
o
l
o
gi
es were
de
vel
o
ped
usi
ng
swi
t
ched ca
paci
t
o
r an
d
swi
t
c
he
d i
n
d
u
c
t
or
hy
b
r
i
d
ci
rc
ui
t
.
T
h
ese ci
rc
ui
t
s
p
o
ssess
re
duce
d
swi
t
c
h
a
n
d
di
ode
v
o
l
t
a
ge st
re
ss.
Fu
rt
her
,
by
ad
d
i
n
g
vo
ltag
e
m
u
lt
ip
lier capacito
r stages, t
h
e
v
o
ltag
e
gain at a gi
ven dut
y
ratio ca
n
be i
n
crease
d
.
C
a
scadi
n
g
of
b
oost
c
o
nve
rt
er
al
so can
p
r
o
v
i
d
e
hi
g
h
gai
n
e
v
en
u
n
d
er
n
o
r
m
al
dut
y
rat
i
o
as desc
ri
be
d
in
[15
]-[17
]. Ho
wev
e
r, th
e switch
v
o
ltag
e
st
ress will b
e
ex
tre
m
ely h
i
g
h
.
Furth
e
r, th
e switch
i
ng
frequ
e
n
c
y an
d
ope
rat
i
n
g effi
c
i
ency
i
s
lim
it
ed d
u
e t
o
har
d
swi
t
c
hi
n
g
. I
n
or
der t
o
a
voi
d t
h
i
s
, soft
swi
t
c
hi
n
g
, usi
ng a
n
act
i
v
e
cla
m
p
circuit, can be
em
ployed
as pr
opo
sed in
[
1
8
]
and
[19
]
.
A so
ft
swi
t
c
he
d hi
g
h
gai
n
D
C
-DC
co
n
v
ert
e
r i
s
prese
n
t
e
d
i
n
t
h
i
s
pape
r.
The pr
o
p
o
s
ed
con
v
ert
e
r
co
nsists o
f
two b
o
o
s
t stag
es t
h
at u
s
e a sing
l
e
p
o
wer switch
and
an
aux
iliary switch
.
The activ
e cla
m
p
circu
i
t
is u
s
ed
to
realise so
ft switch
i
ng
o
f
b
o
t
h
th
e m
a
in
an
d
au
x
iliary switch
e
s Q and
Qa resp
ectiv
ely. Th
is
arra
ngem
e
nt
r
e
duce
s
t
h
e sw
i
t
c
hi
ng st
ress and
i
n
c
r
eases
the converter’s operating e
f
ficiency. T
h
e
circuit
con
f
i
g
urat
i
o
n
,
ope
rat
i
n
g m
odes, anal
y
s
i
s
det
a
i
l
s
, desi
g
n
m
e
t
h
o
dol
ogy
a
nd
expe
ri
m
e
nt
al
resul
t
s
are
di
scuss
e
d
in
th
e
sub
s
eq
uen
t
section
s
.
2.
CIR
C
U
IT DE
SC
RIPTIO
N
Th
e co
nv
en
tion
a
l bo
ost conv
erter canno
t p
r
ov
id
e
h
i
gh
g
a
in
d
u
e
t
o
limita
tio
n
s
of
du
ty cycle an
d
reve
rse rec
o
ve
ry
pr
obl
em
s. One m
e
t
hod t
o
o
b
t
a
i
n
hi
gh
gai
n
wi
t
h
o
u
t
i
n
creasi
ng t
h
e dut
y
rat
i
o
i
s
t
o
con
n
ect
t
w
o
b
oost
st
a
g
es i
n
casca
de c
o
n
f
i
g
urat
i
o
n a
s
sh
ow
n i
n
Fi
g
u
re
1.
To
red
u
ce th
e co
m
p
le
x
ity o
f
t
h
e two-stag
e
bo
ost
co
nve
rt
e
r
, t
h
e p
o
we
r swi
t
c
hes Q
1
and Q
2
in Figure 1 can be reduce
d to
sin
g
l
e pow
er
sw
itch
Q
as sh
own
i
n
Fi
g
u
r
e
2. T
h
e
po
we
r s
w
i
t
c
h
Q
ope
rat
e
s
i
n
ha
r
d
s
w
i
t
c
hi
ng
cau
si
n
g
hi
g
h
s
w
i
t
c
hi
n
g
st
r
e
ss. T
o
ac
hi
ev
e so
ft
switch
i
ng
o
f
the switch, an
activ
e clam
p
circu
it co
m
p
rising
o
f
an aux
iliary
switch
Q
a
, cla
m
p capacitor C
C
and
reso
na
nt
i
n
duct
o
r
L
r
i
n
ad
de
d
as sh
o
w
n
i
n
Fi
gu
re
3.
Fi
gu
re 1.
Tw
o
-
st
age bo
ost
c
o
nve
rt
er
Fi
gu
re 2.
Tw
o
-
st
age bo
ost
c
o
nve
rt
er wi
t
h
si
ngl
e swi
t
c
h
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
PED
S
I
S
SN
:
208
8-8
6
9
4
An
Efficien
t
Hig
h
Ga
in DC
-DC Co
n
v
erter for Au
t
o
mo
tive Ap
p
lica
tion
s
(M. Prabh
a
k
a
r
)
24
4
Fi
gu
re 3.
Pr
o
p
o
se
d hi
g
h
gai
n
soft
s
w
i
t
c
he
d b
oost
co
n
v
ert
e
r
In t
h
i
s
s
o
ft
swi
t
ched t
o
p
o
l
o
gy
, ci
rcui
t
com
pone
nt
s L
1
, D
1
, D
2
, C
1
and Q
act as the first
stage of the
bo
ost
c
o
nve
rt
er a
n
d
p
r
o
v
i
d
e
s
a v
o
l
t
a
ge c
o
nv
ersi
o
n
rat
i
o
of
1
1
(1
)
whe
r
e D i
s
t
h
e dut
y
rat
i
o
o
f
Q
.
The seco
n
d
st
age b
o
o
s
t
con
v
e
rt
er co
nsi
s
t
i
n
g of c
o
m
pone
n
t
s C
1
, L
2
, Q
2
, D
3
and
C
o
an
d vo
ltag
e
co
nv
er
sion
r
a
tio
is
1
1
(2
)
Thu
s
, t
h
e effectiv
e con
v
e
rsi
o
n ratio
o
f
th
e
cascad
ed
b
o
o
s
t co
nv
erter is
ob
tain
ed
as
1
1
(3
)
3.
CIR
C
U
IT O
P
ERATIO
N
Th
e
op
er
ating
m
o
d
e
s o
f
th
e pr
opo
sed conv
er
ter
ar
e el
a
b
orated
by ass
u
m
i
ng that
(i) t
h
e
value
of t
h
e
in
du
ctor
L
1
and L
2
are great
er than L
r
, (i
i
)
t
h
e reso
na
nt
i
nduct
o
r st
o
r
es
m
o
re ener
g
y
t
h
an t
h
e res
ona
nt
capacitor C
r
to ach
iev
e
soft switch
i
ng
and
(iii) th
e cap
acit
a
n
ce of C
1
, Cc and Co are la
rge e
n
ough s
o
that
voltage ac
ross
them are constant. The
r
e are eight m
odes of o
p
e
r
at
i
on
fo
r p
r
o
p
o
se
d con
v
e
r
t
e
r as de
t
a
i
l
e
d
bel
o
w.
M
ode 1
(t
0
< t < t
1
):
In
th
is
mod
e
, t
h
e ma
i
n
switch
Q is t
u
rned
ON and
a
u
x
ilia
ry switch
Q
a
re
mains i
n
OFF
state.
T
h
e diode D
2
is co
ndu
ctin
g wh
ile
dio
d
e
s D
1
and
D
3
are
OFF.
The
output ca
pacitor C
o
di
s
c
har
g
es
th
ro
ugh
th
e lo
ad
.
Sin
ce
L
1
and L
2
is
greater than L
r
,
in
d
u
c
to
r
cu
rr
e
n
t
s
i
L1
an
d i
L2
increase
and are
gi
ven by
≅
(4
)
≅
(5
)
wh
ere D is th
e d
u
t
y ratio
o
f
t
h
e m
a
in
switch Q an
d
T is ti
me p
e
riod
. Th
is m
o
d
e
en
d
s
b
y
th
e
m
a
in
switch
Q is
turned OFF at t
i
m
e
t
1
.
M
ode
2
(t
1
< t
< t
2
):
Th
e main
switch
Q i
s
tu
rn
ed
OFF.
Po
sitiv
e ind
u
cto
r
cu
rren
t of i
Lr
no
w ch
ar
ges th
e
capacitor C
r
fro
m
0
to
V
C1
-V
Lr
≈
V
C1
since
L
1
and L
2
a
r
e greater tha
n
L
r
. The
ca
pacitor voltage V
Cr
< V
C1
, the
di
o
d
es D
1
a
nd
D
3
are re
verse
d
biase
d
while diode D
2
is still co
nd
u
c
ting
.
Wh
en
V
Cr
= V
C1
,
di
o
d
e D
1
is fo
rwa
r
d
biased as the voltage ac
ros
s
the diode D
1
and
C
1
is same V
C1
.
T
h
u
s
,
a
t
t
i
m
e
t
2
, t
h
i
s
m
ode ends w
h
en D
1
is
tu
rn
ed ON.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-86
94
I
J
PED
S
Vo
l. 6,
No
.
2,
Ju
ne 20
15
:
242
–
2
52
2
45
M
ode 3
(t
2
< t < t
3
):
In
th
is mo
d
e
, th
e
d
i
od
es D
1
and
D
2
are
conducting wi
th diode c
u
rre
n
t i
D1
increasing and
i
D2
decreasing. This m
ode e
n
ds at tim
e t
3
when
V
Cr
=
V
CC
whi
c
h ca
uses t
h
e a
n
t
i
-
pa
ral
l
e
l
b
ody
di
o
d
e
of
Q
a
to
becom
e
forwa
r
d
biased.
M
ode
4
(t
3
< t
< t
4
):
T
h
i
s
m
ode
begi
ns
w
h
e
n
t
h
e
ant
i
-
pa
ra
l
l
e
l
di
ode
o
f
Q
a
bec
o
m
e
s for
w
ar
d
bi
ased
.
N
o
w
t
h
e
reso
na
nt
i
n
d
u
c
t
or cu
rre
nt
i
Lr
will flo
w
th
rou
g
h
th
e an
ti-parallel d
i
o
d
e
Q
a
to ground.
There
f
ore, the
drai
n to
source voltage
is zero for Q
a
. Th
e
switch
Q
a
is n
o
w
turn
ed
ON, th
u
s
ach
i
ev
ing
ZVS
d
u
ri
n
g
th
is in
terv
al
. Th
is
m
ode co
m
e
s to an end at time t
4
when di
ode c
u
r
r
ent
i
D2
bec
o
m
e
s zero and t
h
e di
o
d
e
D
2
is reverse
d
biased
wh
ile d
i
od
e D
3
is tu
rn
ed
ON.
M
ode 5 (t
4
< t < t
5
):
T
h
i
s
m
o
d
e
c
o
m
m
e
n
c
e
s
a
t
t
i
m
e
t
4
. At th
is ti
m
e
in
terval, D
2
is re
vers
e biased while D
3
is
turned ON.
T
h
e inductor c
u
rre
nts i
L1
, i
L2
and the
res
o
nant induct
o
r c
u
rrent i
Lr
d
ecrease fro
m
p
o
s
itiv
e to
negat
i
v
e m
a
gn
i
t
ude. T
h
e swi
t
ch Q
a
sh
oul
d
be t
u
rn
ed O
F
F bef
o
re i
Lr
becom
e
s negative to achieve
ZVS.
There
f
ore, s
w
itch
Q
a
is turn
ed OFF at tim
e t
5
w
h
i
c
h m
a
rks t
h
e e
n
d
o
f
t
h
i
s
m
ode.
M
ode 6 (t
5
< t < t
6
):
In
t
h
i
s
m
ode
, t
h
e
res
o
na
nt
i
n
duct
o
r
cu
r
r
ent
i
Lr
i
s
negat
i
ve an
d t
h
e s
w
i
t
c
h Q
a
is tu
rn
ed
OFF
whi
l
e
di
ode
D
3
still conduct
s
. Since i
Lr
is n
e
g
a
tiv
e, it is u
n
d
e
rstoo
d
t
h
at th
e vo
ltage acro
ss cap
a
cito
r C
r
discha
rge
s
. He
nce,
t
h
e
ca
paci
tor voltage V
Cr
starts to dec
r
e
a
ses from
V
Cc.
ZVS
op
eration of th
e m
a
in
switch
is ens
u
re
d sinc
e the capacitor
voltage
V
Cr
be
com
e
s zero a
n
d f
o
rwa
r
d
bi
as
es t
h
e a
n
t
i
-
pa
ra
l
l
e
l
di
ode.
Thi
s
m
ode
ends whe
n
V
Cr
= 0 at tim
e t
6
.
M
ode 7
(t
6
< t < t
7
):
In
th
is m
o
d
e
, cap
acito
r vo
ltag
e
V
Cr
=0
du
e to
wh
ich
th
e an
ti-p
a
rallel d
i
o
d
e
is fo
rward
biased. The induct
o
r c
u
rrent
i
Lr
in
creases toward
s po
sitiv
e
v
a
lu
e fro
m
a n
e
g
a
tiv
e v
a
l
u
e.
Th
e m
a
in
swit
ch
Q is
turned
ON at ZVS
in
terval. The diode
D
1
an
d D
3
are still co
ndu
ctin
g. By
th
e end
o
f
th
is m
o
d
e
, at tim
e
t
7
, the
out
put
di
o
d
e D
3
is tu
rn
ed
OFF and
th
e d
i
o
d
e
D
2
is forwa
r
d
biased.
M
ode 8
(t
7
< t < t
8
):
In
th
is m
o
d
e
, th
e d
i
od
e D
3
i
s
t
u
r
n
e
d
OF
F. T
h
e di
ode
s D
1
and D
2
are in commutation
interval. T
h
e
voltage ac
ross
capacitor C
1
will b
e
sa
m
e
as th
e in
du
ced v
o
ltag
e
d
r
o
p
acro
ss th
e
reso
nan
t
in
du
ctor
. Th
is
cau
ses th
e indu
ctor
cur
r
e
n
t
i
Lr
to increase
.
This m
ode ends when
diode
D
1
is tu
rn
ed
OFF with
i
D1
=0 and m
a
rks the c
o
mm
e
n
cem
ent of the next cycle.
Figure 4
shows the cha
r
acteristic waveform
of the
con
s
i
d
ere
d
c
o
n
v
ert
e
r
an
d
Fi
g
u
r
e
5 s
h
o
w
s t
h
e
equi
val
e
nt
ci
rc
ui
t
di
ag
ram
s
d
u
ri
ng
va
ri
o
u
s
o
p
erat
i
n
g m
odes
.
4.
AN
ALY
S
IS
O
F
THE P
R
ESENTED CONVERTER
The steady state analysis of the
circu
it is u
s
ed
to
d
e
ri
v
e
i
m
p
o
r
tan
t
characteristic eq
u
a
tio
ns lik
e
vol
t
a
ge
gai
n
a
n
d
de
vi
ce st
res
s
. B
y
v
o
l
t
-
sec
o
nd
bal
a
nce
pri
n
ci
pl
e a
ppl
i
e
d
acros
s t
h
e i
n
d
u
c
t
o
rs L
1
a
n
d
i
n
duct
o
r
L
2
,
wi
t
h
out
c
o
nsi
d
e
r
i
n
g t
h
e
dut
y
cy
cl
e l
o
s
s
i
n
eac
h m
o
d
e
, t
h
e st
ea
dy
st
at
e vol
t
a
ge
g
a
i
n
eq
uat
i
o
n c
a
n
be
deri
ved
.
Wh
en
th
e switch
Q
rem
a
in
s
in
ON state, the v
o
ltag
e
across th
e ind
u
c
t
o
r L
1
is eq
u
a
l to th
e sup
p
l
y
vol
t
a
ge
V
in
.
Wh
en
t
h
e switch Q is OFF, t
h
e v
o
ltag
e
acro
s
s L
1
will b
e
V
L1
=V
in
-V
C1
. N
o
w, by
ap
pl
y
i
ng
vol
t
-
seco
nd
bal
a
nce
,
we
get
1
0
(6
)
R
earra
ngi
ng
eq
uat
i
o
n
(
6
)
,
we
get
1
1
(7
)
Wh
en
t
h
e switch
Q is
ON, t
h
e vo
ltag
e
across th
e i
n
du
ctor
L
2
will b
e
same as th
e vo
ltage acro
ss cap
aci
to
r C
1
.
Whe
n
t
h
e s
w
i
t
c
h
Q i
s
t
une
d
OFF
,
t
h
e
v
o
l
t
a
ge ac
ros
s
t
h
e
i
n
d
u
ct
o
r
i
s
gi
ve
n
by
(8
)
Ap
pl
y
i
ng
v
o
l
t
-
seco
nd
bal
a
nce
acr
oss i
n
d
u
ct
o
r
L
2
gi
ves
1
0
(9
)
R
earra
ngi
ng
eq
uat
i
o
n
(
9
)
,
we
get
1
1
(1
0)
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
PED
S
I
S
SN
:
208
8-8
6
9
4
An
Efficien
t
Hig
h
Ga
in DC
-DC Co
n
v
erter for Au
t
o
mo
tive Ap
p
lica
tion
s
(M. Prabh
a
k
a
r
)
24
6
Co
m
b
in
in
g
t
h
e equ
a
tio
ns (7)
an
d (10
)
, th
e
ov
erall co
nv
er
si
on
rat
i
o
o
f
t
h
e
pr
o
pose
d
c
o
nv
ert
e
r i
s
deri
ve
d
as
1
1
(1
1)
Fi
gu
re
4.
C
h
a
r
act
eri
s
t
i
c
wave
fo
r
m
s o
f
th
e presen
ted conv
erter
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-86
94
I
J
PED
S
Vo
l. 6,
No
.
2,
Ju
ne 20
15
:
242
–
2
52
2
47
(a) m
ode
1
(e) M
o
de
5
(b
) m
ode
2
(f
) M
o
de
6
(c) M
o
de
3
(g
) M
o
de
7
(d
) m
ode
4
(h
) M
o
de
8
Fi
gu
re 5.
Eq
ui
val
e
nt
fo
r vari
ous
o
p
e
r
at
i
n
g
m
odes
5.
DESIG
N
SPE
C
IFI
CATI
O
N
S
The reactive el
e
m
ents (L
1
, L
2
and C
C
) a
n
d t
h
e
m
a
xim
u
m
dut
y
cy
cl
e of t
h
e pr
o
pose
d
c
o
n
v
e
rt
er can
be
desi
g
n
e
d
f
r
o
m
equat
i
o
n
(
1
1
)
a
s
1
,
(1
2)
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
PED
S
I
S
SN
:
208
8-8
6
9
4
An
Efficien
t
Hig
h
Ga
in DC
-DC Co
n
v
erter for Au
t
o
mo
tive Ap
p
lica
tion
s
(M. Prabh
a
k
a
r
)
24
8
Based on
t
h
e specified
in
ductor ripple
current
Δ
i
L1
and
Δ
i
L2
values, t
h
e inductance
values
are
deri
ved
as
∆
(1
3)
∆
1
(1
4)
Fo
r successfu
l
soft switch
i
n
g
o
f
th
e m
a
in
an
d aux
iliary switch
e
s, t
h
e energ
y
st
o
r
ed
in
th
e reson
a
n
t
in
du
ctor
L
r
sh
oul
d be
great
e
r
t
h
an e
n
er
gy
st
ore
d
i
n
res
ona
nt
capaci
t
o
r C
r
. Th
e ex
pression
relating
th
i
s
co
nd
itio
n is
d
e
riv
e
d
b
y
con
s
i
d
eri
n
g th
e
op
eratin
g
m
o
d
e
s and
is
g
i
v
e
n
b
y
(1
5)
Th
e
g
a
ting
time d
e
lay b
e
t
w
een
th
e m
a
in
an
d th
e au
x
iliary switch
is
g
i
v
e
n
b
y
2
(1
6)
From
t
h
e
kn
o
w
n C
r
v
a
lu
e,
th
e v
a
lu
e of
th
e
L
r
can
be cal
c
u
l
a
t
e
d
usi
n
g e
q
uat
i
o
n
(
1
4) a
s
≅
4
(1
7)
The
value
of cl
a
m
p capacitance is de
rive
d
from
the express
i
on
≫
1
(1
8)
6.
E
X
PERI
MEN
T
AL
RESUL
T
S
The ad
o
p
t
e
d c
o
n
v
e
r
t
e
r was
f
a
bri
cat
ed i
n
t
h
e l
a
borat
ory
a
n
d o
p
erat
e
d
f
r
o
m
an i
nput
vol
t
a
ge of
1
2
V
,
pr
o
v
i
d
e
d
an
o
u
t
put
v
o
l
t
a
ge
of
12
0
V
at
5
0
k
H
z swi
t
c
hi
n
g
f
r
e
que
ncy
an
d
del
i
vere
d an
o
u
t
p
ut
p
o
we
r
35
W.
The
v
a
lu
es of
indu
ctor
s L
1
and L
2
we
re c
o
m
put
e
d
a
n
d
de
s
i
gne
d t
o
b
e
4
71µ
H a
n
d
4m
H r
e
spect
i
v
el
y
.
T
h
e
switch
i
ng
frequ
en
cy was main
tain
ed
same as th
e res
onant
f
r
eq
ue
nc
y
.
Theref
o
r
e,
t
h
e val
u
e o
f
r
e
so
nant
i
n
d
u
ct
o
r
was
d
e
si
gne
d t
o
be
4
.
7µ
H f
o
r a
res
ona
nt
ca
paci
t
o
r wi
t
h
v
a
l
u
e
4.
7µF/
1
6
0
V
.
T
h
e val
u
e
s
of cl
a
m
p and
out
put
capaci
t
o
rs
we
re desi
g
n
ed
as 1
n
F/
1
6
0
V
an
d 1
00µ
F
/
160V res
p
ecti
v
ely. T
h
e
gate
pulses
were
obtained
by
sui
t
a
bl
y
pr
o
g
ram
m
i
ng PIC
1
8
F
4
5
k
2
0
fl
as
h m
i
crocont
rol
l
er. T
h
e p
o
w
er
de
vi
ces use
d
were
IR
FP
2
50
and
al
l
the di
odes
were MUR460
fas
t
recovery
power
diodes.
The
experim
e
nt was carried
ou
t with
a resistive
lo
ad
wh
ich
was
adju
sted
to
d
r
aw
t
h
e requ
ired
p
o
wer
at
th
e rated
v
o
ltag
e
conditio
n
.
Fig
u
re 6
sho
w
s th
e g
a
te pu
lse o
f
th
e m
a
in
switch
,
aux
iliary switch
and
th
e ou
tpu
t
vo
ltag
e
. It i
s
obs
er
ved
t
h
at
t
h
e
gat
e
pul
ses
are
pr
ovi
de
d
w
i
t
h
t
h
e
desi
re
d
dut
y
cy
cl
e a
n
d
are c
o
m
p
l
i
m
e
nt
ary
t
o
eac
h
o
t
her.
The a
v
era
g
e
o
u
t
p
ut
v
o
l
t
a
ge
obt
ai
ne
d
fr
om
t
h
e co
n
v
ert
e
r
i
s
1
0
6
V
whi
c
h
i
s
very
cl
o
s
e t
o
t
h
e
desi
gne
d
val
u
e
.
Th
e
redu
ction
in
ou
tpu
t
vo
ltag
e
is
du
e to increm
en
tal v
o
ltage
drop ac
ros
s
the i
n
duct
or
an
d
th
e sw
itches.
Th
i
s
dr
o
p
c
oul
d
be
com
p
ensat
e
d
b
y
sui
t
a
bl
y
ad
j
u
st
i
ng t
h
e
dut
y
c
y
cl
e.
Fig
u
re
7
sh
ows th
e
g
a
te pu
lses app
lied
to
main
switch
Q, aux
iliary swi
t
ch
Q
a
, th
e
voltag
e
stress
acros
s the swit
ch Q a
nd t
h
e output voltage. It is clear
that the m
a
in switch expe
riences a
voltage st
ress
whic
h
i
s
cl
ose t
o
t
h
e
out
put
v
o
l
t
a
ge.
Fi
gu
re
8
sh
o
w
s t
h
e
gat
e
p
u
l
s
es ap
pl
i
e
d
t
o
t
h
e s
w
i
t
c
hes
an
d t
h
e
vol
t
a
ge
s
t
ress e
xpe
ri
enc
e
d
by
t
h
em
.
The s
w
i
t
c
h
d
u
t
y
cy
cl
e, oper
a
t
i
ng f
r
e
que
nc
y
,
pr
o
p
er t
u
r
n
O
N
an
d t
u
r
n
OFF
o
f
bot
h
t
h
e swi
t
c
h
e
s a
n
d
t
h
e
com
p
l
i
m
e
nt
ary beha
vi
o
u
r o
f
t
h
e swi
t
c
hes ca
n be co
nfi
r
m
e
d. F
u
rt
he
r, i
t
i
s
cl
ear t
h
at
t
h
e
swi
t
c
h v
o
l
t
a
ge
st
ress
is clo
s
e to
th
e o
u
t
p
u
t
v
o
ltage. It is in
terest
in
g
to
no
tice th
at th
e vo
ltag
e
acro
ss t
h
e switch
ex
h
i
b
its ri
n
g
i
n
g
since s
n
ubber
circuits we
re
not used.
Fi
gu
re 9 s
h
ow
s t
h
e m
easured
wave
fo
rm
of gat
e
p
u
l
s
e, v
o
l
t
a
ge st
ress a
nd
cur
r
ent
st
res
s
o
f
t
h
e swi
t
c
h
Q. T
h
e m
a
gnitude
of the s
w
it
ch c
u
rr
ent is in accorda
n
ce
with
the e
xpecte
d
value
.
T
h
e zero voltage
switc
hing
(ZVS)
of th
e
main
switch
Q is shown
in
Fig
u
re
1
0
. Before th
e switch is
tu
rn
ed
ON, t
h
e switch
cu
rren
t
is
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-86
94
I
J
PED
S
Vo
l. 6,
No
.
2,
Ju
ne 20
15
:
242
–
2
52
2
49
n
e
g
a
tiv
e and
vo
ltag
e
acro
ss th
e switch
is red
u
c
ed
to
zero.
This confi
r
ms the proper
op
eration
of th
e so
ft
sw
itch
i
ng
cir
c
u
it w
h
ich
w
a
s
ad
d
e
d
t
o
th
e cascad
ed
boo
st
co
nv
er
ter
.
Figu
r
e
11
sh
ow
s t
h
e pho
tog
r
aph o
f
t
h
e
im
pl
em
ent
e
d con
v
e
r
t
e
r.
Fig
u
re
6
.
Gate
p
u
l
se of m
a
in
switch
Q, aux
iliary Q
a
an
d ou
t
p
u
t
vo
ltag
e
Fi
gu
re 7.
Gat
e
pul
ses
o
f
Q
a
n
d Q
a
,
v
o
l
t
a
ge st
ress
of
Q
an
d
o
u
t
p
ut
v
o
l
t
a
ge
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
PED
S
I
S
SN
:
208
8-8
6
9
4
An
Efficien
t
Hig
h
Ga
in DC
-DC Co
n
v
erter for Au
t
o
mo
tive Ap
p
lica
tion
s
(M. Prabh
a
k
a
r
)
25
0
Fi
gu
re 8.
Gat
e
pul
ses
an
d v
o
l
t
a
ge
st
re
sses of
swi
t
c
hes Q
a
n
d
Qa
Fi
gu
re
9.
Gat
e
pul
se
,
vol
t
a
ge
acros
s s
w
i
t
c
h
Q a
n
d
cu
rre
nt
t
h
r
o
ug
h t
h
e m
a
in s
w
i
t
c
h
Q
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-86
94
I
J
PED
S
Vo
l. 6,
No
.
2,
Ju
ne 20
15
:
242
–
2
52
2
51
Fig
u
re
11
. Zero
Vo
ltag
e
Switch
i
ng
(ZVS) of m
a
in
switch Q
Fi
gu
re 1
2
. Ph
o
t
og
rap
h
of
t
h
e
i
m
pl
em
ent
e
d
co
nve
rt
er
7.
CO
NCL
USI
O
N
Thi
s
pa
per
p
r
e
s
ent
e
d
t
h
e
anal
y
s
i
s
, desi
gn
an
d e
x
p
e
ri
m
e
nt
al ve
ri
fi
cat
i
o
n
o
f
a s
o
ft
s
w
i
t
c
he
d
DC
-
D
C
con
v
e
r
t
e
r, w
h
i
c
h was de
si
g
n
e
d fo
r aut
o
m
o
ti
ve HI
D l
a
m
p
appl
i
cat
i
o
n. T
h
e co
nve
rt
er p
r
o
v
i
d
e
d
t
h
e re
qui
red
vol
t
a
ge
gai
n
a
t
t
h
e desi
g
n
ed
po
wer l
e
vel
.
Ex
peri
m
e
nt
al
resul
t
s
pr
o
v
e t
h
e val
i
d
i
t
y
of t
h
e desi
gn
. The
m
a
i
n
d
e
sirab
l
e features o
f
th
is conv
erter are (i) its ab
ility
to
o
p
e
rate u
n
d
e
r soft switch
i
ng
co
nd
itio
n
(ii) red
u
ced
d
e
v
i
ce stress an
d
(iii) h
i
gh
vo
ltag
e
g
a
i
n
at lo
wer du
ty
ratio
. By p
r
op
er ch
o
i
ce
o
f
indu
cto
r
and
switches, th
e
requ
ired
v
o
ltage g
a
in can precisely b
e
ach
ieved
.
REFERE
NC
ES
[1]
Tseng K.C.
and
Liang
T.J
.
Novel Hi
gh
Efficiency
Step Up C
onverter
.
IEE Proc. Electro. Po
wer Appl.
2004
;
151(2): 182-190
.
[2]
Liang T.J. and Tseng K.C. An
aly
s
is of Integrated Boost-
Fly
b
ack Step-up Converter
.
IEE Pr
oc.-E
l
e
c
tr. Pow
e
r
Appl.
2005; 152(
2): 217-225.
[3]
Wai Rong-Jong, Duan Rou-Yong Duan. High Step-Up Converter with Coupled
Inductor.
IEEE Transanctions
on
Power
E
l
ec
tr
oni
cs
.
2005; 20(5):
1025-1035.
Evaluation Warning : The document was created with Spire.PDF for Python.